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arm64: dts: qcom: sm6350: change labels to lower-case

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DTS coding style expects labels to be lowercase.  No functional impact.
Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff).

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241022-dts-qcom-label-v3-8-0505bc7d2c56@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Krzysztof Kozlowski
2024-10-22 19:14:34 -05:00
committed by Bjorn Andersson
parent dfe312b825
commit b0864ab227
2 changed files with 103 additions and 103 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm64/boot/dts/qcom/sm6350.dtsi
+95 -95
View File
@@ -45,7 +45,7 @@
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "qcom,kryo560";
reg = <0x0 0x0>;
@@ -53,21 +53,21 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
&clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD0>;
power-domains = <&cpu_pd0>;
power-domain-names = "psci";
#cooling-cells = <2>;
L2_0: l2-cache {
l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
next-level-cache = <&l3_0>;
l3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
@@ -75,7 +75,7 @@
};
};
CPU1: cpu@100 {
cpu1: cpu@100 {
device_type = "cpu";
compatible = "qcom,kryo560";
reg = <0x0 0x100>;
@@ -83,24 +83,24 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_100>;
next-level-cache = <&l2_100>;
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
&clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD1>;
power-domains = <&cpu_pd1>;
power-domain-names = "psci";
#cooling-cells = <2>;
L2_100: l2-cache {
l2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU2: cpu@200 {
cpu2: cpu@200 {
device_type = "cpu";
compatible = "qcom,kryo560";
reg = <0x0 0x200>;
@@ -108,24 +108,24 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_200>;
next-level-cache = <&l2_200>;
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
&clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD2>;
power-domains = <&cpu_pd2>;
power-domain-names = "psci";
#cooling-cells = <2>;
L2_200: l2-cache {
l2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU3: cpu@300 {
cpu3: cpu@300 {
device_type = "cpu";
compatible = "qcom,kryo560";
reg = <0x0 0x300>;
@@ -133,24 +133,24 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_300>;
next-level-cache = <&l2_300>;
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
&clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD3>;
power-domains = <&cpu_pd3>;
power-domain-names = "psci";
#cooling-cells = <2>;
L2_300: l2-cache {
l2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU4: cpu@400 {
cpu4: cpu@400 {
device_type = "cpu";
compatible = "qcom,kryo560";
reg = <0x0 0x400>;
@@ -158,24 +158,24 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_400>;
next-level-cache = <&l2_400>;
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
&clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD4>;
power-domains = <&cpu_pd4>;
power-domain-names = "psci";
#cooling-cells = <2>;
L2_400: l2-cache {
l2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU5: cpu@500 {
cpu5: cpu@500 {
device_type = "cpu";
compatible = "qcom,kryo560";
reg = <0x0 0x500>;
@@ -183,24 +183,24 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_500>;
next-level-cache = <&l2_500>;
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
&clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD5>;
power-domains = <&cpu_pd5>;
power-domain-names = "psci";
#cooling-cells = <2>;
L2_500: l2-cache {
l2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU6: cpu@600 {
cpu6: cpu@600 {
device_type = "cpu";
compatible = "qcom,kryo560";
reg = <0x0 0x600>;
@@ -208,24 +208,24 @@
enable-method = "psci";
capacity-dmips-mhz = <1894>;
dynamic-power-coefficient = <703>;
next-level-cache = <&L2_600>;
next-level-cache = <&l2_600>;
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu6_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
&clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD6>;
power-domains = <&cpu_pd6>;
power-domain-names = "psci";
#cooling-cells = <2>;
L2_600: l2-cache {
l2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU7: cpu@700 {
cpu7: cpu@700 {
device_type = "cpu";
compatible = "qcom,kryo560";
reg = <0x0 0x700>;
@@ -233,61 +233,61 @@
enable-method = "psci";
capacity-dmips-mhz = <1894>;
dynamic-power-coefficient = <703>;
next-level-cache = <&L2_700>;
next-level-cache = <&l2_700>;
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu6_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
&clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD7>;
power-domains = <&cpu_pd7>;
power-domain-names = "psci";
#cooling-cells = <2>;
L2_700: l2-cache {
l2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
cpu = <&cpu0>;
};
core1 {
cpu = <&CPU1>;
cpu = <&cpu1>;
};
core2 {
cpu = <&CPU2>;
cpu = <&cpu2>;
};
core3 {
cpu = <&CPU3>;
cpu = <&cpu3>;
};
core4 {
cpu = <&CPU4>;
cpu = <&cpu4>;
};
core5 {
cpu = <&CPU5>;
cpu = <&cpu5>;
};
core6 {
cpu = <&CPU6>;
cpu = <&cpu6>;
};
core7 {
cpu = <&CPU7>;
cpu = <&cpu7>;
};
};
};
domain-idle-states {
CLUSTER_SLEEP_PC: cluster-sleep-0 {
cluster_sleep_pc: cluster-sleep-0 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x41000044>;
entry-latency-us = <2752>;
@@ -295,7 +295,7 @@
min-residency-us = <6118>;
};
CLUSTER_SLEEP_CX_RET: cluster-sleep-1 {
cluster_sleep_cx_ret: cluster-sleep-1 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x41001244>;
entry-latency-us = <3638>;
@@ -303,7 +303,7 @@
min-residency-us = <8467>;
};
CLUSTER_AOSS_SLEEP: cluster-sleep-2 {
cluster_aoss_sleep: cluster-sleep-2 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x4100b244>;
entry-latency-us = <3263>;
@@ -315,7 +315,7 @@
cpu_idle_states: idle-states {
entry-method = "psci";
LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
little_cpu_sleep_0: cpu-sleep-0-0 {
compatible = "arm,idle-state";
idle-state-name = "little-power-collapse";
arm,psci-suspend-param = <0x40000003>;
@@ -325,7 +325,7 @@
local-timer-stop;
};
LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
little_cpu_sleep_1: cpu-sleep-0-1 {
compatible = "arm,idle-state";
idle-state-name = "little-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
@@ -335,7 +335,7 @@
local-timer-stop;
};
BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
big_cpu_sleep_0: cpu-sleep-1-0 {
compatible = "arm,idle-state";
idle-state-name = "big-power-collapse";
arm,psci-suspend-param = <0x40000003>;
@@ -345,7 +345,7 @@
local-timer-stop;
};
BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
big_cpu_sleep_1: cpu-sleep-1-1 {
compatible = "arm,idle-state";
idle-state-name = "big-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
@@ -504,59 +504,59 @@
compatible = "arm,psci-1.0";
method = "smc";
CPU_PD0: power-domain-cpu0 {
cpu_pd0: power-domain-cpu0 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
};
CPU_PD1: power-domain-cpu1 {
cpu_pd1: power-domain-cpu1 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
};
CPU_PD2: power-domain-cpu2 {
cpu_pd2: power-domain-cpu2 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
};
CPU_PD3: power-domain-cpu3 {
cpu_pd3: power-domain-cpu3 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
};
CPU_PD4: power-domain-cpu4 {
cpu_pd4: power-domain-cpu4 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
};
CPU_PD5: power-domain-cpu5 {
cpu_pd5: power-domain-cpu5 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
};
CPU_PD6: power-domain-cpu6 {
cpu_pd6: power-domain-cpu6 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
};
CPU_PD7: power-domain-cpu7 {
cpu_pd7: power-domain-cpu7 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
};
CLUSTER_PD: power-domain-cpu-cluster0 {
cluster_pd: power-domain-cpu-cluster0 {
#power-domain-cells = <0>;
domain-idle-states = <&CLUSTER_SLEEP_PC
&CLUSTER_SLEEP_CX_RET
&CLUSTER_AOSS_SLEEP>;
domain-idle-states = <&cluster_sleep_pc
&cluster_sleep_cx_ret
&cluster_aoss_sleep>;
};
};
@@ -2777,7 +2777,7 @@
qcom,drv-id = <2>;
qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
<WAKE_TCS 3>, <CONTROL_TCS 1>;
power-domains = <&CLUSTER_PD>;
power-domains = <&cluster_pd>;
rpmhcc: clock-controller {
compatible = "qcom,sm6350-rpmh-clk";
@@ -2954,7 +2954,7 @@
cooling-maps {
map0 {
trip = <&cpu0_alert0>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@@ -2979,7 +2979,7 @@
cooling-maps {
map0 {
trip = <&cpu1_alert0>;
cooling-device = <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@@ -3004,7 +3004,7 @@
cooling-maps {
map0 {
trip = <&cpu2_alert0>;
cooling-device = <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@@ -3029,7 +3029,7 @@
cooling-maps {
map0 {
trip = <&cpu3_alert0>;
cooling-device = <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@@ -3054,7 +3054,7 @@
cooling-maps {
map0 {
trip = <&cpu4_alert0>;
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@@ -3079,7 +3079,7 @@
cooling-maps {
map0 {
trip = <&cpu5_alert0>;
cooling-device = <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@@ -3104,7 +3104,7 @@
cooling-maps {
map0 {
trip = <&cpu6_left_alert0>;
cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@@ -3129,7 +3129,7 @@
cooling-maps {
map0 {
trip = <&cpu6_right_alert0>;
cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@@ -3154,7 +3154,7 @@
cooling-maps {
map0 {
trip = <&cpu7_left_alert0>;
cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@@ -3179,7 +3179,7 @@
cooling-maps {
map0 {
trip = <&cpu7_right_alert0>;
cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
arch/arm64/boot/dts/qcom/sm7225.dtsi
+8 -8
View File
@@ -6,14 +6,14 @@
#include "sm6350.dtsi"
/* SM7225 uses Kryo 570 instead of Kryo 560 */
&CPU0 { compatible = "qcom,kryo570"; };
&CPU1 { compatible = "qcom,kryo570"; };
&CPU2 { compatible = "qcom,kryo570"; };
&CPU3 { compatible = "qcom,kryo570"; };
&CPU4 { compatible = "qcom,kryo570"; };
&CPU5 { compatible = "qcom,kryo570"; };
&CPU6 { compatible = "qcom,kryo570"; };
&CPU7 { compatible = "qcom,kryo570"; };
&cpu0 { compatible = "qcom,kryo570"; };
&cpu1 { compatible = "qcom,kryo570"; };
&cpu2 { compatible = "qcom,kryo570"; };
&cpu3 { compatible = "qcom,kryo570"; };
&cpu4 { compatible = "qcom,kryo570"; };
&cpu5 { compatible = "qcom,kryo570"; };
&cpu6 { compatible = "qcom,kryo570"; };
&cpu7 { compatible = "qcom,kryo570"; };
&cpu0_opp_table {
opp-1804800000 {