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merge into: OERV-BSP/u-boot:k3-dev
Branches Tags
OERV-BSP/u-boot:master OERV-BSP/u-boot:k3-dev OERV-BSP/u-boot:dev ChuanN-sudo/u-boot:k3-dev ChuanN-sudo/u-boot:dev ChuanN-sudo/u-boot:k3-qspi-dev ChuanN-sudo/u-boot:k3-clk-dev ChuanN-sudo/u-boot:master
..
pull from: ChuanN-sudo/u-boot:k3-qspi-dev
Branches Tags
ChuanN-sudo/u-boot:k3-dev ChuanN-sudo/u-boot:dev ChuanN-sudo/u-boot:k3-qspi-dev ChuanN-sudo/u-boot:k3-clk-dev ChuanN-sudo/u-boot:master OERV-BSP/u-boot:master OERV-BSP/u-boot:k3-dev OERV-BSP/u-boot:dev
12 Commits
k3-dev .. k3-qspi-dev
Author SHA1 Message Date
ChuanN-sudo f195148f79 riscv: dts: k3: add QSPI node and board support 
Add the QSPI controller node and the related board-level device
tree support needed for booting from QSPI.

Also add a compatible entry and controller data of fsl_qspi for the
SpacemiT K3 QSPI controller.

Signed-off-by: Jichuan Feng <jichuan.or@isrc.iscas.ac.cn>
 2026-05-09 10:33:27 +08:00
ChuanN-sudo d3f640bbe6 spi: fsl_qspi: add K3 clock handling 
Add support for the clocks used by the SpacemiT K3 QSPI
controller by retrieving and enabling the qspi_en and qspi
clocks during probe.
 2026-05-09 10:33:24 +08:00
ChuanN-sudo a3a71f6803 riscv: dts: k3: add bootph-all to clock nodes 
Add `bootph-all` to the clock controller related nodes so the
required clock data is available during early boot.

Signed-off-by: Chuan <fjchuanil@gmail.com>
 2026-05-09 10:33:19 +08:00
zzSunil f44fc1cd47 board: spacemit-k3: Add ccu driver to support spl related clocks 2026-03-31 16:07:56 +08:00
zzSunil 2a7c1757d8 board: spacemit-k3: Add new dts file for BUILD_TYPE_SPL 2026-03-31 16:07:56 +08:00
SalimTerryLi c96a91b51a board: spacemit-k3: Add support for boot console and its pinctrl 
First usable state reached: SPL booted and console printed
 2026-03-27 18:40:31 +08:00
SalimTerryLi f9d1375854 board: spacemit-k3: SPL entrypoint 2026-03-27 18:40:26 +08:00
SalimTerryLi efdd9326a2 board: spacemit-k3: BROM loadable SPL build 
bootinfo.bin generation is added but not implemented
 2026-03-04 15:26:33 +08:00
SalimTerryLi c432453da6 board: spacemit-k3: enable FIT 2026-03-04 15:26:10 +08:00
SalimTerryLi 75ba4f42c1 board: spacemit-k3: BINMAN skeleton 2026-03-04 15:26:02 +08:00
SalimTerryLi 7bf984bee7 board: spacemit-k3: SPL skeleton 2026-03-04 15:25:51 +08:00
SalimTerryLi 1b58103415 board: spacemit-k3: skeleton support 2026-03-04 15:25:18 +08:00
8723 changed files with 177378 additions and 468970 deletions
Expand all files Collapse all files
.azure-pipelines.yml
+30 -33
View File
@@ -2,7 +2,7 @@ variables:
windows_vm: windows-2022
ubuntu_vm: ubuntu-24.04
macos_vm: macOS-14
ci_runner_image: trini/u-boot-gitlab-ci-runner:noble-20251013-23Jan2026
ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20251013-26Nov2025
# Ensure we do a shallow clone
Agent.Source.Git.ShallowFetchDepth: 1
# Add '-u 0' options for Azure pipelines, otherwise we get "permission
@@ -128,8 +128,8 @@ stages:
- script: |
./tools/buildman/buildman --maintainer-check
- job: allyesconfig_and_tools
displayName: 'Ensure allyesconfig, tools-only and envtools build'
- job: tools_only
displayName: 'Ensure host tools and env tools build'
pool:
vmImage: $(ubuntu_vm)
container:
@@ -137,34 +137,29 @@ stages:
options: $(container_option)
steps:
- script: |
# Allow pipefail because of how we use 'yes' here.
set +o pipefail;
yes 0 | make allyesconfig oldconfig all -j$(nproc)
make mrproper
make tools-only_config tools-only -j$(nproc)
make mrproper
make tools-only_config envtools -j$(nproc)
- job: utils
displayName: 'Run binman, buildman, dtoc and Kconfig testsuites'
displayName: 'Run binman, buildman, dtoc, Kconfig and patman testsuites'
pool:
vmImage: $(ubuntu_vm)
container:
image: $(ci_runner_image)
options: $(container_option)
steps:
- script: |
# Configure git
cat << "EOF" > build.sh
cd $(work_dir)
git config --global user.name "Azure Pipelines"
git config --global user.email bmeng.cn@gmail.com
git config --global --add safe.directory $(work_dir)
export USER=azure
python3 -m venv /tmp/venv
. /tmp/venv/bin/activate
pip install -r test/py/requirements.txt \
-r tools/binman/requirements.txt \
-r tools/buildman/requirements.txt \
-r tools/u_boot_pylib/requirements.txt \
-r scripts/dtc/pylibfdt/requirements.txt
-r tools/patman/requirements.txt \
-r tools/u_boot_pylib/requirements.txt
export UBOOT_TRAVIS_BUILD_DIR=/tmp/tools-only
export PYTHONPATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt
export PATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}
@@ -177,7 +172,13 @@ stages:
COVERAGE_FILE=/tmp/.coverage ./tools/binman/binman ${TOOLPATH} test -T
./tools/buildman/buildman -t
./tools/dtoc/dtoc -t
./tools/patman/patman test
make O=${UBOOT_TRAVIS_BUILD_DIR} testconfig
EOF
cat build.sh
# We cannot use "container" like other jobs above, as buildman
# seems to hang forever with pre-configured "container" environment
docker run -v $PWD:$(work_dir) $(ci_runner_image) /bin/bash $(work_dir)/build.sh
- job: pylint
displayName: Check for any pylint regressions
@@ -195,8 +196,8 @@ stages:
pip install -r test/py/requirements.txt \
-r tools/binman/requirements.txt \
-r tools/buildman/requirements.txt \
-r tools/patman/requirements.txt \
-r tools/u_boot_pylib/requirements.txt \
-r scripts/dtc/pylibfdt/requirements.txt \
asteval pylint==3.3.4 pyopenssl
export PATH=${PATH}:~/.local/bin
echo "[MASTER]" >> .pylintrc
@@ -311,7 +312,6 @@ stages:
-r tools/buildman/requirements.txt \
-r test/py/requirements.txt \
-r tools/u_boot_pylib/requirements.txt \
setuptools \
pytest-azurepipelines
tools/buildman/buildman -o \${UBOOT_TRAVIS_BUILD_DIR} -w -E -W -e --board \${TEST_PY_BD} \${OVERRIDE}
cp /opt/grub/grub_x86.efi \${UBOOT_TRAVIS_BUILD_DIR}/
@@ -391,26 +391,22 @@ stages:
sandbox:
TEST_PY_BD: "sandbox"
TEST_PY_EXTRA: "--timing"
# addr2line in Ubuntu 'Noble' and later are broken.
TEST_PY_TEST_SPEC: "not event_dump"
sandbox_asan:
TEST_PY_BD: "sandbox"
OVERRIDE: "-a ASAN"
TEST_PY_TEST_SPEC: "version"
sandbox_clang:
TEST_PY_BD: "sandbox"
OVERRIDE: "-O clang-20"
# addr2line in Ubuntu 'Noble' and later are broken.
TEST_PY_TEST_SPEC: "not event_dump"
OVERRIDE: "-O clang-18"
sandbox_clang_asan:
TEST_PY_BD: "sandbox"
OVERRIDE: "-O clang-20 -a ASAN"
OVERRIDE: "-O clang-18 -a ASAN"
TEST_PY_TEST_SPEC: "version"
sandbox64:
TEST_PY_BD: "sandbox64"
sandbox64_clang:
TEST_PY_BD: "sandbox64"
OVERRIDE: "-O clang-20"
OVERRIDE: "-O clang-18"
sandbox64_lwip:
TEST_PY_BD: "sandbox64_lwip"
sandbox_spl:
@@ -507,7 +503,6 @@ stages:
qemu_arm64:
TEST_PY_BD: "qemu_arm64"
TEST_PY_TEST_SPEC: "not sleep"
OVERRIDE: "-a CONFIG_SEMIHOSTING=y"
qemu_arm64_lwip:
TEST_PY_BD: "qemu_arm64_lwip"
TEST_PY_TEST_SPEC: "test_net_dhcp or test_net_ping or test_net_tftpboot"
@@ -523,9 +518,6 @@ stages:
TEST_PY_ID: "--id qemu"
TEST_PY_TEST_SPEC: "not sleep and not efi"
OVERRIDE: "-a CONFIG_M68K_QEMU=y -a ~CONFIG_MCFTMR"
qemu_m68k_virt:
TEST_PY_BD: "qemu-m68k"
TEST_PY_TEST_SPEC: "not sleep"
qemu_malta:
TEST_PY_BD: "malta"
TEST_PY_ID: "--id qemu"
@@ -660,9 +652,6 @@ stages:
displayName: 'Build the World'
pool:
vmImage: $(ubuntu_vm)
container:
image: $(ci_runner_image)
options: $(container_option)
strategy:
# We split the world up in to 10 jobs as we can have at most 10
# parallel jobs going on the free tier of Azure.
@@ -727,13 +716,18 @@ stages:
BUILDMAN: $(aarch64_catch_all)
steps:
- script: |
cat << EOF > build.sh
set -ex
# Setup venv, perform build
cd ${WORK_DIR}
# make environment variables available as tests are running inside a container
export BUILDMAN="${BUILDMAN}"
git config --global --add safe.directory ${WORK_DIR}
python3 -m venv /tmp/venv
. /tmp/venv/bin/activate
pip install -r tools/binman/requirements.txt \
-r tools/buildman/requirements.txt \
setuptools
-r tools/buildman/requirements.txt
EOF
cat << "EOF" >> build.sh
if [[ "${BUILDMAN}" != "" ]]; then
ret=0;
tools/buildman/buildman -o /tmp -PEWM ${BUILDMAN} ${OVERRIDE} || ret=$?;
@@ -742,3 +736,6 @@ stages:
exit $ret;
fi;
fi
EOF
cat build.sh
docker run -v $PWD:$(work_dir) $(ci_runner_image) /bin/bash $(work_dir)/build.sh
.b4-config
-5
View File
@@ -4,8 +4,3 @@
[b4]
send-auto-to-cmd = scripts/get_maintainer.pl --nogit --nogit-fallback --nogit-chief-penguins --norolestats --nom
send-auto-cc-cmd = scripts/get_maintainer.pl --nogit-fallback --nogit-chief-penguins --norolestats --nol
# Patchwork integration. You still need to set pw-key to your API key
pw-url = https://patchwork.ozlabs.org/
pw-project = uboot
pw-review-state = under-review
pw-accept-state = accepted
.clang-format
-51
View File
@@ -748,57 +748,6 @@ ForEachMacros:
- 'ynl_attr_for_each_nested'
- 'ynl_attr_for_each_payload'
- 'zorro_for_each_dev'
# U-Boot specific
- '__for_each_child_of_node'
- '__usbhs_for_each_pipe'
- '__usbhsg_for_each_uep'
- '_for_each_zynqmp_part'
- 'alist_for_each'
- 'alist_for_each_filter'
- 'cvmx_coremask_for_each_core'
- 'cvmx_coremask_for_each_node'
- 'dev_for_each_property'
- 'dev_for_each_subnode'
- 'expr_list_for_each_sym'
- 'fdt_for_each_node_by_compatible'
- 'fdt_for_each_property_offset'
- 'fdt_for_each_subnode'
- 'for_each_bin_hdr_v0'
- 'for_each_bl_params_node'
- 'for_each_child_withdel'
- 'for_each_console_dev'
- 'for_each_ext_hdr_v0'
- 'for_each_label'
- 'for_each_label_withdel'
- 'for_each_marker'
- 'for_each_marker_of_type'
- 'for_each_memory_map_entry_reversed'
- 'for_each_mmc_mode_by_pref'
- 'for_each_opt_hdr_v1'
- 'for_each_property_withdel'
- 'for_each_sd_mode_by_pref'
- 'for_each_supported_width'
- 'for_each_tpm_device'
- 'for_each_w1_device'
- 'for_each_zynqmp_image'
- 'for_each_zynqmp_part'
- 'for_each_zynqmp_part_in_image'
- 'mtd_for_each_device'
- 'ofnode_for_each_compatible_node'
- 'ofnode_for_each_prop'
- 'ofnode_for_each_subnode'
- 'pko_for_each_port'
- 'sfi_for_each_mentry'
- 'ubi_for_each_free_peb'
- 'ubi_for_each_protected_peb'
- 'ubi_for_each_scrub_peb'
- 'ubi_for_each_used_peb'
- 'ubi_rb_for_each_entry'
- 'usbhs_for_each_dfifo'
- 'usbhs_for_each_pipe'
- 'usbhs_for_each_pipe_with_dcp'
- 'usbhsg_for_each_uep'
- 'usbhsg_for_each_uep_with_dcp'
IncludeBlocks: Preserve
IncludeCategories:
.gitignore
+1 -5
View File
@@ -16,9 +16,6 @@
*.dtb
*.dtbo
*.dtb.S
*.dtb.clean.dts
*.dtb.diff
*.dtb.full.dts
*.elf
*.exe
*.fit
@@ -73,7 +70,6 @@ fit-dtb.blob*
#
/spl/
/tpl/
/vpl/
/defconfig
/generated_defconfig
/Test*
@@ -83,7 +79,7 @@ fit-dtb.blob*
/*imx8mimage*
/*imx8mcst*
/*rcar4-sa0*
/drivers/video/u_boot_logo.bmp.S
/drivers/video/u_boot_logo.S
/test/fdt_overlay/test-fdt-overlay-stacked.dtbo.S
/test/fdt_overlay/test-fdt-overlay.dtbo.S
capsule_esl_file
.gitlab-ci-sage-lab.yml
-213
View File
@@ -1,213 +0,0 @@
# Definition for the lab connected to the "sage" host and managed with labgrid
.sage_lab_template: &sage_lab_dfn
stage: sage-lab
rules:
- if: $SAGE_LAB == "1"
when: always
- if: $SAGE_LAB != "1"
when: manual
allow_failure: true
# USB can be unreliable.
retry: 2
dependencies: []
needs: [ "sandbox test.py" ]
tags: [ 'konsulko-sage-labgrid' ]
before_script:
# Clone uboot-test-hooks
- git config --global --add safe.directory "${CI_PROJECT_DIR}"
- git clone --depth=1 https://source.denx.de/u-boot/u-boot-test-hooks /tmp/uboot-test-hooks
- ln -s sage /tmp/uboot-test-hooks/bin/`hostname`
- ln -s sage /tmp/uboot-test-hooks/py/`hostname`
- export LG_ENV="/tmp/uboot-test-hooks/bin/sage/labgrid-sage-env.yaml";
export LG_COORDINATOR=172.17.0.1:20408
# Prepare python environment
- python3 -m venv /tmp/venv;
. /tmp/venv/bin/activate;
pip install -r test/py/requirements.txt -r tools/binman/requirements.txt
-r tools/buildman/requirements.txt -r tools/u_boot_pylib/requirements.txt
labgrid==25.0.1 setuptools
# Acquire and turn on the exporter.
- labgrid-client reserve --wait board=${LABGRID_EXPORTER} &&
labgrid-client -p ${LABGRID_EXPORTER} acquire &&
labgrid-client -p ${LABGRID_EXPORTER} power on
# Prepare ssh
- mkdir --mode=0700 ~/.ssh;
printf 'Host sage-exporter-*\n\tUser labgrid\n' > ~/.ssh/config
# If we have TF-A binaries, we need to use them.
- if [[ -d /opt/tf-a/${TEST_PY_BD}${TEST_PY_ID//--id /_} ]]; then
cp /opt/tf-a/${TEST_PY_BD}${TEST_PY_ID//--id /_}/* /tmp/;
elif [[ -d /opt/tf-a/${TEST_PY_BD} ]]; then
cp /opt/tf-a/${TEST_PY_BD}/* /tmp/;
fi;
export BINMAN_INDIRS=/tmp;
script:
- export UBOOT_TRAVIS_BUILD_DIR=/tmp/${TEST_PY_BD}
# Don't stop on non-zero exit codes now, to provide as much chance as
# possible to ensure we don't leave lab resources acquired.
- set +e;
# Sage is 16 threads and has 4 devices attached, so 4 builder threads.
- tools/buildman/buildman -o ${UBOOT_TRAVIS_BUILD_DIR} -w -E -W -e
--board ${TEST_PY_BD} ${OVERRIDE} -T 4;
RC=`echo $?`;
# Wait for the exporter to have the device ready
- while test `labgrid-client resources |
grep -q ${LABGRID_EXPORTER}/${LG_PLACE}/; echo $?` -ne 0; do sleep 1;
done
# Fingerprint the exporter
- ssh-keyscan ${LABGRID_EXPORTER} > ~/.ssh/known_hosts 2>/dev/null
# If we built, run the tests and save the results.
- export PATH=/tmp/uboot-test-hooks/bin:${PATH};
export PYTHONPATH=/tmp/uboot-test-hooks/py/sage;
test $RC -eq 0 && labgrid-client reserve --wait board=${LG_PLACE} &&
labgrid-client -p ${LG_PLACE} acquire &&
./test/py/test.py -ra --bd ${TEST_PY_BD} ${TEST_PY_ID}
${TEST_PY_EXTRA:-"--capture=tee-sys"}
${TEST_PY_TEST_SPEC:+"-k ${TEST_PY_TEST_SPEC}"}
--build-dir "$UBOOT_TRAVIS_BUILD_DIR"
--junitxml=/tmp/${TEST_PY_BD}/results.xml;
RC=`echo $?`;
cp -v /tmp/${TEST_PY_BD}/*.{html,css,xml} .;
# Release and power off everything.
- labgrid-client -p ${LG_PLACE} power off
- labgrid-client -p ${LG_PLACE} release
- labgrid-client -p ${LABGRID_EXPORTER} ssh sudo poweroff && sleep 15 &&
labgrid-client -p ${LABGRID_EXPORTER} power off
- labgrid-client -p ${LABGRID_EXPORTER} release
- exit $RC
artifacts:
when: always
paths:
- "*.html"
- "*.css"
- results.xml
reports:
junit: results.xml
expire_in: 1 week
BeagleBone Black:
<<: *sage_lab_dfn
variables:
LABGRID_EXPORTER: "sage-exporter-bbb-1"
LG_PLACE: "bbb-1"
TEST_PY_BD: "am335x_evm"
OVERRIDE: "-a CMD_BOOTMENU -a CMD_LOG -a CMD_BOOTEFI_HELLO -a CMD_BOOTEFI_SELFTEST"
BeagleBone Black (lwIP):
<<: *sage_lab_dfn
needs: [ "BeagleBone Black" ]
variables:
LABGRID_EXPORTER: "sage-exporter-bbb-1"
LG_PLACE: "bbb-1"
TEST_PY_BD: "am335x_evm"
OVERRIDE: "-a CMD_BOOTMENU -a CMD_LOG -a CMD_BOOTEFI_HELLO -a CMD_BOOTEFI_SELFTEST -a NET_LWIP"
Pine64+:
<<: *sage_lab_dfn
variables:
LABGRID_EXPORTER: "sage-exporter-pine64-1"
LG_PLACE: "pine64-1"
TEST_PY_BD: "pine64_plus"
OVERRIDE: "-a CMD_BOOTMENU -a CMD_LOG"
Pine64+ (lwIP):
<<: *sage_lab_dfn
needs: [ "Pine64+" ]
variables:
LABGRID_EXPORTER: "sage-exporter-pine64-1"
LG_PLACE: "pine64-1"
TEST_PY_BD: "pine64_plus"
# Leads to crash on lwIP, needs investigation.
TEST_PY_TEST_SPEC: "not test_net_pxe_boot_config"
OVERRIDE: "-a CMD_BOOTMENU -a CMD_LOG -a NET_LWIP"
SolidRun Hummingboard 2:
<<: *sage_lab_dfn
variables:
LABGRID_EXPORTER: "sage-exporter-hb-1"
LG_PLACE: "hb-1"
TEST_PY_BD: "mx6cuboxi"
OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG"
SolidRun Hummingboard 2 (lwIP):
<<: *sage_lab_dfn
needs: [ "SolidRun Hummingboard 2" ]
variables:
LABGRID_EXPORTER: "sage-exporter-hb-1"
LG_PLACE: "hb-1"
TEST_PY_BD: "mx6cuboxi"
OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a NET_LWIP"
Raspberry Pi 4:
<<: *sage_lab_dfn
variables:
LABGRID_EXPORTER: "sage-exporter-rpi4-1"
LG_PLACE: "rpi4-1"
TEST_PY_BD: "rpi_4"
OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a ~CMD_BOOTEFI_SELFTEST -a CMD_TFTPPUT -a FIT -a FIT_SIGNATURE -a FIT_BEST_MATCH -a SYS_BOOTM_LEN=0x4000000 -a BOOTSTAGE -a BOOTSTAGE_STASH -a CMD_BOOTSTAGE -a BOOTSTAGE_STASH_ADDR=0x02400000"
Raspberry Pi 4 (rpi_arm64):
<<: *sage_lab_dfn
needs: [ "Raspberry Pi 4" ]
variables:
LABGRID_EXPORTER: "sage-exporter-rpi4-1"
LG_PLACE: "rpi4-1"
TEST_PY_BD: "rpi_arm64"
# DHCP is not being run first, needs to be investigated.
TEST_PY_TEST_SPEC: "not test_efi_helloworld_net_http"
OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a ~CMD_BOOTEFI_SELFTEST -a FIT -a FIT_SIGNATURE -a FIT_BEST_MATCH -a SYS_BOOTM_LEN=0x4000000 -a BOOTSTAGE -a BOOTSTAGE_STASH -a CMD_BOOTSTAGE -a BOOTSTAGE_STASH_ADDR=0x02400000"
Raspberry Pi 4 (rpi_4_32b):
<<: *sage_lab_dfn
needs: [ "Raspberry Pi 4 (rpi_arm64)" ]
variables:
LABGRID_EXPORTER: "sage-exporter-rpi4-1"
LG_PLACE: "rpi4-1"
TEST_PY_BD: "rpi_4_32b"
OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a CMD_BOOTEFI_SELFTEST -a CMD_TFTPPUT -a FIT -a FIT_SIGNATURE -a FIT_BEST_MATCH -a SYS_BOOTM_LEN=0x4000000 -a BOOTSTAGE -a BOOTSTAGE_STASH -a CMD_BOOTSTAGE -a BOOTSTAGE_STASH_ADDR=0x02400000"
Raspberry Pi 4 (rpi_4_32b, lwIP):
<<: *sage_lab_dfn
needs: [ "Raspberry Pi 4 (rpi_4_32b)" ]
variables:
LABGRID_EXPORTER: "sage-exporter-rpi4-1"
LG_PLACE: "rpi4-1"
TEST_PY_BD: "rpi_4_32b"
OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a CMD_BOOTEFI_SELFTEST -a FIT -a FIT_SIGNATURE -a FIT_BEST_MATCH -a SYS_BOOTM_LEN=0x4000000 -a BOOTSTAGE -a BOOTSTAGE_STASH -a CMD_BOOTSTAGE -a BOOTSTAGE_STASH_ADDR=0x02400000 -a NET_LWIP"
Raspberry Pi 3:
<<: *sage_lab_dfn
variables:
LABGRID_EXPORTER: "sage-exporter-rpi3-1"
LG_PLACE: "rpi3-1"
TEST_PY_BD: "rpi_3"
OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a CMD_BOOTEFI_SELFTEST -a CMD_TFTPPUT -a FIT -a FIT_SIGNATURE -a FIT_BEST_MATCH -a SYS_BOOTM_LEN=0x4000000 -a BOOTSTAGE -a BOOTSTAGE_STASH -a CMD_BOOTSTAGE -a BOOTSTAGE_STASH_ADDR=0x02400000"
Raspberry Pi 3 (rpi_arm64):
<<: *sage_lab_dfn
needs: [ "Raspberry Pi 3" ]
variables:
LABGRID_EXPORTER: "sage-exporter-rpi3-1"
LG_PLACE: "rpi3-1"
TEST_PY_BD: "rpi_arm64"
# DHCP is not being run first, needs to be investigated.
TEST_PY_TEST_SPEC: "not test_efi_helloworld_net_http"
OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a ~CMD_BOOTEFI_SELFTEST -a FIT -a FIT_SIGNATURE -a FIT_BEST_MATCH -a SYS_BOOTM_LEN=0x4000000 -a BOOTSTAGE -a BOOTSTAGE_STASH -a CMD_BOOTSTAGE -a BOOTSTAGE_STASH_ADDR=0x02400000"
Raspberry Pi 3 (rpi_3_32b):
<<: *sage_lab_dfn
needs: [ "Raspberry Pi 3 (rpi_arm64)" ]
variables:
LABGRID_EXPORTER: "sage-exporter-rpi3-1"
LG_PLACE: "rpi3-1"
TEST_PY_BD: "rpi_3_32b"
OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a CMD_BOOTEFI_SELFTEST -a CMD_TFTPPUT -a FIT -a FIT_SIGNATURE -a FIT_BEST_MATCH -a SYS_BOOTM_LEN=0x4000000 -a BOOTSTAGE -a BOOTSTAGE_STASH -a CMD_BOOTSTAGE -a BOOTSTAGE_STASH_ADDR=0x02400000"
Raspberry Pi 3 (rpi_3_32b, lwIP):
<<: *sage_lab_dfn
needs: [ "Raspberry Pi 3 (rpi_3_32b)" ]
variables:
LABGRID_EXPORTER: "sage-exporter-rpi3-1"
LG_PLACE: "rpi3-1"
TEST_PY_BD: "rpi_3_32b"
OVERRIDE: "-a UNIT_TEST -a ~CMD_EFIDEBUG -a CMD_BOOTMENU -a CMD_LOG -a CMD_BOOTEFI_SELFTEST -a FIT -a FIT_SIGNATURE -a FIT_BEST_MATCH -a SYS_BOOTM_LEN=0x4000000 -a BOOTSTAGE -a BOOTSTAGE_STASH -a CMD_BOOTSTAGE -a BOOTSTAGE_STASH_ADDR=0x02400000 -a NET_LWIP"
.gitlab-ci.yml
+13 -36
View File
@@ -5,7 +5,6 @@ variables:
DEFAULT_AMD64_TAG: "amd64"
DEFAULT_FAST_TAG: "fast"
MIRROR_DOCKER: docker.io
SAGE_LAB: ""
SJG_LAB: ""
PLATFORM: linux/amd64,linux/arm64
@@ -19,20 +18,19 @@ workflow:
# Grab our configured image. The source for this is found
# in the u-boot tree at tools/docker/Dockerfile
image: ${MIRROR_DOCKER}/trini/u-boot-gitlab-ci-runner:noble-20251013-23Jan2026
image: ${MIRROR_DOCKER}/trini/u-boot-gitlab-ci-runner:jammy-20251013-26Nov2025
# We run some tests in different order, to catch some failures quicker.
stages:
- testsuites
- test.py
- sage-lab
- sjg-lab
- world build
.buildman_and_testpy_template: &buildman_and_testpy_dfn
stage: test.py
retry: 2 # QEMU may be too slow, etc.
needs: [ "Build allyesconfig, tools-only and envtools" ]
needs: [ "Run binman, buildman, dtoc, Kconfig and patman testsuites" ]
before_script:
# Clone uboot-test-hooks
- git config --global --add safe.directory "${CI_PROJECT_DIR}"
@@ -61,7 +59,6 @@ stages:
. /tmp/venv/bin/activate;
pip install -r test/py/requirements.txt -r tools/binman/requirements.txt
-r tools/buildman/requirements.txt -r tools/u_boot_pylib/requirements.txt
setuptools
after_script:
- cp -v /tmp/${TEST_PY_BD}/*.{html,css,xml} .
@@ -154,7 +151,6 @@ build all platforms in a single job:
. /tmp/venv/bin/activate;
pip install -r tools/binman/requirements.txt
-r tools/buildman/requirements.txt
setuptools
- ret=0;
git config --global --add safe.directory "${CI_PROJECT_DIR}";
./tools/buildman/buildman -o /tmp -PEWM -x xtensa || ret=$?;
@@ -195,18 +191,14 @@ Check for configs without MAINTAINERS entry:
- ./tools/buildman/buildman --maintainer-check
# Ensure host tools build
Build allyesconfig, tools-only and envtools:
Build tools-only and envtools:
extends: .testsuites
script:
# Allow pipefail because of how we use 'yes' here.
- set +o pipefail;
yes 0 | make allyesconfig oldconfig all -j$(nproc);
make mrproper;
make tools-only_config tools-only -j$(nproc);
- make tools-only_config tools-only -j$(nproc);
make mrproper;
make tools-only_config envtools -j$(nproc)
Run binman, buildman, dtoc and Kconfig testsuites:
Run binman, buildman, dtoc, Kconfig and patman testsuites:
extends: .testsuites
tags:
- ${DEFAULT_AMD64_TAG}
@@ -218,9 +210,8 @@ Run binman, buildman, dtoc and Kconfig testsuites:
python3 -m venv /tmp/venv;
. /tmp/venv/bin/activate;
pip install -r test/py/requirements.txt -r tools/binman/requirements.txt
-r tools/buildman/requirements.txt
-r tools/u_boot_pylib/requirements.txt
-r scripts/dtc/pylibfdt/requirements.txt;
-r tools/buildman/requirements.txt -r tools/patman/requirements.txt
-r tools/u_boot_pylib/requirements.txt;
export UBOOT_TRAVIS_BUILD_DIR=/tmp/tools-only;
export PYTHONPATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt";
export PATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}";
@@ -234,6 +225,7 @@ Run binman, buildman, dtoc and Kconfig testsuites:
./tools/binman/binman ${TOOLPATH} test -T;
./tools/buildman/buildman -t;
./tools/dtoc/dtoc -t;
./tools/patman/patman test;
make testconfig
# Check for any pylint regressions
@@ -244,9 +236,8 @@ Run pylint:
- python3 -m venv /tmp/venv
- . /tmp/venv/bin/activate
- pip install -r test/py/requirements.txt -r tools/binman/requirements.txt
-r tools/buildman/requirements.txt
-r tools/u_boot_pylib/requirements.txt
-r scripts/dtc/pylibfdt/requirements.txt asteval pylint==3.3.4 pyopenssl
-r tools/buildman/requirements.txt -r tools/patman/requirements.txt
-r tools/u_boot_pylib/requirements.txt asteval pylint==3.3.4 pyopenssl
- export PATH=${PATH}:~/.local/bin
- echo "[MASTER]" >> .pylintrc
- echo "load-plugins=pylint.extensions.docparams" >> .pylintrc
@@ -276,8 +267,6 @@ sandbox test.py:
variables:
TEST_PY_BD: "sandbox"
TEST_PY_EXTRA: "--timing"
# addr2line in Ubuntu 'Noble' and later are broken.
TEST_PY_TEST_SPEC: "not event_dump"
<<: *buildman_and_testpy_dfn
sandbox with clang test.py:
@@ -289,9 +278,7 @@ sandbox with clang test.py:
- ${HOST}
variables:
TEST_PY_BD: "sandbox"
OVERRIDE: "-O clang-20"
# addr2line in Ubuntu 'Noble' and later are broken.
TEST_PY_TEST_SPEC: "not event_dump"
OVERRIDE: "-O clang-18"
<<: *buildman_and_testpy_dfn
sandbox64 test.py:
@@ -314,7 +301,7 @@ sandbox64 with clang test.py:
- ${HOST}
variables:
TEST_PY_BD: "sandbox64"
OVERRIDE: "-O clang-20"
OVERRIDE: "-O clang-18"
<<: *buildman_and_testpy_dfn
sandbox64_lwip test.py:
@@ -392,7 +379,6 @@ qemu_arm64 test.py:
variables:
TEST_PY_BD: "qemu_arm64"
TEST_PY_TEST_SPEC: "not sleep"
OVERRIDE: "-a CONFIG_SEMIHOSTING=y"
<<: *buildman_and_testpy_dfn
qemu_arm64_lwip test.py:
@@ -422,12 +408,6 @@ qemu_m68k test.py:
OVERRIDE: "-a CONFIG_M68K_QEMU=y -a ~CONFIG_MCFTMR"
<<: *buildman_and_testpy_dfn
qemu_m68k_virt test.py:
variables:
TEST_PY_BD: "qemu-m68k"
TEST_PY_TEST_SPEC: "not sleep"
<<: *buildman_and_testpy_dfn
qemu_malta test.py:
variables:
TEST_PY_BD: "malta"
@@ -620,9 +600,6 @@ coreboot test.py:
TEST_PY_ID: "--id qemu"
<<: *buildman_and_testpy_dfn
# Add sage-lab stage
include: .gitlab-ci-sage-lab.yml
.sjg_lab_template: &sjg_lab_dfn
stage: sjg-lab
rules:
@@ -796,5 +773,5 @@ vf2:
qemu-x86_64:
variables:
ROLE: qemu-x86_64
TEST_PY_TEST_SPEC: "not sleep"
TEST_PY_TEST_SPEC: "and not sleep"
<<: *sjg_lab_dfn
.mailmap
+16 -26
View File
@@ -15,9 +15,7 @@
# Proper Name <proper@email.xx> <commit@email.xx>
# Proper Name <proper@email.xx> Commit Name <commit@email.xx>
<duje@dujemihanovic.xyz> <duje.mihanovic@skole.hr>
AKASHI Takahiro <akashi.tkhro@gmail.com> <takahiro.akashi@linaro.org>
Abbarapu Venkatesh Yadav <venkyada@qti.qualcomm.com> Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Alexander Graf <agraf@csgraf.de> <agraf@suse.de>
Allen Martin <amartin@nvidia.com>
Amanda Baze <amanda.baze@amd.com> <nicole.baze@xilinx.com>
@@ -43,21 +41,20 @@ Chen-Yu Tsai <wens@kernel.org> <wens@csie.org>
Christian Kohn <chris.kohn@amd.com> <christian.kohn@xilinx.com>
Christopher Obbard <christopher.obbard@linaro.org> <chris.obbard@collabora.com>
Dirk Behme <dirk.behme@googlemail.com>
<duje@dujemihanovic.xyz> <duje.mihanovic@skole.hr>
Durga Challa <durga.challa@amd.com> <vnsl.durga.challa@xilinx.com>
Eugen Hristev <ehristev@kernel.org> <eugen.hristev@collabora.com>
Eugen Hristev <ehristev@kernel.org> <eugen.hristev@linaro.org>
Eugen Hristev <ehristev@kernel.org> <eugen.hristev@microchip.com>
Eugen Hristev <eugen.hristev@linaro.org> <eugen.hristev@microchip.com>
Eugen Hristev <eugen.hristev@linaro.org> <eugen.hristev@collabora.com>
Fabio Estevam <fabio.estevam@nxp.com>
Greg Malysa <malysagreg@gmail.com> <greg.malysa@timesys.com>
Gregory CLEMENT <gregory.clement@bootlin.com> <gregory.clement@free-electrons.com>
Harini Katakam <harini.katakam@amd.com> <harini.katakam@xilinx.com>
Harsha <harsha.harsha@amd.com> <harsha.harsha@xilinx.com>
Heiko Schocher <hs@nabladev.com> <[hs@denx.de]>
Heiko Schocher <hs@nabladev.com> <heiko.schocher@invitel.hu>
Heiko Schocher <hs@nabladev.com> <hs@denx.de>
Heiko Schocher <hs@nabladev.com> <hs@pollux.(none)>
Heiko Schocher <hs@nabladev.com> <hs@pollux.denx.de>
Heiko Stuebner <heiko.stuebner@cherry.de> <heiko.stuebner@theobroma-systems.com>
Heiko Schocher <hs@nabladev.com> <hs@denx.de>
Heiko Schocher <hs@nabladev.com> <hs@pollux.denx.de>
Heiko Schocher <hs@nabladev.com> <heiko.schocher@invitel.hu>
Heiko Schocher <hs@nabladev.com> <[hs@denx.de]>
Heiko Schocher <hs@nabladev.com> <hs@pollux.(none)>
Heinrich Schuchardt <xypron.glpk@gmx.de> <heinrich.schuchardt@canonical.com>
Heinrich Schuchardt <xypron.glpk@gmx.de> xypron.glpk@gmx.de <xypron.glpk@gmx.de>
Ibai Erkiaga <ibai.erkiaga-elorza@amd.com> <ibai.erkiaga-elorza@xilinx.com>
@@ -70,16 +67,15 @@ Jagan Teki <jaganna@xilinx.com>
Jagan Teki <jagannadh.teki@gmail.com>
Jagan Teki <jagannadha.sutradharudu-teki@xilinx.com>
Jakob Unterwurzacher <jakob.unterwurzacher@cherry.de> <jakob.unterwurzacher@theobroma-systems.com>
Javier Tia <floss@jetm.me> <javier.tia@linaro.org>
Jay Buddhabhatti <jay.buddhabhatti@amd.com> <jay.buddhabhatti@xilinx.com>
Jernej Skrabec <jernej.skrabec@gmail.com> <jernej.skrabec@siol.net>
Jerome Forissier <jerome.forissier@arm.com> <jerome.forissier@linaro.org>
Jerome Forissier <jerome.forissier@arm.com> <jerome@forissier.org>
Jerome Forissier <jerome@forissier.org> <jerome.forissier@linaro.org>
John Linn <john.linn@amd.com> <john.linn@xilinx.com>
Jyotheeswar Reddy Mutthareddyvari <jyotheeswar.reddy.mutthareddyvari@amd.com> <jyothee@xilinx.com>
Jyotheeswar Reddy Mutthareddyvari <jyotheeswar.reddy.mutthareddyvari@amd.com> <jyotheeswar.reddy.mutthareddyvari@xilinx.com>
Kalyani Akula <kalyani.akula@amd.com> <kalyani.akula@xilinx.com>
Klaus Goger <klaus.goger@cherry.de> <klaus.goger@theobroma-systems.com>
Masahisa Kojima <kojima.masahisa@socionext.com> <masahisa.kojima@linaro.org>
Linus Walleij <linusw@kernel.org> <linus.walleij@linaro.org>
Love Kumar <love.kumar@amd.com> <love.kumar@xilinx.com>
Lukasz Majewski <lukma@denx.de>
@@ -89,15 +85,13 @@ Marek Vasut <marex@denx.de> <marek.vasut+renesas@gmail.com>
Marek Vasut <marex@denx.de> <marek.vasut@gmail.com>
Marek Vasut <marex@denx.de> <marex at denx.de>
Markus Klotzbuecher <mk@denx.de>
Masahiro Yamada <masahiroy@kernel.org> <yamada.m@jp.panasonic.com>
Masahiro Yamada <masahiroy@kernel.org> <yamada.masahiro@socionext.com>
Masahisa Kojima <kojima.masahisa@socionext.com> <masahisa.kojima@linaro.org>
Masahiro Yamada <masahiroy@kernel.org> <yamada.m@jp.panasonic.com>
Mattijs Korpershoek <mkorpershoek@kernel.org> <mkorpershoek@baylibre.com>
Michal Simek <michal.simek@amd.com> <Monstr@seznam.cz>
Michal Simek <michal.simek@amd.com> <michal.simek@xilinx.com>
Michal Simek <michal.simek@amd.com> <monstr@monstr.eu>
Michal Simek <michal.simek@amd.com> <root@monstr.eu>
Miquel Raynal <miquel.raynal@bootlin.com> <miquel.raynal@free-electrons.com>
Mirza <Taimoor_Mirza@mentor.com>
Mounika Grace Akula <mounika.akula@amd.com> <mounika.grace.akula@xilinx.com>
Mubin Usman Sayyed <mubin.sayyed@amd.com> <mubin.usman.sayyed@xilinx.com>
@@ -107,6 +101,8 @@ Nava kishore Manne <nava.kishore.manne@amd.com> <nava.manne@xilinx.com>
Neal Frager <neal.frager@amd.com> <neal.frager@xilinx.com>
Neil Armstrong <neil.armstrong@linaro.org> <narmstrong@baylibre.com>
Nicolas Saenz Julienne <nsaenz@kernel.org> <nsaenzjulienne@suse.de>
This contributor prefers not to receive mails <noreply@example.com> <pali@kernel.org>
This contributor prefers not to receive mails <noreply@example.com> <pali.rohar@gmail.com>
Padmarao Begari <padmarao.begari@amd.com> <padmarao.begari@microchip.com>
Patrice Chotard <patrice.chotard@foss.st.com> <patrice.chotard@st.com>
Patrick Delaunay <patrick.delaunay@foss.st.com> <patrick.delaunay@st.com>
@@ -134,11 +130,9 @@ Sam Protsenko <semen.protsenko@linaro.org> <joe.skb7@gmail.com>
Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com> <sandeep.gundlupet-raju@xilinx.com>
Sandeep Paulraj <s-paulraj@ti.com>
Sandeep Reddy Ghanapuram <sandeep.reddy-ghanapuram@amd.com> <sandeep.reddy-ghanapuram@xilinx.com>
Sean Anderson <sean.anderson@linux.dev> <sean.anderson@seco.com>
Shaohui Xie <Shaohui.Xie@freescale.com>
Shravya Kumbham <shravya.kumbham@amd.com> <shravya.kumbham@xilinx.com>
Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> <shubhrajyoti.datta@xilinx.com>
Simon Glass <sjg@chromium.org> <simon.glass@canonical.com>
Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> <siva.durga.paladugu@xilinx.com>
Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> <sivadur@xilinx.com>
Srinivas Goud <srinivas.goud@amd.com> <srinivas.goud@xilinx.com>
@@ -146,18 +140,14 @@ Srinivas Neeli <srinivas.neeli@amd.com> <srinivas.neeli@xilinx.com>
Stefan Roese <stefan.roese@mailbox.org> <stroese>
Stefano Babic <sbabic@nabladev.com>
Stefano Stabellini <stefano.stabellini@amd.com> <stefano.stabellini@xilinx.com>
Sughosh Ganu <sughosh.ganu@arm.com> <sughosh.ganu@linaro.org>
No generic patch CC mail please <noreply@example.com> <swarren@wwwdotorg.org>
No generic patch CC mail please <noreply@example.com> <swarren@nvidia.com>
Sumit Garg <sumit.garg@kernel.org> <sumit.garg@linaro.org>
This contributor prefers not to receive mails <noreply@example.com> <pali.rohar@gmail.com>
This contributor prefers not to receive mails <noreply@example.com> <pali@kernel.org>
This contributor prefers not to receive mails <noreply@example.com> <swarren@nvidia.com>
This contributor prefers not to receive mails <noreply@example.com> <swarren@wwwdotorg.org>
Thomas Petazzoni <thomas.petazzoni@bootlin.com> <thomas.petazzoni@free-electrons.com>
Tom Rini <trini@konsulko.com> <trini@ti.com>
Tomas Thoresen <tomas.thoresen@amd.com> <tomast@xilinx.com>
TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Varalaxmi Bingi <varalaxmi.bingi@amd.com> <varalaxmi.bingi@xilinx.com>
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> <venkatesh.abbarapu@xilinx.com>
Abbarapu Venkatesh Yadav <venkyada@qti.qualcomm.com>
Vikhyat Goyal <vikhyat.goyal@amd.com> <vikhyat.goyal@xilinx.com>
Vishal Patel <vishal.patel@amd.com> <vishal.patel@xilinx.com>
Wolfgang Denk <wd@denx.de> <wd@atlas.denx.de>
.patman-defaults
-32
View File
@@ -1,32 +0,0 @@
# Default patman settings for the U-Boot tree
#
# patman is maintained separately; install it with:
# pip install patch-manager
#
# See https://deinde.dev/patman
#
# patman reads this file at the lowest priority, so anything set here is a
# default that you can override in your own ~/.patman, in a local .patman or
# on the command line. patman autodetects the U-Boot project and locates
# scripts/get_maintainer.pl on its own; the patchwork server and get-maintainer
# script are pinned here so U-Boot does not depend on patman's built-in
# defaults in case those change.
[settings]
patchwork_url: https://patchwork.ozlabs.org
get_maintainer_script: scripts/get_maintainer.pl --norolestats
# Other settings you might set here as project defaults:
# process_tags: True
# add_signoff: True
# check_patch: True
# verbose: False
# smtp_server: /path/to/sendmail
# Aliases are recursive and are usually kept per-user in ~/.patman:
# [alias]
# me: Your Name <you@example.com>
# Addresses known to bounce can be dropped from the recipient list:
# [bounces]
# someone: A Name <someone@example.com>
Kbuild
+4 -6
View File
@@ -7,11 +7,10 @@
generic-offsets-file := include/generated/generic-asm-offsets.h
always-y := $(generic-offsets-file)
always := $(generic-offsets-file)
targets := lib/asm-offsets.s
CFLAGS_REMOVE_lib/asm-offsets.o := $(LTO_CFLAGS)
CFLAGS_REMOVE_arch/$(ARCH)/lib/asm-offsets.o := $(LTO_CFLAGS)
CFLAGS_REMOVE_asm-offsets.o := $(LTO_CFLAGS)
$(obj)/$(generic-offsets-file): $(obj)/lib/asm-offsets.s FORCE
$(call filechk,offsets,__GENERIC_ASM_OFFSETS_H__)
@@ -23,11 +22,10 @@ ifneq ($(wildcard $(srctree)/arch/$(ARCH)/lib/asm-offsets.c),)
offsets-file := include/generated/asm-offsets.h
endif
always-y += $(offsets-file)
always += $(offsets-file)
targets += arch/$(ARCH)/lib/asm-offsets.s
CFLAGS_lib/asm-offsets.o := -DDO_DEPS_ONLY
CFLAGS_arch/$(ARCH)/lib/asm-offsets.o := -DDO_DEPS_ONLY
CFLAGS_asm-offsets.o := -DDO_DEPS_ONLY
$(obj)/$(offsets-file): $(obj)/arch/$(ARCH)/lib/asm-offsets.s FORCE
$(call filechk,offsets,__ASM_OFFSETS_H__)
Kconfig
+52 -50
View File
@@ -140,15 +140,6 @@ config SPL_OPTIMIZE_INLINING
do what it thinks is best, which is desirable in some cases for size
reasons.
config TPL_OPTIMIZE_INLINING
bool "Allow compiler to uninline functions marked 'inline' in TPL"
depends on TPL
help
This option determines if U-Boot forces gcc to inline the functions
developers have marked 'inline'. Doing so takes away freedom from gcc to
do what it thinks is best, which is desirable in some cases for size
reasons.
config ARCH_SUPPORTS_LTO
bool
@@ -172,6 +163,15 @@ config LTO
If unsure, say n.
config TPL_OPTIMIZE_INLINING
bool "Allow compiler to uninline functions marked 'inline' in TPL"
depends on TPL
help
This option determines if U-Boot forces gcc to inline the functions
developers have marked 'inline'. Doing so takes away freedom from gcc to
do what it thinks is best, which is desirable in some cases for size
reasons.
config CC_COVERAGE
bool "Enable code coverage analysis"
depends on SANDBOX
@@ -299,8 +299,8 @@ config SYS_MALLOC_F_LEN
ROCKCHIP_RV1108
default 0x600 if ARCH_ZYNQMP_R5 || ARCH_ZYNQMP
default 0x800 if ARCH_ZYNQ || ROCKCHIP_RK3128 || ROCKCHIP_RK3188 || \
ROCKCHIP_RK322X
default 0x1000 if ARCH_MESON || ARCH_BMIPS || ARCH_MTMIPS || X86
ROCKCHIP_RK322X || X86
default 0x1000 if ARCH_MESON || ARCH_BMIPS || ARCH_MTMIPS
default 0x1800 if ARCH_TEGRA
default 0x4000 if SANDBOX || RISCV || ARCH_APPLE || ROCKCHIP_RK3368 || \
ROCKCHIP_RK3399
@@ -468,41 +468,12 @@ config TOOLS_DEBUG
it is possible to set breakpoints on particular lines, single-step
debug through the source code, etc.
config SKIP_EARLY_DM
bool "Skips initialising device model pre-relocation"
help
Enable this option to skip scanning and probing devices prior to
U-Boot relocation (during board_f). Unless console support is disabled
a serial port is still required, however this can be found through
/chosen/stdout-path in FDT. If the serial port relies on other devices
like clocks these will also be bound and probed on demand.
This can speed up time to interactive console by about 50%, particularly
when combined with OF_LIVE.
config SKIP_RELOCATE
bool "Skips relocation of U-Boot to end of RAM"
help
Skips relocation of U-Boot allowing for systems that have extremely
limited RAM to run U-Boot.
config SKIP_RELOCATE_CODE
bool
help
Skips relocation of U-Boot code to the end of RAM, but still does
relocate data to the end of RAM. This is mainly meant to relocate
data to read-write portion of the RAM, while the code remains in
read-only portion of the RAM from which it is allowed to execute.
This split configuration is present on various secure cores.
config SKIP_RELOCATE_CODE_DATA_OFFSET
hex
default 0x0
depends on SKIP_RELOCATE_CODE
help
Offset of the read-write memory which contains data, from read-only
memory which contains executable text.
endif # EXPERT
config PHYS_64BIT
@@ -548,14 +519,13 @@ config REMAKE_ELF
config BUILD_TARGET
string "Build target special images"
default "u-boot-elf.shdr" if RCAR_64 && RCAR_64_RSIP
default "u-boot-elf.srec" if RCAR_64 && !RCAR_64_RSIP
default "u-boot-elf.srec" if RCAR_64
default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
default "u-boot-with-spl.bin" if MPC85xx && !E500MC && !E5500 && !E6500 && SPL
default "u-boot-with-spl.imx" if (ARCH_MX6 || ARCH_MX7) && SPL
default "u-boot-with-spl.imx" if ARCH_MX6 && SPL
default "u-boot-with-spl.kwb" if ARMADA_32BIT && SPL
default "u-boot-with-spl.sfp" if ARCH_SOCFPGA_ARRIA10
default "u-boot-with-spl.sfp" if ARCH_SOCFPGA_GEN5
default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_ARRIA10
default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_GEN5
default "u-boot.itb" if !BINMAN && SPL_LOAD_FIT && (ARCH_ROCKCHIP || \
RISCV || ARCH_ZYNQMP)
default "u-boot.kwb" if (ARCH_KIRKWOOD || ARMADA_32BIT) && !SPL
@@ -645,11 +615,9 @@ config STACK_SIZE
default 0x4000 if ARCH_STM32
default 0x1000000
help
Define Max stack size that can be used by U-Boot. The UEFI sub-system
considers this value when setting up the memory map. The UEFI
specification requires 128 KiB or more of available stack space. On
some boards initrd_high is calculated as base stack pointer minus this
stack size.
Define Max stack size that can be used by U-Boot. This value is used
by the UEFI sub-system. On some boards initrd_high is calculated as
base stack pointer minus this stack size.
config SYS_MEM_TOP_HIDE
hex "Exclude some memory from U-Boot / OS information"
@@ -804,8 +772,42 @@ source "dts/Kconfig"
source "env/Kconfig"
menu "Networking"
choice
prompt "Networking stack"
default NET
config NO_NET
bool "No networking support"
help
Do not include networking support
config NET
bool "Legacy U-Boot networking stack"
imply NETDEVICES
help
Include networking support with U-Boot's internal implementation of
the TCP/IP protocol stack.
config NET_LWIP
bool "Use lwIP for networking stack"
imply NETDEVICES
help
Include networking support based on the lwIP (lightweight IP)
TCP/IP stack (https://nongnu.org/lwip). This is a replacement for
the default U-Boot network stack and applications located in net/
and enabled via CONFIG_NET as well as other pieces of code that
depend on CONFIG_NET (such as cmd/net.c enabled via CONFIG_CMD_NET).
Therefore the two symbols CONFIG_NET and CONFIG_NET_LWIP are mutually
exclusive.
endchoice
source "net/Kconfig"
endmenu
source "drivers/Kconfig"
source "fs/Kconfig"
MAINTAINERS
+50 -131
View File
@@ -65,11 +65,6 @@ F: include/alist.h
F: lib/alist.c
F: test/lib/alist.c
AMD VERSAL2 PCIE DRIVER
M: Pranav Sanwal <pranav.sanwal@amd.com>
S: Maintained
F: drivers/pci/pcie_dw_amd.c
ANDROID AB
M: Mattijs Korpershoek <mkorpershoek@kernel.org>
R: Igor Opaniuk <igor.opaniuk@gmail.com>
@@ -133,28 +128,20 @@ F: drivers/mmc/snps_dw_mmc.c
APPLE M1 SOC SUPPORT
M: Mark Kettenis <kettenis@openbsd.org>
R: Janne Grunau <j@jannau.net>
S: Maintained
F: arch/arm/include/asm/arch-apple/
F: arch/arm/mach-apple/
F: board/apple/
F: configs/apple_m1_defconfig
F: doc/board/apple/
F: drivers/input/apple_spi_kbd.c
F: drivers/iommu/apple_dart.c
F: drivers/mailbox/apple-mbox.c
F: drivers/nvme/nvme_apple.c
F: drivers/pci/pcie_apple.c
F: drivers/phy/phy-apple-atc.c
F: drivers/pinctrl/pinctrl-apple.c
F: drivers/power/domain/apple-pmgr.c
F: drivers/spi/apple_spi.c
F: drivers/watchdog/apple_wdt.c
F: include/configs/apple.h
ARM
M: Tom Rini <trini@konsulko.com>
M: Ilias Apalodimas <ilias.apalodimas@linaro.org>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-arm.git
F: arch/arm/
@@ -199,7 +186,6 @@ F: drivers/video/meson/
F: drivers/watchdog/meson_gxbb_wdt.c
F: include/configs/meson64.h
F: include/configs/meson64_android.h
F: tools/amlimage*
F: doc/board/amlogic/
N: meson
@@ -328,15 +314,14 @@ F: arch/arm/include/asm/arch-imx*/
F: arch/arm/include/asm/arch-mx*/
F: arch/arm/include/asm/arch-vf610/
F: arch/arm/include/asm/mach-imx/
F: board/nxp/*mx*/
F: board/nxp/common/
F: board/freescale/*mx*/
F: board/freescale/common/
F: common/spl/spl_imx_container.c
F: doc/board/nxp/
F: doc/imx/
F: drivers/mailbox/imx-mailbox.c
F: drivers/remoteproc/imx*
F: drivers/serial/serial_mxc.c
F: drivers/spi/nxp_xspi.c
F: include/imx_container.h
ARM HISILICON
@@ -374,7 +359,7 @@ F: drivers/rng/msm_rng.c
F: drivers/pinctrl/qcom/pinctrl-ipq4019.c
ARM LAYERSCAPE SFP
M: Sean Anderson <sean.anderson@linux.dev>
M: Sean Anderson <sean.anderson@seco.com>
S: Maintained
F: drivers/misc/ls2_sfp.c
@@ -428,12 +413,8 @@ M: Ryder Lee <ryder.lee@mediatek.com>
M: Weijie Gao <weijie.gao@mediatek.com>
M: Chunfeng Yun <chunfeng.yun@mediatek.com>
M: Igor Belwon <igor.belwon@mentallysanemainliners.org>
M: David Lechner <dlechner@baylibre.com>
M: Julien Stephan <jstephan@baylibre.com>
R: GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>
T: git https://source.denx.de/u-boot/custodians/u-boot-mediatek.git
S: Maintained
F: arch/arm/dts/mt*
F: arch/arm/mach-mediatek/
F: arch/arm/include/asm/arch-mediatek/
F: board/mediatek/
@@ -449,8 +430,6 @@ F: drivers/net/phy/mediatek/
F: drivers/phy/phy-mtk-*
F: drivers/pinctrl/mediatek/
F: drivers/power/domain/mtk-power-domain.c
F: drivers/power/pmic/mtk-pwrap.c
F: drivers/power/regulator/mt*.c
F: drivers/pci/pcie_mediatek_gen3.c
F: drivers/pci/pcie_mediatek.c
F: drivers/pwm/pwm-mtk.c
@@ -467,7 +446,6 @@ F: drivers/reset/reset-mediatek.c
F: drivers/serial/serial_mtk.c
F: include/dt-bindings/clock/mediatek,*
F: include/dt-bindings/power/mediatek,*
F: include/power/mt*.h
F: tools/mtk_image.c
F: tools/mtk_image.h
F: tools/mtk_nand_headers.c
@@ -483,7 +461,7 @@ F: configs/eDPU_defconfig
F: configs/uDPU_defconfig
ARM MICROCHIP/ATMEL AT91
M: Eugen Hristev <ehristev@kernel.org>
M: Eugen Hristev <eugen.hristev@microchip.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-at91.git
F: arch/arm/dts/at91*
@@ -646,17 +624,19 @@ S: Supported
F: arch/arm/dts/am335x-sancloud*
ARM SC5XX
M: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
M: Greg Malysa <malysagreg@gmail.com>
M: Ian Roberts <ian.roberts@timesys.com>
M: Vasileios Bimpikas <vasileios.bimpikas@analog.com>
M: Utsav Agarwal <utsav.agarwal@analog.com>
M: Arturs Artamonovs <arturs.artamonovs@analog.com>
L: linux@analog.com
L: adsp-linux@analog.com
S: Supported
T: git https://github.com/analogdevicesinc/u-boot
T: git https://github.com/analogdevicesinc/lnxdsp-u-boot
F: arch/arm/dts/sc5*
F: arch/arm/include/asm/arch-sc5xx/
F: arch/arm/include/asm/arch-adi/
F: arch/arm/mach-sc5xx/
F: board/adi/
F: configs/sc5*
F: doc/device-tree-bindings/arm/adi/adi,sc5xx.yaml
F: doc/device-tree-bindings/clock/adi,sc5xx-clocks.yaml
F: doc/device-tree-bindings/pinctrl/adi,adsp-pinctrl.yaml
@@ -676,7 +656,6 @@ F: drivers/timer/adi_sc5xx_timer.c
F: drivers/usb/musb-new/sc5xx.c
F: drivers/watchdog/adi_wdt.c
F: include/configs/sc5*
F: include/dt-bindings/clock/adi-sc5xx-clock.h
F: include/dt-bindings/pinctrl/adi-adsp.h
F: include/env/adi/
@@ -693,7 +672,6 @@ F: drivers/*/*/pm8???-*
F: drivers/gpio/msm_gpio.c
F: drivers/mmc/msm_sdhci.c
F: drivers/phy/msm8916-usbh-phy.c
F: drivers/phy/qcom/
F: drivers/serial/serial_msm.c
F: drivers/serial/serial_msm_geni.c
F: drivers/smem/msm_smem.c
@@ -769,6 +747,7 @@ N: stm
N: stm32
ARM SUNXI
M: Jagan Teki <jagan@amarulasolutions.com>
M: Andre Przywara <andre.przywara@arm.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-sunxi.git
@@ -1065,6 +1044,15 @@ T: git https://source.denx.de/u-boot/custodians/u-boot-clk.git
F: drivers/clk/
F: drivers/clk/imx/
COLDFIRE
M: Huan Wang <alison.wang@nxp.com>
M: Angelo Dureghello <angelo@kernel-space.org>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-coldfire.git
F: arch/m68k/
F: doc/arch/m68k.rst
F: drivers/watchdog/mcf_wdt.c
CPU
M: Simon Glass <sjg@chromium.org>
M: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
@@ -1117,7 +1105,7 @@ EFI CLIENT
M: Simon Glass <sjg@chromium.org>
M: Heinrich Schuchardt <xypron.glpk@gmx.de>
S: Maintained
W: https://docs.u-boot-project.org/en/latest/develop/uefi/u-boot_on_efi.html
W: https://docs.u-boot.org/en/latest/develop/uefi/u-boot_on_efi.html
F: board/efi/efi-x86_app
F: configs/efi-x86_app*
F: doc/develop/uefi/u-boot_on_efi.rst
@@ -1164,7 +1152,8 @@ F: tools/file2include.c
F: tools/mkeficapsule.c
ENVIRONMENT
S: Orphaned
M: Joe Hershberger <joe.hershberger@ni.com>
S: Maintained
F: env/
F: include/env/
F: include/env*
@@ -1257,17 +1246,12 @@ F: drivers/watchdog/sp805_wdt.c
F: drivers/watchdog/sbsa_gwdt.c
FWU Multi Bank Update
M: Sughosh Ganu <sughosh.ganu@arm.com>
M: Kory Maincent <kory.maincent@bootlin.com>
M: Sughosh Ganu <sughosh.ganu@linaro.org>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-efi.git
F: doc/fwumdata.1
F: doc/mkfwumdata.1
F: lib/fwu_updates/*
F: drivers/fwu-mdata/*
F: tools/fwumdata_src/fwumdata.c
F: tools/fwumdata_src/fwumdata.h
F: tools/fwumdata_src/mkfwumdata.c
F: tools/mkfwumdata.c
GATEWORKS_SC
M: Tim Harvey <tharvey@gateworks.com>
@@ -1275,29 +1259,6 @@ S: Maintained
F: drivers/misc/gsc.c
F: include/gsc.h
GOLDFISH SERIAL DRIVER
M: Kuan-Wei Chiu <visitorckw@gmail.com>
S: Maintained
F: drivers/serial/serial_goldfish.c
F: include/goldfish_tty.h
GOLDFISH TIMER DRIVER
M: Kuan-Wei Chiu <visitorckw@gmail.com>
S: Maintained
F: drivers/timer/goldfish_timer.c
F: include/goldfish_timer.h
INTERCONNECT:
M: Neil Armstrong <neil.armstrong@linaro.org>
S: Maintained
T: git https://source.denx.de/u-boot/u-boot.git
F: arch/sandbox/include/asm/interconnect.h
F: doc/api/interconnect.rst
F: drivers/interconnect/
F: include/interconnect-uclass.h
F: include/interconnect.h
F: test/dm/interconnect.c
I2C
M: Heiko Schocher <hs@nabladev.com>
S: Maintained
@@ -1321,6 +1282,12 @@ F: doc/README.kwbimage
F: doc/kwboot.1
F: tools/kwb*
LED
M: Ivan Vozvakhov <i.vozvakhov@vk.team>
S: Supported
F: doc/device-tree-bindings/leds/leds-pwm.txt
F: drivers/led/led_pwm.c
LOGGING
M: Simon Glass <sjg@chromium.org>
S: Maintained
@@ -1333,21 +1300,6 @@ F: lib/getopt.c
F: test/log/
F: test/py/tests/test_log.py
M680X0 ARCHITECTURE
M: Kuan-Wei Chiu <visitorckw@gmail.com>
S: Maintained
F: arch/m68k/cpu/m680x0/
F: arch/m68k/include/asm/bootinfo.h
M68K
M: Angelo Dureghello <angelo@kernel-space.org>
M: Kuan-Wei Chiu <visitorckw@gmail.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-coldfire.git
F: arch/m68k/
F: doc/arch/m68k.rst
F: drivers/watchdog/mcf_wdt.c
MALI DISPLAY PROCESSORS
M: Liviu Dudau <liviu.dudau@foss.arm.com>
S: Supported
@@ -1407,10 +1359,7 @@ F: drivers/net/phy/ca_phy.c
MIPS MEDIATEK
M: Weijie Gao <weijie.gao@mediatek.com>
M: David Lechner <dlechner@baylibre.com>
M: Julien Stephan <jstephan@baylibre.com>
R: GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>
T: git https://source.denx.de/u-boot/custodians/u-boot-mediatek.git
S: Maintained
F: arch/mips/mach-mtmips/
F: arch/mips/dts/mt7620.dtsi
@@ -1480,7 +1429,9 @@ F: drivers/mmc/
N: mmc
NETWORK
M: Jerome Forissier <jerome.forissier@arm.com>
M: Joe Hershberger <joe.hershberger@ni.com>
M: Ramon Fried <rfried.dev@gmail.com>
M: Jerome Forissier <jerome@forissier.org>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-net.git
F: drivers/net/
@@ -1488,7 +1439,7 @@ F: include/net.h
F: net/
NETWORK (LWIP)
M: Jerome Forissier <jerome.forissier@arm.com>
M: Jerome Forissier <jerome@forissier.org>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-net.git
F: cmd/lwip/
@@ -1507,7 +1458,6 @@ T: git https://source.denx.de/u-boot/custodians/u-boot-nios.git
F: arch/nios2/
NVMe
M: Neil Armstrong <neil.armstrong@linaro.org>
M: Bin Meng <bmeng.cn@gmail.com>
S: Maintained
F: drivers/nvme/
@@ -1566,7 +1516,8 @@ F: drivers/pci/pcie_dw_imx.c
F: drivers/phy/phy-imx8m-pcie.c
PCI Endpoint
S: Orphaned
M: Ramon Fried <rfried.dev@gmail.com>
S: Maintained
F: drivers/pci_endpoint/
F: include/pci_ep.h
@@ -1623,17 +1574,6 @@ S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-mpc85xx.git
F: arch/powerpc/cpu/mpc85xx/
PWM LED
S: Orphan
F: doc/device-tree-bindings/leds/leds-pwm.txt
F: drivers/led/led_pwm.c
QEMU VIRTUAL SYSTEM CONTROLLER
M: Kuan-Wei Chiu <visitorckw@gmail.com>
S: Maintained
F: drivers/sysreset/sysreset_qemu_virt_ctrl.c
F: include/qemu_virt_ctrl.h
RAW NAND
M: Dario Binacchi <dario.binacchi@amarulasolutions.com>
M: Michael Trimarchi <michael@amarulasolutions.com>
@@ -1674,7 +1614,7 @@ F: drivers/pinctrl/pinctrl-th1520.c
F: drivers/ram/thead/th1520_ddr.c
RNG
M: Sughosh Ganu <sughosh.ganu@arm.com>
M: Sughosh Ganu <sughosh.ganu@linaro.org>
R: Heinrich Schuchardt <xypron.glpk@gmx.de>
S: Maintained
F: cmd/rng.c
@@ -1715,7 +1655,7 @@ F: doc/usage/cmd/seama.rst
F: test/cmd/seama.c
SEMIHOSTING
R: Sean Anderson <sean.anderson@linux.dev>
R: Sean Anderson <sean.anderson@seco.com>
S: Orphaned
N: semihosting
@@ -1746,29 +1686,14 @@ F: include/slre.h
F: lib/slre.c
F: test/lib/slre.c
SM3
M: Heiko Schocher <hs@nabladev.com>
S: Maintained
F: cmd/sm3sum.c
F: include/u-boot/sm3.h
F: lib/sm3.c
SMBIOS
M: Raymond Mao <raymondmaoca@gmail.com>
S: Maintained
F: arch/arm/dts/smbios_generic.dtsi
F: cmd/smbios.c
F: drivers/sysinfo/smbios.c
F: include/smbios*
F: lib/smbios.c
SMCCC TRNG
M: Etienne Carriere <etienne.carriere@linaro.org>
S: Maintained
F: drivers/rng/smccc_trng.c
SPI
S: Orphaned
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-spi.git
F: drivers/spi/
F: include/spi*
@@ -1782,8 +1707,9 @@ T: git https://source.denx.de/u-boot/custodians/u-boot-nand-flash.git
F: drivers/mtd/nand/spi/
SPI-NOR
M: Jagan Teki <jagan@amarulasolutions.com>
M: Vignesh R <vigneshr@ti.com>
R: Takahiro Kuwano <takahiro.kuwano@infineon.com>
R: Tudor Ambarus <tudor.ambarus@linaro.org>
S: Maintained
F: drivers/mtd/spi/
F: include/spi_flash.h
@@ -1797,15 +1723,13 @@ F: drivers/spmi/
F: include/spmi/
SQUASHFS
M: Joao Marcos Costa <joaomarcos.costa@bootlin.com>
M: Richard Genoud <richard.genoud@bootlin.com>
M: Joao Marcos Costa <jmcosta944@gmail.com>
R: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
R: Miquel Raynal <miquel.raynal@bootlin.com>
S: Maintained
F: cmd/sqfs.c
F: common/spl/spl_squashfs.c
F: fs/squashfs/
F: include/sqfs.h
F: cmd/sqfs.c
F: test/py/tests/test_fs/test_squashfs/
STACKPROTECTOR
@@ -1873,14 +1797,10 @@ F: drivers/tpm/
F: include/tpm*
F: lib/tpm*
TQ-SYSTEMS
L: u-boot@ew.tq-group.com
S: Maintained
W: https://www.tq-group.com/en/products/tq-embedded/
F: board/tq/*
F: doc/board/tq/*
F: include/configs/tq*.h
F: include/env/tq/*
TQ GROUP
#M: Martin Krause <martin.krause@tq-systems.de>
S: Orphaned (Since 2016-02)
T: git git://git.denx.de/u-boot-tq-group.git
TEE
M: Jens Wiklander <jens.wiklander@linaro.org>
@@ -1922,7 +1842,6 @@ M: Neil Armstrong <neil.armstrong@linaro.org>
M: Bhupesh Sharma <bhupesh.linux@gmail.com>
M: Neha Malcom Francis <n-francis@ti.com>
S: Maintained
F: common/spl/spl_ufs.c
F: drivers/ufs/
UPL
@@ -1965,7 +1884,7 @@ F: drivers/usb/host/xhci*
F: include/usb/xhci.h
UTHREAD
M: Jerome Forissier <jerome.forissier@arm.com>
M: Jerome Forissier <jerome@forissier.org>
S: Maintained
F: cmd/spawn.c
F: include/uthread.h
Makefile
+190 -264
View File
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0+
VERSION = 2026
PATCHLEVEL = 07
PATCHLEVEL = 01
SUBLEVEL =
EXTRAVERSION =
NAME =
@@ -12,12 +12,32 @@ NAME =
# Comments in this file are targeted only to the developer, do not
# expect to learn how to build the kernel reading this file.
$(if $(filter __%, $(MAKECMDGOALS)), \
$(error targets prefixed with '__' are only for internal use))
# That's our default target when none is given on the command line
PHONY := __all
__all:
PHONY := _all
_all:
# Determine target architecture for the sandbox
include include/host_arch.h
ifeq ("", "$(CROSS_COMPILE)")
MK_ARCH="${shell uname -m}"
else
MK_ARCH="${shell echo $(CROSS_COMPILE) | sed -n 's/^\(.*ccache\)\{0,1\}[[:space:]]*\([^\/]*\/\)*\([^-]*\)-[^[:space:]]*/\3/p'}"
endif
unexport HOST_ARCH
ifeq ("x86_64", $(MK_ARCH))
export HOST_ARCH=$(HOST_ARCH_X86_64)
else ifneq (,$(findstring $(MK_ARCH), "i386" "i486" "i586" "i686"))
export HOST_ARCH=$(HOST_ARCH_X86)
else ifneq (,$(findstring $(MK_ARCH), "aarch64" "armv8l"))
export HOST_ARCH=$(HOST_ARCH_AARCH64)
else ifneq (,$(findstring $(MK_ARCH), "arm" "armv5tel" "armv6l" "armv7" "armv7a" "armv7l"))
export HOST_ARCH=$(HOST_ARCH_ARM)
else ifeq ("riscv32", $(MK_ARCH))
export HOST_ARCH=$(HOST_ARCH_RISCV32)
else ifeq ("riscv64", $(MK_ARCH))
export HOST_ARCH=$(HOST_ARCH_RISCV64)
endif
undefine MK_ARCH
# We are using a recursive build, so we need to do a little thinking
# to get the ordering right.
@@ -105,88 +125,79 @@ endif
export quiet Q KBUILD_VERBOSE
# Kbuild will save output files in the current working directory.
# This does not need to match to the root of the kernel source tree.
#
# For example, you can do this:
#
# cd /dir/to/store/output/files; make -f /dir/to/kernel/source/Makefile
#
# If you want to save output files in a different location, there are
# two syntaxes to specify it.
#
# kbuild supports saving output files in a separate directory.
# To locate output files in a separate directory two syntaxes are supported.
# In both cases the working directory must be the root of the kernel src.
# 1) O=
# Use "make O=dir/to/store/output/files/"
#
# 2) Set KBUILD_OUTPUT
# Set the environment variable KBUILD_OUTPUT to point to the output directory.
# export KBUILD_OUTPUT=dir/to/store/output/files/; make
# Set the environment variable KBUILD_OUTPUT to point to the directory
# where the output files shall be placed.
# export KBUILD_OUTPUT=dir/to/store/output/files/
# make
#
# The O= assignment takes precedence over the KBUILD_OUTPUT environment
# variable.
# Do we want to change the working directory?
# KBUILD_SRC is not intended to be used by the regular user (for now),
# it is set on invocation of make with KBUILD_OUTPUT or O= specified.
# OK, Make called in directory where kernel src resides
# Do we want to locate output files in a separate directory?
ifeq ("$(origin O)", "command line")
KBUILD_OUTPUT := $(O)
endif
ifneq ($(words $(subst :, ,$(CURDIR))), 1)
$(error main directory cannot contain spaces nor colons)
endif
ifneq ($(KBUILD_OUTPUT),)
# Make's built-in functions such as $(abspath ...), $(realpath ...) cannot
# expand a shell special character '~'. We use a somewhat tedious way here.
abs_objtree := $(shell mkdir -p $(KBUILD_OUTPUT) && cd $(KBUILD_OUTPUT) && pwd)
$(if $(abs_objtree),, \
$(error failed to create output directory "$(KBUILD_OUTPUT)"))
# check that the output directory actually exists
saved-output := $(KBUILD_OUTPUT)
KBUILD_OUTPUT := $(shell mkdir -p $(KBUILD_OUTPUT) && cd $(KBUILD_OUTPUT) \
&& pwd)
$(if $(KBUILD_OUTPUT),, \
$(error failed to create output directory "$(saved-output)"))
# $(realpath ...) resolves symlinks
abs_objtree := $(realpath $(abs_objtree))
else
abs_objtree := $(CURDIR)
endif # ifneq ($(KBUILD_OUTPUT),)
ifeq ($(abs_objtree),$(CURDIR))
# Suppress "Entering directory ..." unless we are changing the work directory.
MAKEFLAGS += --no-print-directory
else
need-sub-make := 1
endif
this-makefile := $(lastword $(MAKEFILE_LIST))
abs_srctree := $(realpath $(dir $(this-makefile)))
ifneq ($(words $(subst :, ,$(abs_srctree))), 1)
$(error source directory cannot contain spaces or colons)
endif
ifneq ($(abs_srctree),$(abs_objtree))
# Look for make include files relative to root of kernel src
#
# --included-dir is added for backward compatibility, but you should not rely on
# it. Please add $(srctree)/ prefix to include Makefiles in the source tree.
MAKEFLAGS += --include-dir=$(abs_srctree)
endif
# This does not become effective immediately because MAKEFLAGS is re-parsed
# once after the Makefile is read. It is OK since we are going to invoke
# 'sub-make' below.
MAKEFLAGS += --include-dir=$(CURDIR)
need-sub-make := 1
else
# Do not print "Entering directory ..." at all for in-tree build.
MAKEFLAGS += --no-print-directory
endif # ifneq ($(KBUILD_OUTPUT),)
ifneq ($(filter 3.%,$(MAKE_VERSION)),)
# 'MAKEFLAGS += -rR' does not immediately become effective for GNU Make 3.x
# We need to invoke sub-make to avoid implicit rules in the top Makefile.
need-sub-make := 1
# Cancel implicit rules for this Makefile.
$(this-makefile): ;
$(lastword $(MAKEFILE_LIST)): ;
endif
export abs_srctree abs_objtree
export sub_make_done := 1
ifeq ($(need-sub-make),1)
PHONY += $(MAKECMDGOALS) __sub-make
PHONY += $(MAKECMDGOALS) sub-make
$(filter-out $(this-makefile), $(MAKECMDGOALS)) __all: __sub-make
$(filter-out _all sub-make $(CURDIR)/Makefile, $(MAKECMDGOALS)) _all: sub-make
@:
# Invoke a second make in the output directory, passing relevant variables
__sub-make:
$(Q)$(MAKE) -C $(abs_objtree) -f $(abs_srctree)/Makefile $(MAKECMDGOALS)
sub-make:
$(Q)$(MAKE) \
$(if $(KBUILD_OUTPUT),-C $(KBUILD_OUTPUT) KBUILD_SRC=$(CURDIR)) \
-f $(CURDIR)/Makefile $(filter-out _all sub-make,$(MAKECMDGOALS))
endif # need-sub-make
endif # sub_make_done
@@ -199,53 +210,6 @@ ifeq ($(need-sub-make),)
# so that IDEs/editors are able to understand relative filenames.
MAKEFLAGS += --no-print-directory
ifeq ($(abs_srctree),$(abs_objtree))
# building in the source tree
srctree := .
building_out_of_srctree :=
else
ifeq ($(abs_srctree)/,$(dir $(abs_objtree)))
# building in a subdirectory of the source tree
srctree := ..
else
srctree := $(abs_srctree)
endif
building_out_of_srctree := 1
endif
ifneq ($(KBUILD_ABS_SRCTREE),)
srctree := $(abs_srctree)
endif
objtree := .
obj := $(objtree)
VPATH := $(srctree)
export building_out_of_srctree srctree objtree VPATH
# Determine target architecture for the sandbox
include $(srctree)/include/host_arch.h
ifeq ("", "$(CROSS_COMPILE)")
MK_ARCH="${shell uname -m}"
else
MK_ARCH="${shell echo $(CROSS_COMPILE) | sed -n 's/^\(.*ccache\)\{0,1\}[[:space:]]*\([^\/]*\/\)*\([^-]*\)-[^[:space:]]*/\3/p'}"
endif
unexport HOST_ARCH
ifeq ("x86_64", $(MK_ARCH))
export HOST_ARCH=$(HOST_ARCH_X86_64)
else ifneq (,$(findstring $(MK_ARCH), "i386" "i486" "i586" "i686"))
export HOST_ARCH=$(HOST_ARCH_X86)
else ifneq (,$(findstring $(MK_ARCH), "aarch64" "armv8l"))
export HOST_ARCH=$(HOST_ARCH_AARCH64)
else ifneq (,$(findstring $(MK_ARCH), "arm" "armv5tel" "armv6l" "armv7" "armv7a" "armv7l"))
export HOST_ARCH=$(HOST_ARCH_ARM)
else ifeq ("riscv32", $(MK_ARCH))
export HOST_ARCH=$(HOST_ARCH_RISCV32)
else ifeq ("riscv64", $(MK_ARCH))
export HOST_ARCH=$(HOST_ARCH_RISCV64)
endif
undefine MK_ARCH
# Call a source code checker (by default, "sparse") as part of the
# C compilation.
#
@@ -278,7 +242,27 @@ ifeq ("$(origin M)", "command line")
KBUILD_EXTMOD := $(M)
endif
export KBUILD_CHECKSRC KBUILD_EXTMOD
ifeq ($(KBUILD_SRC),)
# building in the source tree
srctree := .
else
ifeq ($(KBUILD_SRC)/,$(dir $(CURDIR)))
# building in a subdirectory of the source tree
srctree := ..
else
srctree := $(KBUILD_SRC)
endif
endif
export KBUILD_CHECKSRC KBUILD_EXTMOD KBUILD_SRC
objtree := .
src := $(srctree)
obj := $(objtree)
VPATH := $(srctree)
export srctree objtree VPATH
# To make sure we do not include .config for any of the *config targets
# catch them early, and hand them over to scripts/kconfig/Makefile
@@ -307,7 +291,6 @@ config-targets := 0
mixed-targets := 0
dot-config := 1
may-sync-config := 1
single-build := 0
ifneq ($(filter $(no-dot-config-targets), $(MAKECMDGOALS)),)
ifeq ($(filter-out $(no-dot-config-targets), $(MAKECMDGOALS)),)
@@ -366,9 +349,7 @@ __build_one_by_one:
else
include $(srctree)/scripts/Kbuild.uboot
include $(srctree)/scripts/Makefile.compiler
include scripts/Kbuild.include
# Read UBOOTRELEASE from include/config/uboot.release (if it exists)
UBOOTRELEASE = $(shell cat include/config/uboot.release 2> /dev/null)
@@ -376,7 +357,7 @@ UBOOTVERSION = $(VERSION)$(if $(PATCHLEVEL),.$(PATCHLEVEL)$(if $(SUBLEVEL),.$(SU
export VERSION PATCHLEVEL SUBLEVEL UBOOTRELEASE UBOOTVERSION
# Modified for U-Boot
-include $(srctree)/scripts/subarch.include
-include scripts/subarch.include
# Cross compiling and selecting different set of gcc/bin-utils
# ---------------------------------------------------------------------------
@@ -427,7 +408,9 @@ KCONFIG_CONFIG ?= .config
export KCONFIG_CONFIG
# SHELL used by kbuild
CONFIG_SHELL := sh
CONFIG_SHELL := $(shell if [ -x "$$BASH" ]; then echo $$BASH; \
else if [ -x /bin/bash ]; then echo /bin/bash; \
else echo sh; fi ; fi)
HOST_LFS_CFLAGS := $(shell getconf LFS_CFLAGS 2>/dev/null)
HOST_LFS_LDFLAGS := $(shell getconf LFS_LDFLAGS 2>/dev/null)
@@ -460,7 +443,7 @@ endef
export size_check
export KBUILD_MODULES KBUILD_BUILTIN
export KBUILD_CHECKSRC KBUILD_EXTMOD
export KBUILD_CHECKSRC KBUILD_SRC KBUILD_EXTMOD
# Make variables (CC, etc...)
AS = $(CROSS_COMPILE)as
@@ -477,20 +460,12 @@ READELF = $(CROSS_COMPILE)readelf
LEX = flex
YACC = bison
AWK = awk
BASH = bash
INSTALLKERNEL := installkernel
DEPMOD = /sbin/depmod
KBZIP2 = bzip2
KGZIP = gzip
KLZOP = lzop
LZMA = lzma
LZ4 = lz4c
PERL = perl
PYTHON = python
PYTHON2 = python2
PYTHON3 = python3
XZ = xz
ZSTD = zstd
# The devicetree compiler and pylibfdt are automatically built unless DTC is
# provided. If DTC is provided, it is assumed the pylibfdt is available too.
@@ -522,7 +497,7 @@ USERINCLUDE := \
# Needed to be compatible with the O= option
UBOOTINCLUDE := \
-Iinclude \
$(if $(building_out_of_srctree), -I$(srctree)/include) \
$(if $(KBUILD_SRC), -I$(srctree)/include) \
$(if $(CONFIG_$(XPL_)MBEDTLS_LIB), \
"-DMBEDTLS_CONFIG_FILE=\"mbedtls_def_config.h\"" \
-I$(srctree)/lib/mbedtls \
@@ -531,7 +506,7 @@ UBOOTINCLUDE := \
-I$(srctree)/lib/mbedtls/external/mbedtls/include) \
$(if $(CONFIG_$(PHASE_)SYS_THUMB_BUILD), \
$(if $(CONFIG_HAS_THUMB2), \
$(if $(CONFIG_CPU_V7M_V8M), \
$(if $(CONFIG_CPU_V7M), \
-I$(srctree)/arch/arm/thumb1/include), \
-I$(srctree)/arch/arm/thumb1/include)) \
-I$(srctree)/arch/$(ARCH)/include \
@@ -558,10 +533,9 @@ KBUILD_LDFLAGS_MODULE := -T $(srctree)/scripts/module-common.lds
KBUILD_LDFLAGS :=
GCC_PLUGINS_CFLAGS :=
export ARCH SRCARCH CONFIG_SHELL BASH HOSTCC KBUILD_HOSTCFLAGS CROSS_COMPILE AS LD CC
export ARCH SRCARCH CONFIG_SHELL HOSTCC KBUILD_HOSTCFLAGS CROSS_COMPILE AS LD CC
export CPP AR NM STRIP OBJCOPY OBJDUMP KBUILD_HOSTLDFLAGS KBUILD_HOSTLDLIBS
export MAKE LEX YACC AWK INSTALLKERNEL PERL PYTHON PYTHON2 PYTHON3 UTS_MACHINE
export KGZIP KBZIP2 KLZOP LZMA LZ4 XZ ZSTD
export HOSTCXX KBUILD_HOSTCXXFLAGS LDFLAGS_MODULE CHECK CHECKFLAGS
export KBUILD_CPPFLAGS NOSTDINC_FLAGS LINUXINCLUDE OBJCOPYFLAGS KBUILD_LDFLAGS
@@ -599,14 +573,6 @@ ifeq ($(NO_PYTHON),)
PYTHON_ENABLE=y
endif
# Files to ignore in find ... statements
export RCS_FIND_IGNORE := \( -name SCCS -o -name BitKeeper -o -name .svn -o \
-name CVS -o -name .pc -o -name .hg -o -name .git \) \
-prune -o
export RCS_TAR_IGNORE := --exclude SCCS --exclude BitKeeper --exclude .svn \
--exclude CVS --exclude .pc --exclude .hg --exclude .git
# ===========================================================================
# Rules shared between *config targets and build targets
@@ -614,34 +580,18 @@ export RCS_TAR_IGNORE := --exclude SCCS --exclude BitKeeper --exclude .svn \
PHONY += scripts_basic
scripts_basic:
$(Q)$(MAKE) $(build)=scripts/basic
$(Q)rm -f .tmp_quiet_recordmcount
PHONY += outputmakefile
ifdef building_out_of_srctree
# Before starting out-of-tree build, make sure the source tree is clean.
# outputmakefile generates a Makefile in the output directory, if using a
# separate output directory. This allows convenient use of make in the
# output directory.
# At the same time when output Makefile generated, generate .gitignore to
# ignore whole output directory
quiet_cmd_makefile = GEN Makefile
cmd_makefile = { \
echo "\# Automatically generated by $(srctree)/Makefile: don't edit"; \
echo "include $(srctree)/Makefile"; \
} > Makefile
outputmakefile:
$(Q)if [ -f $(srctree)/.config -o \
-d $(srctree)/include/config -o \
-d $(srctree)/arch/$(SRCARCH)/include/generated ]; then \
echo >&2 "***"; \
echo >&2 "*** The source tree is not clean, please run 'make$(if $(findstring command line, $(origin ARCH)), ARCH=$(ARCH)) mrproper'"; \
echo >&2 "*** in $(abs_srctree)";\
echo >&2 "***"; \
false; \
fi
ifneq ($(KBUILD_SRC),)
$(Q)ln -fsn $(srctree) source
$(call cmd,makefile)
$(Q)$(CONFIG_SHELL) $(srctree)/scripts/mkmakefile $(srctree)
$(Q)test -e .gitignore || \
{ echo "# this is build directory, ignore it"; echo "*"; } > .gitignore
endif
@@ -706,9 +656,9 @@ else
# but instead _all depend on modules
PHONY += all
ifeq ($(KBUILD_EXTMOD),)
__all: all
_all: all
else
__all: modules
_all: modules
endif
# Decide whether to build built-in, modular, or both.
@@ -828,8 +778,8 @@ ifneq ($(wildcard include/config/auto.conf),)
autoconf_is_old := $(shell find . -path ./$(KCONFIG_CONFIG) -newer \
include/config/auto.conf)
ifeq ($(autoconf_is_old),)
include $(srctree)/config.mk
include $(srctree)/arch/$(ARCH)/Makefile
include config.mk
include arch/$(ARCH)/Makefile
endif
endif
endif
@@ -919,11 +869,6 @@ endif
ifdef CONFIG_CC_OPTIMIZE_FOR_SIZE
KBUILD_CFLAGS += -Os
else ifdef CONFIG_CC_OPTIMIZE_FOR_DEBUG
KBUILD_CFLAGS += -Og
# Avoid false positives -Wmaybe-uninitialized
# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78394
KBUILD_CFLAGS += -Wno-maybe-uninitialized
else
KBUILD_CFLAGS += -O2
endif
@@ -935,8 +880,8 @@ endif
# Tell gcc to never replace conditional load with a non-conditional one
KBUILD_CFLAGS += $(call cc-option,--param=allow-store-data-races=0)
include $(srctree)/scripts/Makefile.kcov
include $(srctree)/scripts/Makefile.gcc-plugins
include scripts/Makefile.kcov
include scripts/Makefile.gcc-plugins
LTO_CFLAGS :=
LTO_FINAL_LDFLAGS :=
export LTO_CFLAGS LTO_FINAL_LDFLAGS
@@ -1024,7 +969,7 @@ KBUILD_CFLAGS += $(call cc-disable-warning, unused-but-set-variable)
# Prohibit date/time macros, which would make the build non-deterministic
KBUILD_CFLAGS += $(call cc-option,-Werror=date-time)
include $(srctree)/scripts/Makefile.extrawarn
include scripts/Makefile.extrawarn
# Add user supplied CPPFLAGS, AFLAGS and CFLAGS as the last assignments
KBUILD_CPPFLAGS += $(KCPPFLAGS)
@@ -1041,7 +986,7 @@ KBUILD_HOSTCFLAGS += $(if $(CONFIG_TOOLS_DEBUG),-g)
# Needed to be compatible with the O= option
UBOOTINCLUDE := \
-Iinclude \
$(if $(building_out_of_srctree), -I$(srctree)/include) \
$(if $(KBUILD_SRC), -I$(srctree)/include) \
$(if $(CONFIG_$(XPL_)MBEDTLS_LIB), \
"-DMBEDTLS_CONFIG_FILE=\"mbedtls_def_config.h\"" \
-I$(srctree)/lib/mbedtls \
@@ -1050,7 +995,7 @@ UBOOTINCLUDE := \
-I$(srctree)/lib/mbedtls/external/mbedtls/include) \
$(if $(CONFIG_$(PHASE_)SYS_THUMB_BUILD), \
$(if $(CONFIG_HAS_THUMB2), \
$(if $(CONFIG_CPU_V7M_V8M), \
$(if $(CONFIG_CPU_V7M), \
-I$(srctree)/arch/arm/thumb1/include), \
-I$(srctree)/arch/arm/thumb1/include)) \
-I$(srctree)/arch/$(ARCH)/include \
@@ -1081,7 +1026,7 @@ libs-$(CONFIG_OF_EMBED) += dts/
libs-y += env/
libs-y += lib/
libs-y += fs/
libs-$(CONFIG_NET) += net/
libs-$(filter y,$(CONFIG_NET) $(CONFIG_NET_LWIP)) += net/
libs-y += disk/
libs-y += drivers/
libs-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/
@@ -1231,7 +1176,6 @@ ifneq ($(CONFIG_SPL_TARGET),)
INPUTS-$(CONFIG_SPL) += $(CONFIG_SPL_TARGET:"%"=%)
endif
INPUTS-$(CONFIG_REMAKE_ELF) += u-boot.elf
INPUTS-$(CONFIG_SPL_REMAKE_ELF) += spl/u-boot-spl.elf
INPUTS-$(CONFIG_EFI_APP) += u-boot-app.efi
INPUTS-$(CONFIG_EFI_STUB) += u-boot-payload.efi
@@ -1243,8 +1187,12 @@ endif
endif
ifdef CONFIG_FUNCTION_TRACER
ifdef CONFIG_FTRACE_MCOUNT_USE_CC
CC_FLAGS_FTRACE += -mrecord-mcount
ifdef CONFIG_FTRACE_MCOUNT_RECORD
# gcc 5 supports generating the mcount tables directly
ifeq ($(call cc-option-yn,-mrecord-mcount),y)
CC_FLAGS_FTRACE += -mrecord-mcount
export CC_USING_RECORD_MCOUNT := 1
endif
ifdef CONFIG_HAVE_NOP_MCOUNT
ifeq ($(call cc-option-yn, -mnop-mcount),y)
CC_FLAGS_FTRACE += -mnop-mcount
@@ -1252,17 +1200,7 @@ ifdef CONFIG_FTRACE_MCOUNT_USE_CC
endif
endif
endif
ifdef CONFIG_FTRACE_MCOUNT_USE_OBJTOOL
CC_FLAGS_USING += -DCC_USING_NOP_MCOUNT
endif
ifdef CONFIG_FTRACE_MCOUNT_USE_RECORDMCOUNT
ifdef CONFIG_HAVE_C_RECORDMCOUNT
BUILD_C_RECORDMCOUNT := y
export BUILD_C_RECORDMCOUNT
endif
endif
ifdef CONFIG_HAVE_FENTRY
# s390-linux-gnu-gcc did not support -mfentry until gcc-9.
ifeq ($(call cc-option-yn, -mfentry),y)
CC_FLAGS_FTRACE += -mfentry
CC_FLAGS_USING += -DCC_USING_FENTRY
@@ -1271,6 +1209,12 @@ endif
export CC_FLAGS_FTRACE
KBUILD_CFLAGS += $(CC_FLAGS_FTRACE) $(CC_FLAGS_USING)
KBUILD_AFLAGS += $(CC_FLAGS_USING)
ifdef CONFIG_DYNAMIC_FTRACE
ifdef CONFIG_HAVE_C_RECORDMCOUNT
BUILD_C_RECORDMCOUNT := y
export BUILD_C_RECORDMCOUNT
endif
endif
endif
# Add optional build target if defined in board/cpu/soc headers
@@ -1373,7 +1317,7 @@ expect = $(foreach cfg,$(1),y)
# 1: List of options to migrate to (e.g. "CONFIG_DM_MMC CONFIG_BLK")
# 2: Name of component (e.g . "Ethernet drivers")
# 3: Release deadline (e.g. "v202.07")
# 4: Condition to require before checking (e.g. "$(CONFIG_NET_LEGACY)")
# 4: Condition to require before checking (e.g. "$(CONFIG_NET)")
# Note: Script avoids bash construct, hence the strange double 'if'
# (patches welcome!)
define deprecated
@@ -1423,6 +1367,7 @@ endif
PHONY += dtbs dtbs_check
dtbs: dts/dt.dtb
@:
dts/dt.dtb: dtbs_prepare u-boot
$(Q)$(MAKE) $(build)=dts dtbs
@@ -1446,15 +1391,11 @@ quiet_cmd_copy = COPY $@
cmd_copy = cp $< $@
ifeq ($(CONFIG_OF_UPSTREAM),y)
ifeq ($(CONFIG_CPU_V8M),y)
dt_dir := dts/upstream/src/arm64
else
ifeq ($(CONFIG_ARM64),y)
dt_dir := dts/upstream/src/arm64
else
dt_dir := dts/upstream/src/$(ARCH)
endif
endif
else
dt_dir := arch/$(ARCH)/dts
endif
@@ -1489,10 +1430,10 @@ MKIMAGEFLAGS_fit-dtb.blob = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
MKIMAGEFLAGS_fit-dtb.blob += -B 0x8
ifneq ($(EXT_DTB),)
u-boot-fit-dtb.bin: u-boot-nodtb.bin $(EXT_DTB) FORCE
u-boot-fit-dtb.bin: u-boot-nodtb.bin $(EXT_DTB)
$(call if_changed,cat)
else
u-boot-fit-dtb.bin: u-boot-nodtb.bin $(FINAL_DTB_CONTAINER) FORCE
u-boot-fit-dtb.bin: u-boot-nodtb.bin $(FINAL_DTB_CONTAINER)
$(call if_changed,cat)
endif
@@ -1578,9 +1519,6 @@ spl/u-boot-spl.srec: spl/u-boot-spl FORCE
%.scif: %.srec
$(Q)$(MAKE) $(build)=arch/arm/mach-renesas $@
%.shdr: %.srec
$(Q)$(MAKE) $(build)=arch/arm/mach-renesas $@
OBJCOPYFLAGS_u-boot-nodtb.bin := -O binary \
$(if $(CONFIG_X86_16BIT_INIT),-R .start16 -R .resetvec) \
$(if $(CONFIG_MPC85XX_HAVE_RESET_VECTOR),$(if $(CONFIG_OF_SEPARATE),-R .bootpg -R .resetvec))
@@ -1590,7 +1528,7 @@ binary_size_check: u-boot-nodtb.bin FORCE
map_size=$(shell cat u-boot.map | \
awk ' \
/_image_copy_start/ { start = $$1 } \
/_image_binary_end/ { end = $$1;exit } \
/_image_binary_end/ { end = $$1 } \
END { \
if (start != "" && end != "") \
print end " " start; \
@@ -1685,7 +1623,7 @@ cmd_binman = $(srctree)/tools/binman/binman $(if $(BINMAN_DEBUG),-D) \
build -u -d $(binman_dtb) -O . -m \
--allow-missing --fake-ext-blobs \
$(if $(BINMAN_ALLOW_MISSING),--ignore-missing) \
-I . -I $(srctree)/board/$(BOARDDIR) -I $(srctree) \
-I . -I $(srctree) -I $(srctree)/board/$(BOARDDIR) \
$(foreach f,$(of_list_dirs),-I $(f)) -a of-list=$(of_list) \
$(foreach f,$(BINMAN_INDIRS),-I $(f)) \
-a atf-bl1-path=${BL1} \
@@ -1840,18 +1778,14 @@ tpl/u-boot-with-tpl.bin: tpl/u-boot-tpl.bin u-boot.bin FORCE
SPL: spl/u-boot-spl.bin FORCE
$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
ifeq ($(CONFIG_SPL_LOAD_IMX_CONTAINER),y)
ifeq ($(CONFIG_ARCH_IMX8M)$(CONFIG_ARCH_IMX8),y)
#ifeq ($(CONFIG_ARCH_IMX8M)$(CONFIG_ARCH_IMX8), y)
ifeq ($(CONFIG_SPL_LOAD_IMX_CONTAINER), y)
u-boot.cnt: u-boot.bin FORCE
$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
flash.bin: spl/u-boot-spl.bin u-boot.cnt FORCE
$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
else
flash.bin: spl/u-boot-spl.bin FORCE
$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
endif
else
ifeq ($(CONFIG_BINMAN),y)
flash.bin: spl/u-boot-spl.bin $(INPUTS-y) FORCE
$(call if_changed,binman)
@@ -1860,6 +1794,7 @@ flash.bin: spl/u-boot-spl.bin u-boot.itb FORCE
$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
endif
endif
#endif
u-boot.uim: u-boot.bin FORCE
$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
@@ -2004,19 +1939,10 @@ quiet_cmd_u-boot-elf ?= LD $@
$(if $(CONFIG_SYS_BIG_ENDIAN),-EB,-EL) \
-T u-boot-elf.lds --defsym=$(CONFIG_PLATFORM_ELFENTRY)=$(CONFIG_TEXT_BASE) \
-Ttext=$(CONFIG_TEXT_BASE)
u-boot.elf: u-boot.bin u-boot-elf.lds FORCE
u-boot.elf: u-boot.bin u-boot-elf.lds
$(Q)$(OBJCOPY) -I binary $(PLATFORM_ELFFLAGS) $< u-boot-elf.o
$(call if_changed,u-boot-elf)
quiet_cmd_u-boot-spl-elf ?= LD $@
cmd_u-boot-spl-elf ?= $(LD) spl/u-boot-spl-elf.o -o $@ \
$(if $(CONFIG_SYS_BIG_ENDIAN),-EB,-EL) \
-T u-boot-elf.lds --defsym=$(CONFIG_PLATFORM_ELFENTRY)=$(CONFIG_SPL_TEXT_BASE) \
-Ttext=$(CONFIG_SPL_TEXT_BASE)
spl/u-boot-spl.elf: spl/u-boot-spl.bin u-boot-elf.lds
$(Q)$(OBJCOPY) -I binary $(PLATFORM_ELFFLAGS) $< spl/u-boot-spl-elf.o
$(call if_changed,u-boot-spl-elf)
u-boot-elf.lds: arch/u-boot-elf.lds prepare FORCE
$(call if_changed_dep,cpp_lds)
@@ -2030,7 +1956,7 @@ PHONY += prepare0
ifeq ($(CONFIG_SPL),y)
spl/u-boot-spl-mtk.bin: spl/u-boot-spl
u-boot-mtk.bin: u-boot-with-spl.bin FORCE
u-boot-mtk.bin: u-boot-with-spl.bin
$(call if_changed,copy)
else
MKIMAGEFLAGS_u-boot-mtk.bin = -T mtk_image \
@@ -2063,9 +1989,9 @@ quiet_cmd_keep_syms_lto_cc = KSLCC $@
cmd_keep_syms_lto_cc = \
$(CC) $(filter-out $(LTO_CFLAGS),$(c_flags)) -c -o $@ $<
$(u-boot-keep-syms-lto_c): $(u-boot-main) FORCE
$(u-boot-keep-syms-lto_c): $(u-boot-main)
$(call if_changed,keep_syms_lto)
$(u-boot-keep-syms-lto): $(u-boot-keep-syms-lto_c) FORCE
$(u-boot-keep-syms-lto): $(u-boot-keep-syms-lto_c)
$(call if_changed,keep_syms_lto_cc)
else
u-boot-keep-syms-lto :=
@@ -2150,12 +2076,10 @@ ENV_FILE := $(if $(ENV_SOURCE_FILE),$(ENV_FILE_CFG),$(wildcard $(ENV_FILE_BOARD)
quiet_cmd_gen_envp = ENVP $@
cmd_gen_envp = \
if [ -s "$(ENV_FILE)" ]; then \
$(CPP) -P $(KBUILD_CPPFLAGS) $(UBOOTINCLUDE) \
-x assembler-with-cpp -undef \
$(CPP) -P $(cpp_flags) -x assembler-with-cpp -undef \
-D__ASSEMBLY__ \
-D__UBOOT_CONFIG__ \
-DDEFAULT_DEVICE_TREE=$(subst ",,$(CONFIG_DEFAULT_DEVICE_TREE)) \
-DDEFAULT_FDT_FILE=$(subst ",,$(CONFIG_DEFAULT_FDT_FILE)) \
-I . -I include -I $(srctree)/include \
-include linux/kconfig.h -include include/config.h \
-I$(srctree)/arch/$(ARCH)/include \
@@ -2249,7 +2173,7 @@ PHONY += prepare archprepare prepare1 prepare3
# and if so do:
# 1) Check that make has not been executed in the kernel src $(srctree)
prepare3: include/config/uboot.release
ifdef building_out_of_srctree
ifneq ($(KBUILD_SRC),)
@$(kecho) ' Using $(srctree) as source for U-Boot'
$(Q)if [ -f $(srctree)/.config -o -d $(srctree)/include/config ]; then \
echo >&2 " $(srctree) is not clean, please run 'make mrproper'"; \
@@ -2343,10 +2267,10 @@ define filechk_timestamp.h
endef
define filechk_defaultenv.h
( ( { grep -v '^#' | grep -v '^$$' || true ; echo '' ; } | \
( { grep -v '^#' | grep -v '^$$' || true ; echo '' ; } | \
tr '\n' '\0' | \
sed -e 's/\\\x0\s*//g' | \
xxd -i ; ) < $<; )
xxd -i ; )
endef
define filechk_dt.h
@@ -2389,7 +2313,7 @@ dtbs_check: export CHECK_DTBS=1
dtbs_check: dt_binding_check
dtbs_install:
$(Q)$(MAKE) -f $(srctree)/scripts/Makefile.dtbinst obj=$(dtstree)
$(Q)$(MAKE) $(dtbinst)=$(dtstree)
ifdef CONFIG_OF_EARLY_FLATTREE
all: dtbs
@@ -2507,7 +2431,7 @@ checkarmreloc: u-boot
false; \
fi
tools/version.h: include/version.h FORCE
tools/version.h: include/version.h
$(Q)mkdir -p $(dir $@)
$(call if_changed,copy)
@@ -2539,12 +2463,12 @@ CHANGELOG:
# make distclean Remove editor backup files, patch leftover files and the like
# Directories & files removed with 'make clean'
CLEAN_FILES += $(MODVERDIR) \
CLEAN_DIRS += $(MODVERDIR) \
$(foreach d, spl tpl vpl, $(patsubst %,$d/%, \
$(filter-out include, $(shell ls -1 $d 2>/dev/null))))
CLEAN_FILES += include/autoconf.mk* include/bmp_logo.h include/bmp_logo_data.h \
include/config.h include/generated/env.* drivers/video/u_boot_logo.bmp.S \
include/config.h include/generated/env.* drivers/video/u_boot_logo.S \
tools/version.h u-boot* MLO* SPL System.map fit-dtb.blob* \
u-boot-ivt.img.log u-boot-dtb.imx.log SPL.log u-boot.imx.log \
lpc32xx-* bl31.c bl31.elf bl31_*.bin image.map tispl.bin* \
@@ -2558,7 +2482,7 @@ CLEAN_FILES += include/autoconf.mk* include/bmp_logo.h include/bmp_logo_data.h \
imx9image* m33-oei-ddrfw* tifalcon.bin
# Directories & files removed with 'make mrproper'
MRPROPER_FILES += include/config include/generated spl tpl vpl \
MRPROPER_DIRS += include/config include/generated spl tpl vpl \
.tmp_objdiff doc/output include/asm
# Remove include/asm symlink created by U-Boot before v2014.01
@@ -2568,14 +2492,37 @@ MRPROPER_FILES += .config .config.old include/autoconf.mk* include/config.h \
# clean - Delete most, but leave enough to build external modules
#
clean: rm-dirs := $(CLEAN_DIRS)
clean: rm-files := $(CLEAN_FILES)
clean-dirs := $(foreach f,$(u-boot-alldirs),$(if $(wildcard $(srctree)/$f/Makefile),$f))
clean-dirs := $(addprefix _clean_, $(clean-dirs))
PHONY += archclean
PHONY += $(clean-dirs) clean archclean
$(clean-dirs):
$(Q)$(MAKE) $(clean)=$(patsubst _clean_%,%,$@)
clean: archclean
clean: $(clean-dirs)
$(call cmd,rmdirs)
$(call cmd,rmfiles)
@find $(if $(KBUILD_EXTMOD), $(KBUILD_EXTMOD), .) $(RCS_FIND_IGNORE) \
\( -name '*.[oas]' -o -name '*.ko' -o -name '.*.cmd' \
-o -name '*.ko.*' -o -name '*.su' -o -name '*.pyc' \
-o -name '*.dtb' -o -name '*.dtbo' \
-o -name '*.dtb.S' -o -name '*.dtbo.S' \
-o -name '.*.d' -o -name '.*.tmp' -o -name '*.mod.c' \
-o -name '*.lex.c' -o -name '*.tab.[ch]' \
-o -name '*.asn1.[ch]' \
-o -name '*.symtypes' -o -name 'modules.order' \
-o -name modules.builtin -o -name '.tmp_*.o.*' \
-o -name 'dsdt_generated.aml' -o -name 'dsdt_generated.asl.tmp' \
-o -name 'dsdt_generated.c' \
-o -name 'generated_defconfig' \
-o -name '*.efi' -o -name '*.gcno' -o -name '*.so' \) \
-type f -print | xargs rm -f
# mrproper - Delete all generated files, including .config
#
mrproper: rm-dirs := $(wildcard $(MRPROPER_DIRS))
mrproper: rm-files := $(wildcard $(MRPROPER_FILES))
mrproper-dirs := $(addprefix _mrproper_,scripts)
@@ -2584,50 +2531,22 @@ $(mrproper-dirs):
$(Q)$(MAKE) $(clean)=$(patsubst _mrproper_%,%,$@)
mrproper: clean $(mrproper-dirs)
$(call cmd,rmdirs)
$(call cmd,rmfiles)
@rm -f arch/*/include/asm/arch
# distclean
#
PHONY += distclean
distclean: mrproper
@find . $(RCS_FIND_IGNORE) \
@find $(srctree) $(RCS_FIND_IGNORE) \
\( -name '*.orig' -o -name '*.rej' -o -name '*~' \
-o -name '*.bak' -o -name '#*#' -o -name '*%' \
-o -name 'core' -o -name tags -o -name TAGS -o -name 'cscope*' \
-o -name GPATH -o -name GRTAGS -o -name GSYMS -o -name GTAGS \) \
-o -name '*.bak' -o -name '#*#' -o -name '.*.orig' \
-o -name '.*.rej' -o -name '*%' -o -name 'core' \
-o -name '*.pyc' \) \
-type f -print | xargs rm -f
# Modified for U-Boot, the kernel figures this out through it's own variable
clean-dirs := $(foreach f,$(u-boot-alldirs),$(if $(wildcard $(srctree)/$f/Makefile),$f))
clean-dirs := $(addprefix _clean_, $(clean-dirs))
PHONY += $(clean-dirs) clean
$(clean-dirs):
$(Q)$(MAKE) $(clean)=$(patsubst _clean_%,%,$@)
clean: $(clean-dirs)
$(call cmd,rmfiles)
@find $(or $(KBUILD_EXTMOD), .) $(RCS_FIND_IGNORE) \
\( -name '*.[aios]' -o -name '*.ko' -o -name '.*.cmd' \
-o -name '*.ko.*' -o -name '*.su' -o -name '*.pyc' \
-o -name '*.dtb' -o -name '*.dtbo' -o -name '*.dtb.S' -o -name '*.dt.yaml' \
-o -name '*.dtb.clean.dts' -o -name '*.dtb.full.dts' -o -name '*.dtb.diff' \
-o -name '*.dwo' -o -name '*.lst' \
-o -name '*.su' -o -name '*.mod' -o -name '*.usyms' \
-o -name '.*.d' -o -name '.*.tmp' -o -name '*.mod.c' \
-o -name '*.lex.c' -o -name '*.tab.[ch]' \
-o -name '*.asn1.[ch]' \
-o -name '*.symtypes' -o -name 'modules.order' \
-o -name '.tmp_*' \
-o -name '*.c.[012]*.*' \
-o -name '*.ll' \
-o -name 'dsdt_generated.aml' -o -name 'dsdt_generated.asl.tmp' \
-o -name 'dsdt_generated.c' \
-o -name 'generated_defconfig' \
-o -name '*.gcno' \
-o -name '*.efi' -o -name '*.gcno' -o -name '*.so' \
-o -name '*.*.symversions' \) -type f -print | xargs rm -f
@rm -f boards.cfg CHANGELOG .binman_stamp
# See doc/develop/python_cq.rst
PHONY += pylint pylint_err
@@ -2691,6 +2610,7 @@ pip pip_test pip_release: _pip
_pip:
scripts/make_pip.sh u_boot_pylib ${PIP_ARGS}
scripts/make_pip.sh patman ${PIP_ARGS}
scripts/make_pip.sh buildman ${PIP_ARGS}
scripts/make_pip.sh dtoc ${PIP_ARGS}
scripts/make_pip.sh binman ${PIP_ARGS}
@@ -2755,19 +2675,21 @@ help:
@echo 'Execute "make" or "make all" to build all targets marked with [*] '
@echo 'For further info see the ./README file'
run_tests = $(Q)env -u sub_make_done $(srctree)/test/run
ifneq ($(filter tests pcheck qcheck tcheck,$(MAKECMDGOALS)),)
export sub_make_done := 0
endif
tests check:
$(run_tests)
$(srctree)/test/run
pcheck:
$(run_tests) parallel
$(srctree)/test/run parallel
qcheck:
$(run_tests) quick
$(srctree)/test/run quick
tcheck:
$(run_tests) tools
$(srctree)/test/run tools
# Documentation targets
# ---------------------------------------------------------------------------
@@ -2775,7 +2697,8 @@ DOC_TARGETS := xmldocs latexdocs pdfdocs htmldocs epubdocs cleandocs \
linkcheckdocs dochelp refcheckdocs texinfodocs infodocs
PHONY += $(DOC_TARGETS)
$(DOC_TARGETS): scripts_basic FORCE
$(Q)$(MAKE) $(build)=doc $@
$(Q)PYTHONPATH=$(srctree)/test/py/tests:$(srctree)/test/py \
$(MAKE) $(build)=doc $@
PHONY += checkstack ubootrelease ubootversion
@@ -2856,13 +2779,16 @@ u-boot-initial-env: scripts_basic $(version_h) $(env_h) include/config.h FORCE
PHONY += coccicheck
coccicheck:
$(Q)$(BASH) $(srctree)/scripts/$@
$(Q)$(CONFIG_SHELL) $(srctree)/scripts/$@
# FIXME Should go into a make.lib or something
# ===========================================================================
quiet_cmd_rmdirs = $(if $(wildcard $(rm-dirs)),CLEAN $(wildcard $(rm-dirs)))
cmd_rmdirs = rm -rf $(rm-dirs)
quiet_cmd_rmfiles = $(if $(wildcard $(rm-files)),CLEAN $(wildcard $(rm-files)))
cmd_rmfiles = rm -rf $(rm-files)
cmd_rmfiles = rm -f $(rm-files)
# Run depmod only if we have System.map and depmod is executable
quiet_cmd_depmod = DEPMOD $(KERNELRELEASE)
README
+120 -2
View File
@@ -597,6 +597,32 @@ The following options need to be configured:
A byte containing the id of the VLAN.
- Status LED: CONFIG_LED_STATUS
Several configurations allow to display the current
status using a LED. For instance, the LED will blink
fast while running U-Boot code, stop blinking as
soon as a reply to a BOOTP request was received, and
start blinking slow once the Linux kernel is running
(supported by a status LED driver in the Linux
kernel). Defining CONFIG_LED_STATUS enables this
feature in U-Boot.
Additional options:
CONFIG_LED_STATUS_GPIO
The status LED can be connected to a GPIO pin.
In such cases, the gpio_led driver can be used as a
status LED backend implementation. Define CONFIG_LED_STATUS_GPIO
to include the gpio_led driver in the U-Boot binary.
CFG_GPIO_LED_INVERTED_TABLE
Some GPIO connected LEDs may have inverted polarity in which
case the GPIO high value corresponds to LED off state and
GPIO low value corresponds to LED on state.
In such cases CFG_GPIO_LED_INVERTED_TABLE may be defined
with a list of GPIO LEDs that have inverted polarity.
- I2C Support:
CFG_SYS_NUM_I2C_BUSES
Hold the number of i2c buses you want to use.
@@ -628,6 +654,98 @@ The following options need to be configured:
If you do not have i2c muxes on your board, omit this define.
- Legacy I2C Support:
If you use the software i2c interface (CONFIG_SYS_I2C_SOFT)
then the following macros need to be defined (examples are
from include/configs/lwmon.h):
I2C_INIT
(Optional). Any commands necessary to enable the I2C
controller or configure ports.
eg: #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
I2C_ACTIVE
The code necessary to make the I2C data line active
(driven). If the data line is open collector, this
define can be null.
eg: #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
I2C_TRISTATE
The code necessary to make the I2C data line tri-stated
(inactive). If the data line is open collector, this
define can be null.
eg: #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
I2C_READ
Code that returns true if the I2C data line is high,
false if it is low.
eg: #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
I2C_SDA(bit)
If <bit> is true, sets the I2C data line high. If it
is false, it clears it (low).
eg: #define I2C_SDA(bit) \
if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
else immr->im_cpm.cp_pbdat &= ~PB_SDA
I2C_SCL(bit)
If <bit> is true, sets the I2C clock line high. If it
is false, it clears it (low).
eg: #define I2C_SCL(bit) \
if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
else immr->im_cpm.cp_pbdat &= ~PB_SCL
I2C_DELAY
This delay is invoked four times per clock cycle so this
controls the rate of data transfer. The data rate thus
is 1 / (I2C_DELAY * 4). Often defined to be something
like:
#define I2C_DELAY udelay(2)
CONFIG_SOFT_I2C_GPIO_SCL / CONFIG_SOFT_I2C_GPIO_SDA
If your arch supports the generic GPIO framework (asm/gpio.h),
then you may alternatively define the two GPIOs that are to be
used as SCL / SDA. Any of the previous I2C_xxx macros will
have GPIO-based defaults assigned to them as appropriate.
You should define these to the GPIO value as given directly to
the generic GPIO functions.
CFG_SYS_I2C_NOPROBES
This option specifies a list of I2C devices that will be skipped
when the 'i2c probe' command is issued.
e.g.
#define CFG_SYS_I2C_NOPROBES {0x50,0x68}
will skip addresses 0x50 and 0x68 on a board with one I2C bus
CONFIG_SOFT_I2C_READ_REPEATED_START
defining this will force the i2c_read() function in
the soft_i2c driver to perform an I2C repeated start
between writing the address pointer and reading the
data. If this define is omitted the default behaviour
of doing a stop-start sequence will be used. Most I2C
devices can use either method, but some require one or
the other.
- SPI Support: CONFIG_SPI
Enables SPI driver (so far only tested with
@@ -1544,7 +1662,7 @@ New uImage format (FIT)
Flexible and powerful format based on Flattened Image Tree -- FIT (similar
to Flattened Device Tree). It allows the use of images with multiple
components (several kernels, ramdisks, etc.), with contents protected by
SHA1, MD5 or CRC32. More details are found in the doc/usage/fit directory.
SHA1, MD5 or CRC32. More details are found in the doc/uImage.FIT directory.
Old uImage format
@@ -2281,5 +2399,5 @@ Contributing
The U-Boot projects depends on contributions from the user community.
If you want to participate, please, have a look at the 'General'
section of https://docs.u-boot-project.org/en/latest/develop/index.html
section of https://docs.u-boot.org/en/latest/develop/index.html
where we describe coding standards and the patch submission process.
arch/Kconfig
+4 -20
View File
@@ -159,7 +159,6 @@ config PPC
config RISCV
bool "RISC-V architecture"
select CREATE_ARCH_SYMLINK
select HAVE_PRIVATE_LIBGCC if 64BIT
select HAVE_SETJMP
select HAVE_INITJMP
select SUPPORT_ACPI
@@ -190,7 +189,6 @@ config SANDBOX
select HAVE_SETJMP
select HAVE_INITJMP
select ARCH_SUPPORTS_LTO
select AXI
select BOARD_LATE_INIT
select BZIP2
select CMD_POWEROFF if CMDLINE
@@ -200,37 +198,24 @@ config SANDBOX
select DM_GPIO
select DM_I2C
select DM_KEYBOARD
select DM_MAILBOX
select DM_RESET
select DM_SERIAL
select DM_SPI
select DM_SPI_FLASH
select GPIO
select GZIP_COMPRESSED
select I2C
select LZO
select MMC
select MTD
select OF_BOARD_SETUP
select OF_CONTROL
select PCI_ENDPOINT
select SANDBOX_RESET
select SPI
select SERIAL
select SUPPORT_OF_CONTROL
select SUPPORT_BIG_ENDIAN
select SUPPORT_LITTLE_ENDIAN
select SYSRESET
select SYSRESET_CMD_RESET
select SYSRESET_CMD_POWEROFF if SYSRESET && CMD_POWEROFF
select SYSRESET_CMD_POWEROFF if CMD_POWEROFF
select SYS_CACHE_SHIFT_4
select IRQ
select SUPPORT_EXTENSION_SCAN if CMDLINE
select SUPPORT_ACPI
select TIMER
select SPL_TIMER if SPL
select TPL_TIMER if TPL
select VPL_TIMER if VPL
imply BITREVERSE
select BLOBLIST
imply LTO
@@ -254,7 +239,7 @@ config SANDBOX
imply AVB_VERIFY
imply LIBAVB
imply CMD_AVB
imply PARTITION_TYPE_GUID if EFI_PARTITION
imply PARTITION_TYPE_GUID
imply SCP03
imply CMD_SCP03
imply UDP_FUNCTION_FASTBOOT
@@ -264,7 +249,7 @@ config SANDBOX
# Re-enable this when fully implemented
# imply VIRTIO_BLK
imply VIRTIO_NET
imply SOUND
imply DM_SOUND
imply PCI_SANDBOX_EP
imply PCH
imply PHYLIB
@@ -280,6 +265,7 @@ config SANDBOX
imply PHY_FIXED
imply DM_DSA
imply CMD_EXTENSION
imply KEYBOARD
imply PHYSMEM
imply GENERATE_ACPI_TABLE
imply BINMAN
@@ -297,7 +283,6 @@ config SH
config X86
bool "x86 architecture"
select AHCI
select HAVE_SETJMP
select SUPPORT_SPL
select SUPPORT_TPL
@@ -306,7 +291,6 @@ config X86
select DM
select HAVE_ARCH_IOMAP
select HAVE_PRIVATE_LIBGCC
select LMB_ARCH_MEM_MAP
select OF_CONTROL
select PCI
select SUPPORT_ACPI
arch/arc/lib/bootm.c
+9 -2
View File
@@ -10,6 +10,9 @@
#include <irq_func.h>
#include <log.h>
#include <asm/cache.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
static int cleanup_before_linux(void)
{
@@ -50,13 +53,17 @@ static void boot_jump_linux(struct bootm_headers *images, int flag)
{
ulong kernel_entry;
unsigned int r0, r2;
int fake = (flag & BOOTM_STATE_OS_FAKE_GO);
kernel_entry = images->ep;
debug("## Transferring control to Linux (at address %08lx)...\n",
kernel_entry);
bootstage_mark(BOOTSTAGE_ID_RUN_OS);
bootm_final(flag);
printf("\nStarting kernel ...%s\n\n", fake ?
"(fake run for tracing)" : "");
bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel");
if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) {
r0 = 2;
@@ -68,7 +75,7 @@ static void boot_jump_linux(struct bootm_headers *images, int flag)
cleanup_before_linux();
if (!(flag & BOOTM_STATE_OS_FAKE_GO))
if (!fake)
board_jump_and_run(kernel_entry, r0, 0, r2);
}
arch/arm/Kconfig
+45 -52
View File
@@ -30,7 +30,7 @@ config COUNTER_FREQUENCY
ROCKCHIP_RK3288 || ROCKCHIP_RK322X || ROCKCHIP_RK3036
default 25000000 if ARCH_LX2160A || ARCH_LX2162A || ARCH_LS1088A
default 100000000 if ARCH_ZYNQMP
default 200000000 if ARCH_SOCFPGA_AGILEX5 || ARCH_SOCFPGA_AGILEX7M
default 200000000 if TARGET_SOCFPGA_AGILEX5 || TARGET_SOCFPGA_AGILEX7M
default 0
help
For platforms with ARMv8-A and ARMv7-A which features a system
@@ -363,8 +363,7 @@ config CPU_V7A
select SYS_CACHE_SHIFT_6
imply SYS_ARM_MMU
# ARMv7-M/ARMv8-M
config CPU_V7M_V8M
config CPU_V7M
bool
select HAS_THUMB2
select SYS_ARM_MPU
@@ -373,10 +372,6 @@ config CPU_V7M_V8M
select THUMB2_KERNEL
select NVIC
config CPU_V7M
bool
select CPU_V7M_V8M
config CPU_V7R
bool
select HAS_THUMB2
@@ -384,10 +379,6 @@ config CPU_V7R
select SYS_ARM_MPU
select SYS_CACHE_SHIFT_6
config CPU_V8M
bool
select CPU_V7M_V8M
config SYS_CPU
default "arm720t" if CPU_ARM720T
default "arm920t" if CPU_ARM920T
@@ -398,7 +389,6 @@ config SYS_CPU
default "armv7" if CPU_V7A
default "armv7" if CPU_V7R
default "armv7m" if CPU_V7M
default "armv7m" if CPU_V8M
default "armv8" if ARM64
config SYS_ARM_ARCH
@@ -412,7 +402,6 @@ config SYS_ARM_ARCH
default 7 if CPU_V7A
default 7 if CPU_V7M
default 7 if CPU_V7R
default 7 if CPU_V8M
default 8 if ARM64
choice
@@ -456,7 +445,7 @@ config ARCH_CPU_INIT
config SYS_ARCH_TIMER
bool "ARM Generic Timer support"
depends on CPU_V7A || CPU_V7M_V8M || ARM64
depends on CPU_V7A || CPU_V7M || ARM64
default y if ARM64
help
The ARM Generic Timer (aka arch-timer) provides an architected
@@ -681,6 +670,13 @@ config ARCH_MVEBU
select SPI
imply CMD_DM
config ARCH_ORION5X
bool "Marvell Orion"
select CPU_ARM926EJS
select GPIO_EXTRA_HEADER
select SPL_SEPARATE_BSS if SPL
select TIMER
config ARCH_BCM283X
bool "Broadcom BCM283X family"
select CPU
@@ -839,15 +835,10 @@ config ARCH_K3
select FIT_SIGNATURE if ARM64
select DMA_ADDR_T_64BIT
select LTO
select SPL_LOAD_FIT if SPL
select SPL_USE_TINY_PRINTF_POINTER_SUPPORT if SPL_USE_TINY_PRINTF && DFU && CPU_V7R
imply TI_SECURE_DEVICE
imply DM_RNG if ARM64
imply TEE if ARM64
imply OPTEE if ARM64
imply TPM if ARM64 && MMC
imply TPM2_FTPM_TEE if ARM64 && MMC
imply SUPPORT_EMMC_RPMB if ARM64 && MMC
config ARCH_OMAP2PLUS
bool "TI OMAP2+"
@@ -873,6 +864,7 @@ config ARCH_MESON
config ARCH_MEDIATEK
bool "MediaTek SoCs"
select DM
select GPIO_EXTRA_HEADER
select OF_CONTROL
select SPL_DM if SPL
select SPL_LIBCOMMON_SUPPORT if SPL
@@ -1082,7 +1074,6 @@ config ARCH_APPLE
imply CMD_GPT
imply BOOTSTD_FULL
imply OF_HAS_PRIOR_STAGE
imply OF_UPSTREAM
config ARCH_OWL
bool "Actions Semi OWL SoCs"
@@ -1152,7 +1143,6 @@ config ARCH_SNAPDRAGON
select SYSRESET
select SYSRESET_PSCI
select ANDROID_BOOT_IMAGE_IGNORE_BLOB_ADDR
select MMU_PGPROT
imply OF_UPSTREAM
imply CMD_DM
imply DM_USB_GADGET
@@ -1160,35 +1150,35 @@ config ARCH_SNAPDRAGON
config ARCH_SOCFPGA
bool "Altera SOCFPGA family"
select ARCH_EARLY_INIT_R
select ARCH_MISC_INIT if !ARCH_SOCFPGA_ARRIA10
select ARM64 if ARCH_SOCFPGA_SOC64
select CPU_V7A if ARCH_SOCFPGA_GEN5 || ARCH_SOCFPGA_ARRIA10
select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10
select ARM64 if TARGET_SOCFPGA_SOC64
select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select DM
select DM_SERIAL
select GPIO_EXTRA_HEADER
select ENABLE_ARM_SOC_BOOT0_HOOK if ARCH_SOCFPGA_GEN5 || ARCH_SOCFPGA_ARRIA10
select LMB_ARCH_MEM_MAP if ARCH_SOCFPGA_SOC64
select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select LMB_ARCH_MEM_MAP if TARGET_SOCFPGA_SOC64
select OF_CONTROL
select SPL_DM_RESET if DM_RESET
select SPL_DM_SERIAL
select SPL_LIBCOMMON_SUPPORT
select SPL_LIBGENERIC_SUPPORT
select SPL_OF_CONTROL
select SPL_SEPARATE_BSS if ARCH_SOCFPGA_SOC64
select SPL_DRIVERS_MISC if ARCH_SOCFPGA_SOC64
select SPL_SOCFPGA_DT_REG if ARCH_SOCFPGA_SOC64
select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64
select SPL_DRIVERS_MISC if TARGET_SOCFPGA_SOC64
select SPL_SOCFPGA_DT_REG if TARGET_SOCFPGA_SOC64
select SPL_SERIAL
select SPL_SYSRESET
select SPL_WATCHDOG
select SUPPORT_SPL
select SYS_NS16550
select SYS_THUMB_BUILD if ARCH_SOCFPGA_GEN5 || ARCH_SOCFPGA_ARRIA10
select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select SYSRESET
select SYSRESET_SOCFPGA if ARCH_SOCFPGA_GEN5 || ARCH_SOCFPGA_ARRIA10
select SYSRESET_SOCFPGA_SOC64 if !ARCH_SOCFPGA_AGILEX5 && \
ARCH_SOCFPGA_SOC64
select SYSRESET_PSCI if ARCH_SOCFPGA_AGILEX5
select USE_BOOTFILE if SPL_ATF && ARCH_SOCFPGA_SOC64
select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select SYSRESET_SOCFPGA_SOC64 if !TARGET_SOCFPGA_AGILEX5 && \
TARGET_SOCFPGA_SOC64
select SYSRESET_PSCI if TARGET_SOCFPGA_AGILEX5
select USE_BOOTFILE if SPL_ATF && TARGET_SOCFPGA_SOC64
imply CMD_DM
imply CMD_MTDPARTS
imply CRC32_VERIFY
@@ -2169,6 +2159,7 @@ config TARGET_POMELO
select SCSI_AHCI
select AHCI_PCI
select PCI
select DM_PCI
select SCSI
select DM_SERIAL
imply CMD_PCI
@@ -2354,6 +2345,8 @@ source "arch/arm/mach-omap2/Kconfig"
source "arch/arm/cpu/armv8/fsl-layerscape/Kconfig"
source "arch/arm/mach-orion5x/Kconfig"
source "arch/arm/mach-owl/Kconfig"
source "arch/arm/mach-renesas/Kconfig"
@@ -2429,23 +2422,23 @@ source "board/cavium/thunderx/Kconfig"
source "board/eets/pdu001/Kconfig"
source "board/emulation/qemu-arm/Kconfig"
source "board/emulation/qemu-sbsa/Kconfig"
source "board/nxp/ls2080aqds/Kconfig"
source "board/nxp/ls2080ardb/Kconfig"
source "board/nxp/ls1088a/Kconfig"
source "board/nxp/ls1028a/Kconfig"
source "board/nxp/ls1021aqds/Kconfig"
source "board/nxp/ls1043aqds/Kconfig"
source "board/nxp/ls1021atwr/Kconfig"
source "board/nxp/ls1021atsn/Kconfig"
source "board/nxp/ls1021aiot/Kconfig"
source "board/nxp/ls1046aqds/Kconfig"
source "board/nxp/ls1043ardb/Kconfig"
source "board/nxp/ls1046ardb/Kconfig"
source "board/nxp/ls1046afrwy/Kconfig"
source "board/nxp/ls1012aqds/Kconfig"
source "board/nxp/ls1012ardb/Kconfig"
source "board/nxp/ls1012afrdm/Kconfig"
source "board/nxp/lx2160a/Kconfig"
source "board/freescale/ls2080aqds/Kconfig"
source "board/freescale/ls2080ardb/Kconfig"
source "board/freescale/ls1088a/Kconfig"
source "board/freescale/ls1028a/Kconfig"
source "board/freescale/ls1021aqds/Kconfig"
source "board/freescale/ls1043aqds/Kconfig"
source "board/freescale/ls1021atwr/Kconfig"
source "board/freescale/ls1021atsn/Kconfig"
source "board/freescale/ls1021aiot/Kconfig"
source "board/freescale/ls1046aqds/Kconfig"
source "board/freescale/ls1043ardb/Kconfig"
source "board/freescale/ls1046ardb/Kconfig"
source "board/freescale/ls1046afrwy/Kconfig"
source "board/freescale/ls1012aqds/Kconfig"
source "board/freescale/ls1012ardb/Kconfig"
source "board/freescale/ls1012afrdm/Kconfig"
source "board/freescale/lx2160a/Kconfig"
source "board/grinn/chiliboard/Kconfig"
source "board/hisilicon/hikey/Kconfig"
source "board/hisilicon/hikey960/Kconfig"
arch/arm/Makefile
+1 -2
View File
@@ -16,7 +16,6 @@ arch-$(CONFIG_CPU_V7A) =$(call cc-option, -march=armv7-a, \
$(call cc-option, -march=armv7))
arch-$(CONFIG_CPU_V7M) =-march=armv7-m
arch-$(CONFIG_CPU_V7R) =-march=armv7-r
arch-$(CONFIG_CPU_V8M) =-march=armv8-m.main
ifeq ($(CONFIG_ARM64_CRC32),y)
arch-$(CONFIG_ARM64) =-march=armv8-a+crc
else
@@ -43,7 +42,6 @@ tune-$(CONFIG_CPU_ARM1136) =
tune-$(CONFIG_CPU_ARM1176) =
tune-$(CONFIG_CPU_V7A) =-mtune=generic-armv7-a
tune-$(CONFIG_CPU_V7R) =
tune-$(CONFIG_CPU_V8M) =
tune-$(CONFIG_ARM64) =
# Evaluate tune cc-option calls now
@@ -77,6 +75,7 @@ machine-$(CONFIG_ARCH_MVEBU) += mvebu
machine-$(CONFIG_ARCH_NEXELL) += nexell
machine-$(CONFIG_ARCH_NPCM) += npcm
machine-$(CONFIG_ARCH_OMAP2PLUS) += omap2
machine-$(CONFIG_ARCH_ORION5X) += orion5x
machine-$(CONFIG_ARCH_OWL) += owl
machine-$(CONFIG_ARCH_RENESAS) += renesas
machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip
arch/arm/config.mk
-8
View File
@@ -112,14 +112,6 @@ endif
# needed for relocation
LDFLAGS_u-boot += -pie
ifeq ($(CONFIG_ARM64),y)
# U-Boot uses fixed 4K granules, so we force the linker to match.
# Otherwise, we're subject to toolchain preferences, (e.g Fedora's
# aarch64-linux-none toolchain selects 64K granules) and we end up wasting
# a lot of space in ELFs with MMU_PGPROT enabled.
LDFLAGS_u-boot += -z common-page-size=0x1000 -z max-page-size=0x1000
endif
#
# FIXME: binutils versions < 2.22 have a bug in the assembler where
# branches to weak symbols can be incorrectly optimized in thumb mode
arch/arm/cpu/arm1136/u-boot-spl.lds
+2 -6
View File
@@ -30,10 +30,8 @@ SECTIONS
.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
. = ALIGN(4);
.data : {
*(SORT_BY_ALIGNMENT(.data*))
. = ALIGN(8);
} >.sram
.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
. = ALIGN(4);
__image_copy_end = .;
_end = .;
@@ -46,5 +44,3 @@ SECTIONS
__bss_end = .;
} >.sdram
}
ASSERT(_end % 8 == 0, "_end must be 8-byte aligned for device tree");
arch/arm/cpu/arm926ejs/mxs/Makefile
+12 -12
View File
@@ -26,7 +26,7 @@ MKIMAGE_TARGET-$(CONFIG_MX28) = mxsimage$(CONFIG_SPL_FRAMEWORK:%=-spl).mx28.cfg
#
quiet_cmd_mkivt_mxs = MXSIVT $@
cmd_mkivt_mxs = \
sz=`expr \`stat -c "%s" $<\` + 64 + 3904 + 128` ; \
sz=`expr \`stat -c "%s" $^\` + 64 + 3904 + 128` ; \
echo -n "0x402000d1 $2 0 0 0 $3 $4 0 $$sz 0 0 0 0 0 0 0" | \
tr -s " " | xargs -d " " -i printf "%08x\n" "{}" | rev | \
sed "s/\(.\)\(.\)/\\\\\\\\x\2\1\n/g" | xargs -i printf "{}" >$@
@@ -34,15 +34,15 @@ cmd_mkivt_mxs = \
# Align binary to 64B
quiet_cmd_mkalign_mxs = MXSALGN $@
cmd_mkalign_mxs = \
dd if=$< of=$@ ibs=64 conv=sync 2>/dev/null && \
mv $@ $<
dd if=$^ of=$@ ibs=64 conv=sync 2>/dev/null && \
mv $@ $^
# Assemble the CSF file
quiet_cmd_mkcsfreq_mxs = MXSCSFR $@
cmd_mkcsfreq_mxs = \
ivt=$(word 1,$(real-prereqs)) ; \
bin=$(word 2,$(real-prereqs)) ; \
csf=$(word 3,$(real-prereqs)) ; \
ivt=$(word 1,$^) ; \
bin=$(word 2,$^) ; \
csf=$(word 3,$^) ; \
sed "s@VENDOR@$(VENDOR)@g;s@BOARD@$(BOARD)@g" "$$csf" | \
sed '/^\#\#Blocks/ d' > $@ ; \
echo " Blocks = $2 0x0 `stat -c '%s' $$bin` \"$$bin\" , \\" >> $@ ; \
@@ -50,26 +50,26 @@ cmd_mkcsfreq_mxs = \
# Sign files
quiet_cmd_mkcst_mxs = MXSCST $@
cmd_mkcst_mxs = cst -o $@ < $< \
cmd_mkcst_mxs = cst -o $@ < $^ \
$(if $(KBUILD_VERBOSE:1=), >/dev/null)
spl/u-boot-spl.ivt: spl/u-boot-spl.bin FORCE
spl/u-boot-spl.ivt: spl/u-boot-spl.bin
$(call if_changed,mkalign_mxs)
$(call if_changed,mkivt_mxs,$(CONFIG_SPL_TEXT_BASE),\
0x00008000,0x00008040)
u-boot.ivt: u-boot.bin FORCE
u-boot.ivt: u-boot.bin
$(call if_changed,mkalign_mxs)
$(call if_changed,mkivt_mxs,$(CONFIG_TEXT_BASE),\
0x40001000,0x40001040)
spl/u-boot-spl.csf: spl/u-boot-spl.ivt spl/u-boot-spl.bin board/$(VENDOR)/$(BOARD)/sign/u-boot-spl.csf FORCE
spl/u-boot-spl.csf: spl/u-boot-spl.ivt spl/u-boot-spl.bin board/$(VENDOR)/$(BOARD)/sign/u-boot-spl.csf
$(call if_changed,mkcsfreq_mxs,$(CONFIG_SPL_TEXT_BASE),0x8000)
u-boot.csf: u-boot.ivt u-boot.bin board/$(VENDOR)/$(BOARD)/sign/u-boot.csf FORCE
u-boot.csf: u-boot.ivt u-boot.bin board/$(VENDOR)/$(BOARD)/sign/u-boot.csf
$(call if_changed,mkcsfreq_mxs,$(CONFIG_TEXT_BASE),0x40001000)
%.sig: %.csf FORCE
%.sig: %.csf
$(call if_changed,mkcst_mxs)
MKIMAGEFLAGS_u-boot.sb = -n $< -T mxsimage
arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
+9 -4
View File
@@ -33,11 +33,19 @@ SECTIONS
*(.data*)
}
. = ALIGN(4);
.rel.dyn : {
__rel_dyn_start = .;
*(.rel*)
__rel_dyn_end = .;
}
.bss : {
. = ALIGN(4);
__bss_start = .;
*(.bss*)
. = ALIGN(8);
. = ALIGN(4);
__bss_end = .;
}
@@ -54,6 +62,3 @@ SECTIONS
.gnu : { *(.gnu*) }
.ARM.exidx : { *(.ARM.exidx*) }
}
ASSERT(_image_binary_end % 8 == 0, \
"_image_binary_end must be 8-byte aligned for device tree");
arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds
+1 -4
View File
@@ -31,9 +31,9 @@ SECTIONS
. = ALIGN(4);
__u_boot_list : {
KEEP(*(SORT(__u_boot_list*)));
. = ALIGN(8);
} > .sram
. = ALIGN(4);
__image_copy_end = .;
_end = .;
_image_binary_end = .;
@@ -47,6 +47,3 @@ SECTIONS
__bss_end = .;
} > .sdram
}
ASSERT(_image_binary_end % 8 == 0, \
"_image_binary_end must be 8-byte aligned for device tree");
arch/arm/cpu/armv7/s5p4418/cpu.c
+3
View File
@@ -7,6 +7,7 @@
#include <command.h>
#include <asm/system.h>
#include <asm/cache.h>
#include <asm/global_data.h>
#include <asm/sections.h>
#include <asm/io.h>
#include <asm/arch/nexell.h>
@@ -14,6 +15,8 @@
#include <asm/arch/tieoff.h>
#include <cpu_func.h>
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_ARCH_CPU_INIT
#error must be define the macro "CONFIG_ARCH_CPU_INIT"
#endif
arch/arm/cpu/armv7/sunxi/u-boot-spl.lds
+1 -4
View File
@@ -40,9 +40,9 @@ SECTIONS
. = ALIGN(4);
__u_boot_list : {
KEEP(*(SORT(__u_boot_list*)));
. = ALIGN(8);
} > .sram
. = ALIGN(4);
__image_copy_end = .;
_end = .;
_image_binary_end = .;
@@ -56,6 +56,3 @@ SECTIONS
__bss_end = .;
} > .sdram
}
ASSERT(_image_binary_end % 8 == 0, \
"_image_binary_end must be 8-byte aligned for device tree");
arch/arm/cpu/armv7/vf610/Kconfig
+1 -1
View File
@@ -30,7 +30,7 @@ endchoice
config SYS_SOC
default "vf610"
source "board/nxp/vf610twr/Kconfig"
source "board/freescale/vf610twr/Kconfig"
source "board/phytec/pcm052/Kconfig"
source "board/toradex/colibri_vf/Kconfig"
arch/arm/cpu/armv7/vf610/Makefile
+1 -1
View File
@@ -7,5 +7,5 @@ obj-y += timer.o
MKIMAGEFLAGS_u-boot.vyb = -T vybridimage
u-boot.vyb: u-boot.imx FORCE
u-boot.vyb: u-boot.imx
$(call if_changed,mkimage)
arch/arm/cpu/armv7m/cpu.c
+2 -8
View File
@@ -19,9 +19,6 @@
*/
int cleanup_before_linux(void)
{
if (!CONFIG_IS_ENABLED(LIB_BOOTM) && !CONFIG_IS_ENABLED(LIB_BOOTZ))
return 0;
/*
* this function is called just before we call linux
* it prepares the processor for linux
@@ -48,9 +45,8 @@ int cleanup_before_linux(void)
}
/*
* Perform the low-level reset. ARMv7M only.
* Perform the low-level reset.
*/
#if IS_ENABLED(CONFIG_CPU_V7M)
void reset_cpu(void)
{
/*
@@ -60,10 +56,8 @@ void reset_cpu(void)
| (V7M_SCB->aircr & V7M_AIRCR_PRIGROUP_MSK)
| V7M_AIRCR_SYSRESET, &V7M_SCB->aircr);
}
#endif
void spl_perform_arch_fixups(struct spl_image_info *spl_image)
{
if (IS_ENABLED(CONFIG_XPL_BUILD))
spl_image->entry_point |= 0x1;
spl_image->entry_point |= 0x1;
}
arch/arm/cpu/armv8/cache_v8.c
+3 -7
View File
@@ -810,10 +810,8 @@ __weak void mmu_setup(void)
el = current_el();
set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(NULL, NULL),
MEMORY_ATTRIBUTES);
}
void mmu_enable(void)
{
/* enable the mmu */
set_sctlr(get_sctlr() | CR_M);
}
@@ -880,17 +878,15 @@ void flush_dcache_range(unsigned long start, unsigned long stop)
void dcache_enable(void)
{
/* The data cache is not active unless the mmu is enabled */
if (!mmu_status()) {
__asm_invalidate_tlb_all();
if (!mmu_status())
mmu_setup();
mmu_enable();
}
/* Set up page tables only once (it is done also by mmu_setup()) */
if (!gd->arch.tlb_fillptr)
setup_all_pgtables();
invalidate_dcache_all();
__asm_invalidate_tlb_all();
set_sctlr(get_sctlr() | CR_C);
}
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
-1
View File
@@ -382,7 +382,6 @@ menu "Layerscape architecture"
config FSL_LAYERSCAPE
bool
select ARM_SMCCC
select LMB_ARCH_MEM_MAP
config HAS_FEATURE_GIC64K_ALIGN
bool
arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+2 -7
View File
@@ -1143,7 +1143,7 @@ int arch_early_init_r(void)
#ifdef CONFIG_SYS_HAS_SERDES
fsl_serdes_init();
#endif
#if defined(CONFIG_SYS_FSL_HAS_RGMII) && defined(CONFIG_FSL_MC_ENET)
#ifdef CONFIG_SYS_FSL_HAS_RGMII
/* some dpmacs in armv8a based freescale layerscape SOCs can be
* configured via both serdes(sgmii, 10gbase-r, xlaui etc) bits and via
* EC*_PMUX(rgmii) bits in RCW.
@@ -1158,10 +1158,6 @@ int arch_early_init_r(void)
* function of SOC, the dpmac will be enabled as RGMII even if it was
* also enabled before as SGMII. If ECx_PMUX is not configured for
* RGMII, DPMAC will remain configured as SGMII from fsl_serdes_init().
*
* fsl_rgmii_init() itself is only built under CONFIG_FSL_MC_ENET
* (drivers/net/ldpaa_eth/); gate the call the same way so builds
* without MC-ENET still link.
*/
fsl_rgmii_init();
#endif
@@ -1553,8 +1549,7 @@ void lmb_arch_add_memory(void)
gd->arch.resv_ram < ram_start + ram_size)
ram_size = gd->arch.resv_ram - ram_start;
#endif
if (ram_size > 0)
lmb_add(ram_start, ram_size);
lmb_add(ram_start, ram_size);
}
}
#endif
arch/arm/cpu/armv8/fsl-layerscape/fdt.c
-57
View File
@@ -12,7 +12,6 @@
#include <asm/cache.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
#include <malloc.h>
#include <phy.h>
#ifdef CONFIG_FSL_LSCH3
#include <asm/arch/fdt.h>
@@ -49,61 +48,6 @@ int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc)
}
#ifdef CONFIG_MP
static void fdt_fixup_thermal_cooling_device(void *blob, int cpu_off)
{
int cnt, idx, len;
int map, maps;
int offline, phandle;
int ret;
int zone, zones;
u32 *tbl;
struct fdtdec_phandle_args dev;
zones = fdt_subnode_offset(blob, 0, "thermal-zones");
if (zones < 0)
return;
offline = fdt_get_phandle(blob, cpu_off);
fdt_for_each_subnode(zone, blob, zones) {
maps = fdt_subnode_offset(blob, zone, "cooling-maps");
if (maps < 0)
continue;
fdt_for_each_subnode(map, blob, maps) {
if (!fdt_getprop(blob, map, "cooling-device", &len))
continue;
cnt = fdtdec_parse_phandle_with_args(blob, map,
"cooling-device",
"#cooling-cells",
0, -1, NULL);
if (cnt <= 0)
continue;
tbl = (u32 *)malloc(len);
if (!tbl)
return;
idx = 0;
for (int i = 0; i < cnt; i++) {
ret = fdtdec_parse_phandle_with_args(blob, map,
"cooling-device",
"#cooling-cells",
0, i,
&dev);
if (ret < 0)
goto skip_update;
phandle = fdt_get_phandle(blob, dev.node);
if (phandle == offline)
continue;
tbl[idx++] = cpu_to_fdt32(phandle);
for (int j = 0; j < dev.args_count; j++)
tbl[idx++] = cpu_to_fdt32(dev.args[j]);
}
fdt_setprop(blob, map, "cooling-device", tbl,
(idx*sizeof(*tbl)));
skip_update:
free(tbl);
}
}
}
void ft_fixup_cpu(void *blob)
{
int off;
@@ -129,7 +73,6 @@ void ft_fixup_cpu(void *blob)
if (reg) {
core_id = fdt_read_number(reg, addr_cells);
if (!test_bit(id_to_core(core_id), &mask)) {
fdt_fixup_thermal_cooling_device(blob, off);
fdt_del_node(blob, off);
off = off_prev;
}
arch/arm/cpu/armv8/fwcall.c
-15
View File
@@ -129,18 +129,3 @@ void __noreturn psci_system_off(void)
while (1)
;
}
int psci_features(u32 psci_func_id)
{
struct pt_regs regs;
regs.regs[0] = ARM_PSCI_1_0_FN_PSCI_FEATURES;
regs.regs[1] = psci_func_id;
if (use_smc_for_psci)
smc_call(&regs);
else
hvc_call(&regs);
return regs.regs[0];
}
arch/arm/cpu/armv8/u-boot-spl.lds
+2 -13
View File
@@ -49,20 +49,12 @@ SECTIONS
} >.sram
#endif
.binman_sym_table : {
. = ALIGN(8);
__binman_sym_start = .;
KEEP(*(SORT(.binman_sym*)));
__binman_sym_end = .;
. = ALIGN(8);
} > .sram
__u_boot_list : {
. = ALIGN(8);
KEEP(*(SORT(__u_boot_list*)));
. = ALIGN(8);
} >.sram
. = ALIGN(8);
__image_copy_end = .;
_end = .;
_image_binary_end = .;
@@ -75,7 +67,7 @@ SECTIONS
__bss_end = .;
} >.sdram
#else
.bss _image_binary_end (OVERLAY) : {
.bss (NOLOAD) : {
__bss_start = .;
*(.bss*)
. = ALIGN(8);
@@ -97,8 +89,5 @@ SECTIONS
#endif
}
ASSERT(_image_binary_end % 8 == 0, \
"_image_binary_end must be 8-byte aligned for device tree");
ASSERT(ADDR(.bss) % 8 == 0, \
".bss must be 8-byte aligned");
arch/arm/cpu/armv8/u-boot.lds
-3
View File
@@ -146,7 +146,6 @@ SECTIONS
__rel_dyn_start = .;
*(.rela*)
__rel_dyn_end = .;
. = ALIGN(8);
}
_end = .;
@@ -176,5 +175,3 @@ SECTIONS
#include "linux-kernel-image-header-vars.h"
#endif
}
ASSERT(_end % 8 == 0, "_end must be 8-byte aligned for device tree");
arch/arm/cpu/u-boot-spl.lds
+14 -8
View File
@@ -31,6 +31,11 @@ SECTIONS
*(.data*)
}
. = ALIGN(4);
__u_boot_list : {
KEEP(*(SORT(__u_boot_list*)));
}
. = ALIGN(4);
.binman_sym_table : {
__binman_sym_start = .;
@@ -39,16 +44,20 @@ SECTIONS
}
. = ALIGN(4);
__u_boot_list : {
KEEP(*(SORT(__u_boot_list*)));
. = ALIGN(8);
}
__image_copy_end = .;
.rel.dyn : {
__rel_dyn_start = .;
*(.rel*)
__rel_dyn_end = .;
}
. = ALIGN(8);
_image_binary_end = .;
_end = .;
.bss _image_binary_end (OVERLAY) : {
.bss __rel_dyn_start (OVERLAY) : {
__bss_start = .;
*(.bss*)
. = ALIGN(8);
@@ -71,9 +80,6 @@ ASSERT(__image_copy_end - __image_copy_start <= (IMAGE_MAX_SIZE), \
"SPL image too big");
#endif
ASSERT(_image_binary_end % 8 == 0, \
"_image_binary_end must be 8-byte aligned for device tree");
#if defined(CONFIG_SPL_BSS_MAX_SIZE)
ASSERT(__bss_end - __bss_start <= (CONFIG_SPL_BSS_MAX_SIZE), \
"SPL image BSS too big");
arch/arm/cpu/u-boot.lds
-4
View File
@@ -164,7 +164,6 @@ SECTIONS
__rel_dyn_start = .;
*(.rel*)
__rel_dyn_end = .;
. = ALIGN(8);
}
_end = .;
@@ -193,6 +192,3 @@ SECTIONS
/DISCARD/ : { *(.ARM.exidx*) }
/DISCARD/ : { *(.gnu.linkonce.armexidx.*) }
}
ASSERT(_image_binary_end % 8 == 0, \
"_image_binary_end must be 8-byte aligned for device tree");
arch/arm/dts/Makefile
+34 -16
View File
@@ -32,6 +32,13 @@ dtb-$(CONFIG_TARGET_A5Y17LTE) += exynos78x0-axy17lte.dtb
dtb-$(CONFIG_TARGET_A3Y17LTE) += exynos78x0-axy17lte.dtb
dtb-$(CONFIG_TARGET_A7Y17LTE) += exynos78x0-axy17lte.dtb
dtb-$(CONFIG_ARCH_APPLE) += \
t8103-j274.dtb \
t8103-j293.dtb \
t8103-j313.dtb \
t8103-j456.dtb \
t8103-j457.dtb
dtb-$(CONFIG_ARCH_DAVINCI) += \
da850-lcdk.dtb \
da850-lego-ev3.dtb
@@ -45,6 +52,23 @@ dtb-$(CONFIG_MACH_S900) += \
dtb-$(CONFIG_MACH_S700) += \
s700-cubieboard7.dtb
dtb-$(CONFIG_ROCKCHIP_RK3128) += \
rk3128-evb.dtb
dtb-$(CONFIG_ROCKCHIP_RK322X) += \
rk3229-evb.dtb
dtb-$(CONFIG_ROCKCHIP_RK3288) += \
rk3288-evb.dtb \
rk3288-popmetal.dtb \
rk3288-rock2-square.dtb \
rk3288-rock-pi-n8.dtb \
rk3288-veyron-jerry.dtb \
rk3288-veyron-mickey.dtb \
rk3288-veyron-minnie.dtb \
rk3288-veyron-speedy.dtb \
rk3288-vyasa.dtb
dtb-$(CONFIG_ROCKCHIP_RK3368) += \
rk3368-sheep.dtb \
rk3368-geekbox.dtb \
@@ -427,7 +451,6 @@ dtb-$(CONFIG_TARGET_THUNDERX_88XX) += thunderx-88xx.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_agilex5_socdk.dtb \
socfpga_agilex5_socdk_emmc.dtb \
socfpga_arria5_secu1.dtb \
socfpga_arria5_socdk.dtb \
socfpga_arria10_chameleonv3_270_2.dtb \
@@ -445,8 +468,6 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_cyclone5_socrates.dtb \
socfpga_cyclone5_sr1500.dtb \
socfpga_cyclone5_vining_fpga.dtb \
socfpga_cyclone5_ac501soc.dtb \
socfpga_cyclone5_ac550soc.dtb \
socfpga_n5x_socdk.dtb \
socfpga_stratix10_socdk.dtb
@@ -859,6 +880,9 @@ dtb-$(CONFIG_ARCH_IMX8) += \
fsl-imx8qxp-mek.dtb \
imx8-capricorn-cxg3.dtb \
dtb-$(CONFIG_ARCH_IMX8ULP) += \
imx8ulp-evk.dtb
dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mm-data-modul-edm-sbc.dtb \
imx8mm-icore-mx8mm-ctouch2.dtb \
@@ -866,6 +890,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mm-mx8menlo.dtb \
imx8mm-phg.dtb \
imx8mq-cm.dtb \
imx8mn-var-som-symphony.dtb \
imx8mq-mnt-reform2.dtb \
imx8mq-phanbell.dtb \
imx8mp-data-modul-edm-sbc.dtb \
@@ -893,11 +918,12 @@ dtb-$(CONFIG_RZA1) += \
r7s72100-genmai.dtb \
r7s72100-gr-peach.dtb
dtb-$(CONFIG_RCAR_GEN3) += \
r8a779md-geist.dtb
dtb-$(CONFIG_RCAR_GEN5) += \
r8a78000-ironhide-cm33.dtb
r8a78000-ironhide.dtb
ifdef CONFIG_RCAR_GEN5
DTC_FLAGS += -R 4 -p 0x1000
endif
dtb-$(CONFIG_TARGET_AT91SAM9261EK) += at91sam9261ek.dtb
@@ -1065,8 +1091,7 @@ dtb-$(CONFIG_SOC_K3_J7200) += k3-j7200-r5-common-proc-board.dtb
dtb-$(CONFIG_SOC_K3_J721S2) += k3-am68-sk-r5-base-board.dtb\
k3-j721s2-r5-common-proc-board.dtb
dtb-$(CONFIG_SOC_K3_J784S4) += k3-am69-r5-aquila-dev.dtb \
k3-am69-r5-sk.dtb \
dtb-$(CONFIG_SOC_K3_J784S4) += k3-am69-r5-sk.dtb \
k3-j784s4-r5-evm.dtb
dtb-$(CONFIG_SOC_K3_J722S) += k3-j722s-r5-evm.dtb \
@@ -1090,9 +1115,6 @@ dtb-$(CONFIG_SOC_K3_AM62D2) += k3-am62d2-r5-evm.dtb
dtb-$(CONFIG_SOC_K3_AM62P5) += k3-am62p5-r5-sk.dtb \
k3-am62p5-verdin-r5.dtb
mt8371-genio-520-evk-ufs-dtbs := mt8371-genio-520-evk.dtb mt8371-genio-common-ufs.dtbo
mt8391-genio-720-evk-ufs-dtbs := mt8391-genio-720-evk.dtb mt8371-genio-common-ufs.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7622-rfb.dtb \
mt7623a-unielec-u7623-02-emmc.dtb \
@@ -1112,10 +1134,6 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7988-rfb.dtb \
mt7988-sd-rfb.dtb \
mt8183-pumpkin.dtb \
mt8371-genio-520-evk.dtb \
mt8371-genio-520-evk-ufs.dtb \
mt8391-genio-720-evk.dtb \
mt8391-genio-720-evk-ufs.dtb \
mt8512-bm1-emmc.dtb \
mt8516-pumpkin.dtb \
mt8518-ap1-emmc.dtb
arch/arm/dts/an7581-u-boot.dtsi
-76
View File
@@ -35,48 +35,6 @@
reg = <0x0 0x1fa20000 0x0 0x388>;
};
pon_pcs: pcs@1fa08000 {
compatible = "airoha,an7581-pcs-pon";
reg = <0x0 0x1fa08000 0x0 0x1000>,
<0x0 0x1fa80000 0x0 0x60>,
<0x0 0x1fa80a00 0x0 0x164>,
<0x0 0x1fa84000 0x0 0x450>,
<0x0 0x1fa85900 0x0 0x338>,
<0x0 0x1fa86000 0x0 0x300>,
<0x0 0x1fa8a000 0x0 0x1000>,
<0x0 0x1fa8b000 0x0 0x1000>;
reg-names = "xfi_mac", "hsgmii_an", "hsgmii_pcs",
"multi_sgmii", "usxgmii",
"hsgmii_rate_adp", "xfi_ana", "xfi_pma";
resets = <&scuclk EN7581_XPON_MAC_RST>,
<&scuclk EN7581_XPON_PHY_RST>;
reset-names = "mac", "phy";
airoha,scu = <&scuclk>;
};
eth_pcs: pcs@1fa09000 {
compatible = "airoha,an7581-pcs-eth";
reg = <0x0 0x1fa09000 0x0 0x1000>,
<0x0 0x1fa70000 0x0 0x60>,
<0x0 0x1fa70a00 0x0 0x164>,
<0x0 0x1fa74000 0x0 0x450>,
<0x0 0x1fa75900 0x0 0x338>,
<0x0 0x1fa76000 0x0 0x300>,
<0x0 0x1fa7a000 0x0 0x1000>,
<0x0 0x1fa7b000 0x0 0x1000>;
reg-names = "xfi_mac", "hsgmii_an", "hsgmii_pcs",
"multi_sgmii", "usxgmii",
"hsgmii_rate_adp", "xfi_ana", "xfi_pma";
resets = <&scuclk EN7581_XSI_MAC_RST>,
<&scuclk EN7581_XSI_PHY_RST>;
reset-names = "mac", "phy";
airoha,scu = <&scuclk>;
};
eth: ethernet@1fb50000 {
compatible = "airoha,en7581-eth";
reg = <0 0x1fb50000 0 0x2600>,
@@ -94,45 +52,11 @@
reset-names = "fe", "pdma", "qdma",
"hsi0-mac", "hsi1-mac", "hsi-mac",
"xfp-mac";
gdm1: ethernet@1 {
compatible = "airoha,eth-mac";
reg = <1>;
phy-mode = "internal";
status = "disabled";
fixed-link {
speed = <10000>;
full-duplex;
pause;
};
};
gdm2: ethernet@2 {
compatible = "airoha,eth-mac";
reg = <2>;
pcs = <&pon_pcs>;
status = "disabled";
};
gdm4: ethernet@4 {
compatible = "airoha,eth-mac";
reg = <4>;
pcs = <&eth_pcs>;
status = "disabled";
};
};
switch: switch@1fb58000 {
compatible = "airoha,en7581-switch";
reg = <0 0x1fb58000 0 0x8000>;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
};
};
snfi: spi@1fa10000 {
arch/arm/dts/at91-sam9x60_curiosity-u-boot.dtsi
+3 -6
View File
@@ -21,11 +21,8 @@
bootph-all;
};
options {
u-boot {
compatible = "u-boot,config";
boot-led = <&led_blue>;
};
config {
u-boot,boot-led = "blue";
};
leds {
@@ -37,7 +34,7 @@
default-state = "off";
};
led_blue: led-blue {
led-blue {
default-state = "off";
};
};
arch/arm/dts/at91sam9g45-corvus.dts
-11
View File
@@ -10,7 +10,6 @@
* 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
*/
/dts-v1/;
#include <dt-bindings/leds/common.h>
#include "at91sam9g45.dtsi"
/ {
@@ -107,14 +106,4 @@
status = "okay";
};
};
leds {
compatible = "gpio-leds";
red_led: led-0 {
gpios = <&pioD 31 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_RED>;
default-state = "on";
};
};
};
arch/arm/dts/cros-ec-sbs.dtsi
+52
View File
@@ -0,0 +1,52 @@
/*
* Smart battery dts fragment for devices that use cros-ec-sbs
*
* Copyright (c) 2015 Google, Inc
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
&i2c_tunnel {
battery: sbs-battery@b {
compatible = "sbs,sbs-battery";
reg = <0xb>;
sbs,i2c-retry-count = <2>;
sbs,poll-retry-count = <1>;
};
};
arch/arm/dts/en7523-evb-u-boot.dtsi
-4
View File
@@ -9,7 +9,3 @@
};
#include "en7523-u-boot.dtsi"
&gdm1 {
status = "okay";
};
arch/arm/dts/en7523-u-boot.dtsi
-18
View File
@@ -37,29 +37,11 @@
<&scu EN7523_HSI_MAC_RST>;
reset-names = "fe", "pdma", "qdma",
"hsi0-mac", "hsi1-mac", "hsi-mac";
gdm1: ethernet@1 {
compatible = "airoha,eth-mac";
reg = <1>;
phy-mode = "internal";
status = "disabled";
fixed-link {
speed = <10000>;
full-duplex;
pause;
};
};
};
switch: switch@1fb58000 {
compatible = "airoha,en7523-switch";
reg = <0x1fb58000 0x8000>;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
};
};
snfi: spi@1fa10000 {
arch/arm/dts/en7581-evb-u-boot.dtsi
-18
View File
@@ -9,21 +9,3 @@
};
#include "an7581-u-boot.dtsi"
&gdm1 {
status = "okay";
};
&gdm2 {
status = "okay";
managed = "in-band-status";
phy-mode = "10gbase-r";
};
&gdm4 {
status = "okay";
managed = "in-band-status";
phy-mode = "usxgmii";
};
arch/arm/dts/exynos7870-a2corelte-u-boot.dtsi
-26
View File
@@ -1,26 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2026 Kaustabh Chakraborty <kauschluss@disroot.org>
*/
/ {
/* These properties are required by S-BOOT. */
model_info-chip = <7870>;
model_info-hw_rev = <0>;
model_info-hw_rev_end = <255>;
chosen {
#address-cells = <2>;
#size-cells = <1>;
ranges;
framebuffer@67000000 {
compatible = "simple-framebuffer";
reg = <0x0 0x67000000 (540 * 960 * 4)>;
width = <540>;
height = <960>;
stride = <(540 * 4)>;
format = "a8r8g8b8";
};
};
};
arch/arm/dts/exynos7870-j6lte-u-boot.dtsi
-46
View File
@@ -1,46 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) Kaustabh Chakraborty <kauschluss@disroot.org>
*/
/ {
/* These properties are required by S-BOOT. */
model_info-chip = <7870>;
model_info-hw_rev = <0>;
model_info-hw_rev_end = <255>;
chosen {
#address-cells = <2>;
#size-cells = <1>;
ranges;
framebuffer@67000000 {
compatible = "simple-framebuffer";
reg = <0x0 0x67000000 (720 * 1480 * 4)>;
width = <720>;
height = <1480>;
stride = <(720 * 4)>;
format = "a8r8g8b8";
};
};
/*
* S-BOOT will populate the memory nodes stated below. Existing
* values redefine the safe memory requirements as stated in upstream
* device tree, in separate nodes for each bank.
*/
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0x3d800000>;
};
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x40000000>;
};
memory@100000000 {
device_type = "memory";
reg = <0x1 0x00000000 0x00000000>;
};
};
arch/arm/dts/exynos7870-on7xelte-u-boot.dtsi
-41
View File
@@ -1,41 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2026 Kaustabh Chakraborty <kauschluss@disroot.org>
*/
/ {
/* These properties are required by S-BOOT. */
model_info-chip = <7870>;
model_info-hw_rev = <0>;
model_info-hw_rev_end = <255>;
chosen {
#address-cells = <2>;
#size-cells = <1>;
ranges;
framebuffer@67000000 {
compatible = "simple-framebuffer";
reg = <0x0 0x67000000 (1080 * 1920 * 4)>;
width = <1080>;
height = <1920>;
stride = <(1080 * 4)>;
format = "a8r8g8b8";
};
};
/*
* S-BOOT will populate the memory nodes stated below. Existing
* values redefine the safe memory requirements as stated in upstream
* device tree, in separate nodes for each bank.
*/
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0x3e400000>;
};
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x80000000>;
};
};
arch/arm/dts/fsl-ls1012a-qds.dtsi
+3 -3
View File
@@ -17,7 +17,7 @@
bus-num = <0>;
status = "okay";
dflash0: n25q128a@0 {
dflash0: n25q128a {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
@@ -25,7 +25,7 @@
spi-max-frequency = <1000000>; /* input clock */
};
dflash1: sst25wf040b@1 {
dflash1: sst25wf040b {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
@@ -33,7 +33,7 @@
reg = <1>;
};
dflash2: en25s64@2 {
dflash2: en25s64 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
arch/arm/dts/fsl-ls1012a.dtsi
+2 -2
View File
@@ -48,7 +48,7 @@
clocks = <&sysclk>;
};
dspi0: spi@2100000 {
dspi0: dspi@2100000 {
compatible = "fsl,vf610-dspi";
#address-cells = <1>;
#size-cells = <0>;
@@ -178,7 +178,7 @@
clocks = <&clockgen 4 0>;
};
qspi: spi@1550000 {
qspi: quadspi@1550000 {
compatible = "fsl,ls1021a-qspi";
#address-cells = <1>;
#size-cells = <0>;
arch/arm/dts/fsl-ls1028a-qds.dtsi
+14 -14
View File
@@ -26,29 +26,29 @@
bus-num = <0>;
status = "okay";
dflash0: sst25wf040b@0 {
dflash0: sst25wf040b {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
compatible = "spi-flash";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <0>;
};
dflash1: en25s64@1 {
dflash1: en25s64 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
compatible = "spi-flash";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <1>;
};
dflash2: n25q128a@2 {
dflash2: n25q128a {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
compatible = "spi-flash";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
@@ -60,29 +60,29 @@
bus-num = <0>;
status = "okay";
dflash3: sst25wf040b@0 {
dflash3: sst25wf040b {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
compatible = "spi-flash";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <0>;
};
dflash4: en25s64@1 {
dflash4: en25s64 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
compatible = "spi-flash";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <1>;
};
dflash5: n25q128a@2 {
dflash5: n25q128a {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
compatible = "spi-flash";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
@@ -94,10 +94,10 @@
bus-num = <0>;
status = "okay";
dflash8: en25s64@0 {
dflash8: en25s64 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
compatible = "spi-flash";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
arch/arm/dts/fsl-ls1043a-qds.dtsi
+3 -3
View File
@@ -21,7 +21,7 @@
bus-num = <0>;
status = "okay";
dflash0: n25q128a@0 {
dflash0: n25q128a {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
@@ -31,7 +31,7 @@
reg = <0>;
};
dflash1: sst25wf040b@1 {
dflash1: sst25wf040b {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
@@ -41,7 +41,7 @@
reg = <1>;
};
dflash2: en25s64@2 {
dflash2: en25s64 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
arch/arm/dts/fsl-ls1043a-rdb.dts
+1 -1
View File
@@ -28,7 +28,7 @@
bus-num = <0>;
status = "okay";
dspiflash: n25q12a@0 {
dspiflash: n25q12a {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
arch/arm/dts/fsl-ls1043a.dtsi
+3 -3
View File
@@ -54,7 +54,7 @@
clocks = <&sysclk>;
};
dspi0: spi@2100000 {
dspi0: dspi@2100000 {
compatible = "fsl,vf610-dspi";
#address-cells = <1>;
#size-cells = <0>;
@@ -67,7 +67,7 @@
status = "disabled";
};
dspi1: spi@2110000 {
dspi1: dspi@2110000 {
compatible = "fsl,vf610-dspi";
#address-cells = <1>;
#size-cells = <0>;
@@ -306,7 +306,7 @@
clock-names = "ipg";
status = "disabled";
};
qspi: spi@1550000 {
qspi: quadspi@1550000 {
compatible = "fsl,ls1021a-qspi";
#address-cells = <1>;
#size-cells = <0>;
arch/arm/dts/fsl-ls1046a-qds.dtsi
+3 -3
View File
@@ -21,7 +21,7 @@
bus-num = <0>;
status = "okay";
dflash0: n25q128a@0 {
dflash0: n25q128a {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
@@ -31,7 +31,7 @@
reg = <0>;
};
dflash1: sst25wf040b@1 {
dflash1: sst25wf040b {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
@@ -41,7 +41,7 @@
reg = <1>;
};
dflash2: en25s64@2 {
dflash2: en25s64 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
arch/arm/dts/fsl-ls1046a.dtsi
+3 -3
View File
@@ -54,7 +54,7 @@
clocks = <&sysclk>;
};
dspi0: spi@2100000 {
dspi0: dspi@2100000 {
compatible = "fsl,vf610-dspi";
#address-cells = <1>;
#size-cells = <0>;
@@ -67,7 +67,7 @@
status = "disabled";
};
dspi1: spi@2110000 {
dspi1: dspi@2110000 {
compatible = "fsl,vf610-dspi";
#address-cells = <1>;
#size-cells = <0>;
@@ -311,7 +311,7 @@
status = "disabled";
};
qspi: spi@1550000 {
qspi: quadspi@1550000 {
compatible = "fsl,ls1021a-qspi";
#address-cells = <1>;
#size-cells = <0>;
arch/arm/dts/fsl-ls1088a-qds-21-x-u-boot.dtsi
-9
View File
@@ -1,9 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2024 NXP
*
*/
#include <config.h>
#include "fsl-ls1088a-qds-u-boot.dtsi"
arch/arm/dts/fsl-ls1088a-qds-29-x-u-boot.dtsi
-9
View File
@@ -1,9 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2024 NXP
*
*/
#include <config.h>
#include "fsl-ls1088a-qds-u-boot.dtsi"
arch/arm/dts/fsl-ls1088a-qds.dtsi
+3 -3
View File
@@ -144,7 +144,7 @@
bus-num = <0>;
status = "okay";
dflash0: n25q128a@0 {
dflash0: n25q128a {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
@@ -152,7 +152,7 @@
spi-max-frequency = <1000000>; /* input clock */
};
dflash1: sst25wf040b@1 {
dflash1: sst25wf040b {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
@@ -160,7 +160,7 @@
reg = <1>;
};
dflash2: en25s64@2 {
dflash2: en25s64 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
arch/arm/dts/fsl-ls1088a-ten64-u-boot.dtsi
+8
View File
@@ -18,3 +18,11 @@
ethernet9 = &dpmac1;
};
};
&i2c0 {
uc: board-controller@7e {
compatible = "traverse,ten64-controller";
reg = <0x7e>;
};
};
arch/arm/dts/fsl-ls1088a-ten64.dts
+388
View File
@@ -0,0 +1,388 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for Traverse Technologies Ten64
* (LS1088A) board
* Based on fsl-ls1088a-rdb.dts
* Copyright 2017-2020 NXP
* Copyright 2019-2023 Traverse Technologies
*
* Author: Mathew McBride <matt@traverse.com.au>
*/
/dts-v1/;
#include "fsl-ls1088a.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "Traverse Ten64";
compatible = "traverse,ten64", "fsl,ls1088a";
aliases {
serial0 = &duart0;
serial1 = &duart1;
};
chosen {
stdout-path = "serial0:115200n8";
};
buttons {
compatible = "gpio-keys";
/* Fired by system controller when
* external power off (e.g ATX Power Button)
* asserted
*/
button-powerdn {
label = "External Power Down";
gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
};
/* Rear Panel 'ADMIN' button (GPIO_H) */
button-admin {
label = "ADMIN button";
gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_WPS_BUTTON>;
};
};
leds {
compatible = "gpio-leds";
led-0 {
label = "ten64:green:sfp1:down";
gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>;
};
led-1 {
label = "ten64:green:sfp2:up";
gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>;
};
led-2 {
label = "ten64:admin";
gpios = <&sfpgpio 12 GPIO_ACTIVE_HIGH>;
};
};
sfp_xg0: dpmac2-sfp {
compatible = "sff,sfp";
i2c-bus = <&sfplower_i2c>;
tx-fault-gpios = <&sfpgpio 0 GPIO_ACTIVE_HIGH>;
tx-disable-gpios = <&sfpgpio 1 GPIO_ACTIVE_HIGH>;
mod-def0-gpios = <&sfpgpio 2 GPIO_ACTIVE_LOW>;
los-gpios = <&sfpgpio 3 GPIO_ACTIVE_HIGH>;
maximum-power-milliwatt = <2000>;
};
sfp_xg1: dpmac1-sfp {
compatible = "sff,sfp";
i2c-bus = <&sfpupper_i2c>;
tx-fault-gpios = <&sfpgpio 4 GPIO_ACTIVE_HIGH>;
tx-disable-gpios = <&sfpgpio 5 GPIO_ACTIVE_HIGH>;
mod-def0-gpios = <&sfpgpio 6 GPIO_ACTIVE_LOW>;
los-gpios = <&sfpgpio 7 GPIO_ACTIVE_HIGH>;
maximum-power-milliwatt = <2000>;
};
};
/* XG1 - Upper SFP */
&dpmac1 {
sfp = <&sfp_xg1>;
pcs-handle = <&pcs1>;
phy-connection-type = "10gbase-r";
managed = "in-band-status";
};
/* XG0 - Lower SFP */
&dpmac2 {
sfp = <&sfp_xg0>;
pcs-handle = <&pcs2>;
phy-connection-type = "10gbase-r";
managed = "in-band-status";
};
/* DPMAC3..6 is GE4 to GE8 */
&dpmac3 {
phy-handle = <&mdio1_phy5>;
phy-connection-type = "qsgmii";
managed = "in-band-status";
pcs-handle = <&pcs3_0>;
};
&dpmac4 {
phy-handle = <&mdio1_phy6>;
phy-connection-type = "qsgmii";
managed = "in-band-status";
pcs-handle = <&pcs3_1>;
};
&dpmac5 {
phy-handle = <&mdio1_phy7>;
phy-connection-type = "qsgmii";
managed = "in-band-status";
pcs-handle = <&pcs3_2>;
};
&dpmac6 {
phy-handle = <&mdio1_phy8>;
phy-connection-type = "qsgmii";
managed = "in-band-status";
pcs-handle = <&pcs3_3>;
};
/* DPMAC7..10 is GE0 to GE3 */
&dpmac7 {
phy-handle = <&mdio1_phy1>;
phy-connection-type = "qsgmii";
managed = "in-band-status";
pcs-handle = <&pcs7_0>;
};
&dpmac8 {
phy-handle = <&mdio1_phy2>;
phy-connection-type = "qsgmii";
managed = "in-band-status";
pcs-handle = <&pcs7_1>;
};
&dpmac9 {
phy-handle = <&mdio1_phy3>;
phy-connection-type = "qsgmii";
managed = "in-band-status";
pcs-handle = <&pcs7_2>;
};
&dpmac10 {
phy-handle = <&mdio1_phy4>;
phy-connection-type = "qsgmii";
managed = "in-band-status";
pcs-handle = <&pcs7_3>;
};
&duart0 {
status = "okay";
};
&duart1 {
status = "okay";
};
&emdio1 {
status = "okay";
mdio1_phy5: ethernet-phy@c {
reg = <0xc>;
};
mdio1_phy6: ethernet-phy@d {
reg = <0xd>;
};
mdio1_phy7: ethernet-phy@e {
reg = <0xe>;
};
mdio1_phy8: ethernet-phy@f {
reg = <0xf>;
};
mdio1_phy1: ethernet-phy@1c {
reg = <0x1c>;
};
mdio1_phy2: ethernet-phy@1d {
reg = <0x1d>;
};
mdio1_phy3: ethernet-phy@1e {
reg = <0x1e>;
};
mdio1_phy4: ethernet-phy@1f {
reg = <0x1f>;
};
};
&esdhc {
status = "okay";
};
&i2c0 {
status = "okay";
sfpgpio: gpio@76 {
compatible = "ti,tca9539";
reg = <0x76>;
#gpio-cells = <2>;
gpio-controller;
admin_led_lower {
gpio-hog;
gpios = <13 GPIO_ACTIVE_HIGH>;
output-low;
};
};
at97sc: tpm@29 {
compatible = "atmel,at97sc3204t";
reg = <0x29>;
};
};
&i2c2 {
status = "okay";
rx8035: rtc@32 {
compatible = "epson,rx8035";
reg = <0x32>;
};
};
&i2c3 {
status = "okay";
i2c-mux@70 {
compatible = "nxp,pca9540";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
sfpupper_i2c: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
sfplower_i2c: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
};
};
&pcs_mdio1 {
status = "okay";
};
&pcs_mdio2 {
status = "okay";
};
&pcs_mdio3 {
status = "okay";
};
&pcs_mdio7 {
status = "okay";
};
&qspi {
status = "okay";
en25s64: flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
spi-max-frequency = <20000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "bl2";
reg = <0 0x100000>;
};
partition@100000 {
label = "bl3";
reg = <0x100000 0x200000>;
};
partition@300000 {
label = "mcfirmware";
reg = <0x300000 0x200000>;
};
partition@500000 {
label = "ubootenv";
reg = <0x500000 0x80000>;
};
partition@580000 {
label = "dpl";
reg = <0x580000 0x40000>;
};
partition@5C0000 {
label = "dpc";
reg = <0x5C0000 0x40000>;
};
partition@600000 {
label = "devicetree";
reg = <0x600000 0x40000>;
};
};
};
nand: flash@1 {
compatible = "spi-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <1>;
spi-max-frequency = <20000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/* reserved for future boot direct from NAND flash
* (this would use the same layout as the 8MiB NOR flash)
*/
partition@0 {
label = "nand-boot-reserved";
reg = <0 0x800000>;
};
/* recovery / install environment */
partition@800000 {
label = "recovery";
reg = <0x800000 0x2000000>;
};
/* ubia (first OpenWrt) - a/b names to prevent confusion with ubi0/1/etc. */
partition@2800000 {
label = "ubia";
reg = <0x2800000 0x6C00000>;
};
/* ubib (second OpenWrt) */
partition@9400000 {
label = "ubib";
reg = <0x9400000 0x6C00000>;
};
};
};
};
&usb0 {
status = "okay";
};
&usb1 {
status = "okay";
};
arch/arm/dts/fsl-ls1088a-u-boot.dtsi
-5
View File
@@ -55,14 +55,9 @@
&usb0 {
compatible = "fsl,layerscape-dwc3", "snps,dwc3";
status = "okay";
};
&usb1 {
compatible = "fsl,layerscape-dwc3", "snps,dwc3";
status = "okay";
};
&esdhc {
status = "okay";
};
arch/arm/dts/fsl-ls1088a.dtsi
-10
View File
@@ -978,61 +978,51 @@
dpmac1: ethernet@1 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <1>;
status = "disabled";
};
dpmac2: ethernet@2 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <2>;
status = "disabled";
};
dpmac3: ethernet@3 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <3>;
status = "disabled";
};
dpmac4: ethernet@4 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <4>;
status = "disabled";
};
dpmac5: ethernet@5 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <5>;
status = "disabled";
};
dpmac6: ethernet@6 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <6>;
status = "disabled";
};
dpmac7: ethernet@7 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <7>;
status = "disabled";
};
dpmac8: ethernet@8 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <8>;
status = "disabled";
};
dpmac9: ethernet@9 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <9>;
status = "disabled";
};
dpmac10: ethernet@a {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0xa>;
status = "disabled";
};
};
};
arch/arm/dts/fsl-ls2080a-qds.dtsi
+3 -3
View File
@@ -31,7 +31,7 @@
bus-num = <0>;
status = "okay";
dflash0: n25q128a@0 {
dflash0: n25q128a {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
@@ -40,7 +40,7 @@
spi-cpha;
reg = <0>;
};
dflash1: sst25wf040b@1 {
dflash1: sst25wf040b {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
@@ -49,7 +49,7 @@
spi-cpha;
reg = <1>;
};
dflash2: en25s64@2 {
dflash2: en25s64 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
arch/arm/dts/fsl-ls2080a-rdb.dts
+1 -1
View File
@@ -22,7 +22,7 @@
bus-num = <0>;
status = "okay";
dflash0: n25q512a@0 {
dflash0: n25q512a {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
arch/arm/dts/fsl-ls2080a.dtsi
+2 -2
View File
@@ -118,7 +118,7 @@
interrupts = <0 35 0x4>; /* Level high type */
};
dspi: spi@2100000 {
dspi: dspi@2100000 {
compatible = "fsl,vf610-dspi";
#address-cells = <1>;
#size-cells = <0>;
@@ -127,7 +127,7 @@
spi-num-chipselects = <6>;
};
qspi: spi@1550000 {
qspi: quadspi@1550000 {
compatible = "fsl,ls2080a-qspi";
#address-cells = <1>;
#size-cells = <0>;
arch/arm/dts/fsl-ls2081a-rdb.dts
+1 -1
View File
@@ -25,7 +25,7 @@
bus-num = <0>;
status = "okay";
dflash0: n25q512a@0 {
dflash0: n25q512a {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
+1 -1
View File
@@ -113,7 +113,7 @@
bus-num = <0>;
status = "okay";
dflash0: n25q512a@0 {
dflash0: n25q512a {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
arch/arm/dts/fsl-lx2160a-qds.dtsi
+18 -18
View File
@@ -31,28 +31,28 @@
bus-num = <0>;
status = "okay";
dflash0: n25q128a@0 {
dflash0: n25q128a {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
compatible = "spi-flash";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <0>;
};
dflash1: sst25wf040b@1 {
dflash1: sst25wf040b {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
compatible = "spi-flash";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <1>;
};
dflash2: en25s64@2 {
dflash2: en25s64 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
compatible = "spi-flash";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
@@ -64,28 +64,28 @@
bus-num = <0>;
status = "okay";
dflash3: n25q128a@0 {
dflash3: n25q128a {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
compatible = "spi-flash";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <0>;
};
dflash4: sst25wf040b@1 {
dflash4: sst25wf040b {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
compatible = "spi-flash";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <1>;
};
dflash5: en25s64@2 {
dflash5: en25s64 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
compatible = "spi-flash";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
@@ -97,28 +97,28 @@
bus-num = <0>;
status = "okay";
dflash6: n25q128a@0 {
dflash6: n25q128a {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
compatible = "spi-flash";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <0>;
};
dflash7: sst25wf040b@1 {
dflash7: sst25wf040b {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
compatible = "spi-flash";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <1>;
};
dflash8: en25s64@2 {
dflash8: en25s64 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
compatible = "spi-flash";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
arch/arm/dts/fsl-lx2160a.dtsi
+4 -4
View File
@@ -134,7 +134,7 @@
<1 10 0x8>; /* Hypervisor PPI, active-low */
};
fspi: spi@20c0000 {
fspi: flexspi@20c0000 {
compatible = "nxp,lx2160a-fspi";
#address-cells = <1>;
#size-cells = <0>;
@@ -221,7 +221,7 @@
status = "disabled";
};
dspi0: spi@2100000 {
dspi0: dspi@2100000 {
compatible = "fsl,vf610-dspi";
#address-cells = <1>;
#size-cells = <0>;
@@ -230,7 +230,7 @@
spi-num-chipselects = <6>;
};
dspi1: spi@2110000 {
dspi1: dspi@2110000 {
compatible = "fsl,vf610-dspi";
#address-cells = <1>;
#size-cells = <0>;
@@ -239,7 +239,7 @@
spi-num-chipselects = <6>;
};
dspi2: spi@2120000 {
dspi2: dspi@2120000 {
compatible = "fsl,vf610-dspi";
#address-cells = <1>;
#size-cells = <0>;
arch/arm/dts/fsl-lx2162a-qds.dts
+18 -18
View File
@@ -41,28 +41,28 @@
bus-num = <0>;
status = "okay";
dflash0: n25q128a@0 {
dflash0: n25q128a {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
compatible = "spi-flash";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <0>;
};
dflash1: sst25wf040b@1 {
dflash1: sst25wf040b {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
compatible = "spi-flash";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <1>;
};
dflash2: en25s64@2 {
dflash2: en25s64 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
compatible = "spi-flash";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
@@ -74,28 +74,28 @@
bus-num = <0>;
status = "okay";
dflash3: n25q128a@0 {
dflash3: n25q128a {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
compatible = "spi-flash";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <0>;
};
dflash4: sst25wf040b@1 {
dflash4: sst25wf040b {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
compatible = "spi-flash";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <1>;
};
dflash5: en25s64@2 {
dflash5: en25s64 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
compatible = "spi-flash";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
@@ -107,28 +107,28 @@
bus-num = <0>;
status = "okay";
dflash6: n25q128a@0 {
dflash6: n25q128a {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
compatible = "spi-flash";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <0>;
};
dflash7: sst25wf040b@1 {
dflash7: sst25wf040b {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
compatible = "spi-flash";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <1>;
};
dflash8: en25s64@2 {
dflash8: en25s64 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
compatible = "spi-flash";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
arch/arm/dts/imx23-olinuxino-u-boot.dtsi
-15
View File
@@ -1,20 +1,5 @@
// SPDX-License-Identifier: GPL-2.0+
/ {
leds {
user_led: user {
default-state = "on";
};
};
options {
u-boot {
compatible = "u-boot,config";
boot-led = <&user_led>;
};
};
};
&ssp0 {
non-removable;
};
arch/arm/dts/imx7d-mba7-u-boot.dtsi
-10
View File
@@ -1,10 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Device Tree Source for TQ-Systems TQMa7D board on MBa7x carrier board.
*
* Copyright (C) 2024-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,
* D-82229 Seefeld, Germany
* Author: Steffen Doster
*/
#include "imx7s-mba7-u-boot.dtsi"
arch/arm/dts/imx7s-mba7-u-boot.dtsi
-48
View File
@@ -1,48 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Device Tree Source for TQ-Systems TQMa7S board on MBa7x carrier board.
*
* Copyright (C) 2025-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,
* D-82229 Seefeld, Germany
* Author: Steffen Doster
*/
#include "imx7s-tqma7-u-boot.dtsi"
/ {
config {
u-boot,mmc-env-offset = <0x100000>;
u-boot,mmc-env-offset-redundant = <0x110000>;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
};
};
&gpio4 {
/* Deassert BOOT_EN after boot to separate BOOT_CFG circuits from LCD signals */
boot-en-hog {
gpio-hog;
gpios = <3 GPIO_ACTIVE_LOW>;
output-low;
};
};
&wdog1 {
u-boot,noautostart;
timeout-sec = <60>;
};
&iomuxc {
bootph-pre-ram;
};
&pinctrl_uart6 {
bootph-pre-ram;
};
&uart6 {
bootph-pre-ram;
};
arch/arm/dts/imx7s-tqma7-u-boot.dtsi
-22
View File
@@ -1,22 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Device Tree Source for TQ-Systems TQMa7S module.
*
* Copyright (C) 2024-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,
* D-82229 Seefeld, Germany
* Author: Steffen Doster
*/
#include "imx7s-u-boot.dtsi"
&soc {
bootph-pre-ram;
};
&aips1 {
bootph-pre-ram;
};
&aips3 {
bootph-pre-ram;
};
arch/arm/dts/imx8-capricorn-cxg3.dts
-44
View File
@@ -102,26 +102,6 @@
pinctrl-0 = <&pinctrl_gpio_keys>;
muxcgrp: imx8qxp-som {
pinctrl_fec2: fec2grp {
fsl,pins = <
SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0
SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0
SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0
SC_P_ENET0_MDC_CONN_ENET1_MDC 0x00000060
SC_P_ENET0_MDIO_CONN_ENET1_MDIO 0x00000060
SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_IN 0x00000060
SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000060
SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000060
SC_P_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER 0x00000060
SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000060
SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000060
SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000060
SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000060
>;
};
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
SC_P_ESAI0_FST_LSIO_GPIO0_IO01 0x06000021
@@ -147,27 +127,3 @@
>;
};
};
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec2>;
phy-mode = "rmii";
phy-handle = <&ethphy1>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
};
arch/arm/dts/imx8-capricorn.dtsi
+59 -1
View File
@@ -63,6 +63,41 @@
SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041
SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
SC_P_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 0x06000021
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041
SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021
SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021
SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021
SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021
SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021
SC_P_ENET0_RGMII_TXD2_CONN_USDHC1_CD_B 0x06000021
//SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x06000021
SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x06000021
>;
};
pinctrl_fec2: fec2grp {
fsl,pins = <
SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0
SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0
SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0
SC_P_ENET0_MDC_CONN_ENET1_MDC 0x00000060
SC_P_ENET0_MDIO_CONN_ENET1_MDIO 0x00000060
SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_IN 0x00000060
SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000060
SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000060
SC_P_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER 0x00000060
SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000060
SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000060
SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000060
SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000060 /* ERST: Reset pin */
>;
};
};
@@ -91,7 +126,6 @@
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
max-frequency = <52000000>;
clock-frequency=<52000000>;
no-1-8-v;
bus-width = <8>;
@@ -126,3 +160,27 @@
&fec1 {
status ="disabled";
};
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec2>;
phy-mode = "rmii";
phy-handle = <&ethphy1>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
};
arch/arm/dts/imx8mm-phyboard-polis-rdk-u-boot.dtsi
-16
View File
@@ -12,22 +12,6 @@
wdt = <&wdog1>;
bootph-pre-ram;
};
bootstd {
bootph-verify;
compatible = "u-boot,boot-std";
filename-prefixes = "/", "/boot/";
bootdev-order = "mmc2", "mmc1", "ethernet";
rauc {
compatible = "u-boot,distro-rauc";
};
script {
compatible = "u-boot,script";
};
};
};
&pinctrl_i2c1 {
arch/arm/dts/imx8mm-phygate-tauri-l-u-boot.dtsi
-16
View File
@@ -11,22 +11,6 @@
wdt = <&wdog1>;
bootph-pre-ram;
};
bootstd {
bootph-verify;
compatible = "u-boot,boot-std";
filename-prefixes = "/", "/boot/";
bootdev-order = "mmc2", "mmc1", "ethernet";
rauc {
compatible = "u-boot,distro-rauc";
};
script {
compatible = "u-boot,script";
};
};
};
&pinctrl_uart3 {
arch/arm/dts/imx8mm-u-boot.dtsi
+8 -5
View File
@@ -50,6 +50,14 @@
section {
pad-byte = <0x00>;
#ifdef CONFIG_FSPI_CONF_HEADER
fspi_conf_block {
filename = CONFIG_FSPI_CONF_FILE;
type = "blob-ext";
size = <0x1000>;
};
#endif
#ifdef CONFIG_IMX_HAB
nxp-imx8mcst@0 {
filename = "u-boot-spl-mkimage.signed.bin";
@@ -60,12 +68,7 @@
binman_imx_spl: nxp-imx8mimage {
filename = "u-boot-spl-mkimage.bin";
#ifdef CONFIG_FSPI_CONF_HEADER
nxp,boot-from = "fspi";
nxp,fspi-header-filename = CONFIG_FSPI_CONF_FILE;
#else
nxp,boot-from = "sd";
#endif
nxp,rom-version = <1>;
nxp,loader-address = <CONFIG_SPL_TEXT_BASE>;
args; /* Needed by mkimage etype superclass */
arch/arm/dts/imx8mn-u-boot.dtsi
+8 -5
View File
@@ -104,6 +104,14 @@
section {
pad-byte = <0x00>;
#ifdef CONFIG_FSPI_CONF_HEADER
fspi_conf_block {
filename = CONFIG_FSPI_CONF_FILE;
type = "blob-ext";
offset = <0x400>;
};
#endif
#ifdef CONFIG_IMX_HAB
nxp-imx8mcst@0 {
filename = "u-boot-spl-mkimage.signed.bin";
@@ -114,12 +122,7 @@
binman_imx_spl: nxp-imx8mimage {
filename = "u-boot-spl-mkimage.bin";
#ifdef CONFIG_FSPI_CONF_HEADER
nxp,boot-from = "fspi";
nxp,fspi-header-filename = CONFIG_FSPI_CONF_FILE;
#else
nxp,boot-from = "sd";
#endif
nxp,rom-version = <2>;
nxp,loader-address = <CONFIG_SPL_TEXT_BASE>;
args; /* Needed by mkimage etype superclass */
arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
+62 -1
View File
@@ -3,7 +3,52 @@
* Copyright 2021 Collabora Ltd.
*/
#include "imx8mn-var-som-u-boot.dtsi"
#include "imx8mn-u-boot.dtsi"
&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
bootph-pre-ram;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} {
bootph-pre-ram;
};
&eeprom_som {
#address-cells = <1>;
#size-cells = <1>;
eth_mac_address: eth-mac-address@19 {
reg = <0x19 0x06>;
};
};
&fec1 {
nvmem-cells = <&eth_mac_address>;
nvmem-cell-names = "mac-address";
};
&gpio1 {
bootph-pre-ram;
};
&gpio2 {
bootph-pre-ram;
};
&gpio4 {
bootph-pre-ram;
};
&i2c1 {
bootph-all;
};
&pinctrl_i2c1 {
bootph-all;
};
&pinctrl_pmic {
bootph-pre-ram;
};
&pinctrl_reg_usdhc2_vmmc {
bootph-pre-ram;
@@ -17,6 +62,14 @@
bootph-pre-ram;
};
&pinctrl_usdhc3 {
bootph-pre-ram;
};
&pinctrl_wdog {
bootph-pre-ram;
};
&uart4 {
bootph-pre-ram;
};
@@ -24,3 +77,11 @@
&usdhc2 {
bootph-pre-ram;
};
&usdhc3 {
bootph-pre-ram;
};
&eeprom_som {
bootph-all;
};
arch/arm/dts/imx8mn-var-som-symphony.dts
+236
View File
@@ -0,0 +1,236 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2019-2020 Variscite Ltd.
* Copyright (C) 2020 Krzysztof Kozlowski <krzk@kernel.org>
*/
/dts-v1/;
#include "imx8mn-var-som.dtsi"
/ {
model = "Variscite VAR-SOM-MX8MN Symphony evaluation board";
compatible = "variscite,var-som-mx8mn-symphony", "variscite,var-som-mx8mn", "fsl,imx8mn";
reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
gpio-keys {
compatible = "gpio-keys";
key-back {
label = "Back";
gpios = <&pca9534 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_BACK>;
};
key-home {
label = "Home";
gpios = <&pca9534 2 GPIO_ACTIVE_LOW>;
linux,code = <KEY_HOME>;
};
key-menu {
label = "Menu";
gpios = <&pca9534 3 GPIO_ACTIVE_LOW>;
linux,code = <KEY_MENU>;
};
};
leds {
compatible = "gpio-leds";
led {
label = "Heartbeat";
gpios = <&pca9534 0 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
};
};
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
pca9534: gpio@20 {
compatible = "nxp,pca9534";
reg = <0x20>;
gpio-controller;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pca9534>;
interrupt-parent = <&gpio1>;
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
#gpio-cells = <2>;
wakeup-source;
/* USB 3.0 OTG (usbotg1) / SATA port switch, set to USB 3.0 */
usb3-sata-sel-hog {
gpio-hog;
gpios = <4 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "usb3_sata_sel";
};
som-vselect-hog {
gpio-hog;
gpios = <6 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "som_vselect";
};
enet-sel-hog {
gpio-hog;
gpios = <7 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "enet_sel";
};
};
extcon_usbotg1: typec@3d {
compatible = "nxp,ptn5150";
reg = <0x3d>;
interrupt-parent = <&gpio1>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ptn5150>;
status = "okay";
};
};
&i2c3 {
/* Capacitive touch controller */
ft5x06_ts: touchscreen@38 {
compatible = "edt,edt-ft5406";
reg = <0x38>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_captouch>;
interrupt-parent = <&gpio5>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
touchscreen-size-x = <800>;
touchscreen-size-y = <480>;
touchscreen-inverted-x;
touchscreen-inverted-y;
};
rtc@68 {
compatible = "dallas,ds1337";
reg = <0x68>;
};
};
/* Header */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
/* Header */
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&usbotg1 {
disable-over-current;
extcon = <&extcon_usbotg1>, <&extcon_usbotg1>;
};
&pinctrl_fec1 {
fsl,pins = <
MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
/* Remove the MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 as not used */
>;
};
&pinctrl_fec1_sleep {
fsl,pins = <
MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16 0x120
MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17 0x120
MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x120
MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19 0x120
MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20 0x120
MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21 0x120
MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x120
MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x120
MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27 0x120
MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26 0x120
MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23 0x120
MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25 0x120
MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x120
MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x120
/* Remove the MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 as not used */
>;
};
&iomuxc {
pinctrl_captouch: captouchgrp {
fsl,pins = <
MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x16
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
>;
};
pinctrl_pca9534: pca9534grp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x16
>;
};
pinctrl_ptn5150: ptn5150grp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x16
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x41
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
>;
};
};
arch/arm/dts/imx8mn-var-som-u-boot.dtsi
-70
View File
@@ -1,70 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2025 Dimonoff
*/
#include "imx8mn-u-boot.dtsi"
/ {
aliases {
eeprom-som = &eeprom_som;
};
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
bootph-pre-ram;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} {
bootph-pre-ram;
};
&eeprom_som {
bootph-all;
#address-cells = <1>;
#size-cells = <1>;
eth_mac_address: eth-mac-address@19 {
reg = <0x19 0x06>;
};
};
&fec1 {
nvmem-cells = <&eth_mac_address>;
nvmem-cell-names = "mac-address";
};
&gpio1 {
bootph-pre-ram;
};
&gpio2 {
bootph-pre-ram;
};
&gpio4 {
bootph-pre-ram;
};
&i2c1 {
bootph-all;
};
&usdhc3 {
bootph-pre-ram;
};
&pinctrl_i2c1 {
bootph-all;
};
&pinctrl_wdog {
bootph-pre-ram;
};
&pinctrl_pmic {
bootph-pre-ram;
};
&pinctrl_usdhc3 {
bootph-pre-ram;
};
arch/arm/dts/imx8mn-var-som.dtsi
+564
View File
@@ -0,0 +1,564 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2019 NXP
* Copyright 2019-2020 Variscite Ltd.
* Copyright (C) 2020 Krzysztof Kozlowski <krzk@kernel.org>
*/
#include "imx8mn.dtsi"
/ {
model = "Variscite VAR-SOM-MX8MN module";
compatible = "variscite,var-som-mx8mn", "fsl,imx8mn";
aliases {
eeprom-som = &eeprom_som;
};
chosen {
stdout-path = &uart4;
};
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0 0x40000000>;
};
reg_eth_phy: regulator-eth-phy {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_eth_phy>;
regulator-name = "eth_phy_pwr";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&A53_0 {
cpu-supply = <&buck2_reg>;
};
&A53_1 {
cpu-supply = <&buck2_reg>;
};
&A53_2 {
cpu-supply = <&buck2_reg>;
};
&A53_3 {
cpu-supply = <&buck2_reg>;
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>,
<&gpio1 0 GPIO_ACTIVE_LOW>;
/delete-property/ dmas;
/delete-property/ dma-names;
status = "okay";
/* Resistive touch controller */
touchscreen@0 {
reg = <0>;
compatible = "ti,ads7846";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_restouch>;
interrupt-parent = <&gpio1>;
interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
spi-max-frequency = <1500000>;
pendown-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
ti,x-min = /bits/ 16 <125>;
touchscreen-size-x = <4008>;
ti,y-min = /bits/ 16 <282>;
touchscreen-size-y = <3864>;
ti,x-plate-ohms = /bits/ 16 <180>;
touchscreen-max-pressure = <255>;
touchscreen-average-samples = <10>;
ti,debounce-tol = /bits/ 16 <3>;
ti,debounce-rep = /bits/ 16 <1>;
ti,settle-delay-usec = /bits/ 16 <150>;
ti,keep-vref-on;
wakeup-source;
};
};
&fec1 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_fec1>;
pinctrl-1 = <&pinctrl_fec1_sleep>;
phy-mode = "rgmii";
phy-handle = <&ethphy>;
phy-supply = <&reg_eth_phy>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy: ethernet-phy@4 { /* AR8033 or ADIN1300 */
compatible = "ethernet-phy-ieee802.3-c22";
reg = <4>;
reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
/*
* Deassert delay:
* ADIN1300 requires 5ms.
* AR8033 requires 1ms.
*/
reset-deassert-us = <20000>;
};
};
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic@4b {
compatible = "rohm,bd71847";
reg = <0x4b>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio2>;
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
rohm,reset-snvs-powered;
regulators {
buck1_reg: BUCK1 {
regulator-name = "buck1";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <1250>;
};
buck2_reg: BUCK2 {
regulator-name = "buck2";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <1250>;
rohm,dvs-run-voltage = <1000000>;
rohm,dvs-idle-voltage = <900000>;
};
buck3_reg: BUCK3 {
regulator-name = "buck3";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1350000>;
regulator-boot-on;
regulator-always-on;
};
buck4_reg: BUCK4 {
regulator-name = "buck4";
regulator-min-microvolt = <2600000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
buck5_reg: BUCK5 {
regulator-name = "buck5";
regulator-min-microvolt = <1605000>;
regulator-max-microvolt = <1995000>;
regulator-boot-on;
regulator-always-on;
};
buck6_reg: BUCK6 {
regulator-name = "buck6";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
regulator-boot-on;
regulator-always-on;
};
ldo1_reg: LDO1 {
regulator-name = "ldo1";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <1900000>;
regulator-boot-on;
regulator-always-on;
};
ldo2_reg: LDO2 {
regulator-name = "ldo2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
regulator-always-on;
};
ldo3_reg: LDO3 {
regulator-name = "ldo3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo4_reg: LDO4 {
regulator-name = "ldo4";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo5_reg: LDO5 {
regulator-compatible = "ldo5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo6_reg: LDO6 {
regulator-name = "ldo6";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
};
};
eeprom_som: eeprom@52 {
compatible = "atmel,24c04";
reg = <0x52>;
pagesize = <16>;
};
};
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
/* TODO: configure audio, as of now just put a placeholder */
wm8904: codec@1a {
compatible = "wlf,wm8904";
reg = <0x1a>;
status = "disabled";
};
};
&snvs_pwrkey {
status = "okay";
};
/* Bluetooth */
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
assigned-clocks = <&clk IMX8MN_CLK_UART2>;
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
uart-has-rtscts;
status = "okay";
};
/* Console */
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
&usbotg1 {
dr_mode = "otg";
usb-role-switch;
status = "okay";
};
/* WIFI */
&usdhc1 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <4>;
non-removable;
keep-power-in-suspend;
status = "okay";
brcmf: bcrmf@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};
/* SD */
&usdhc2 {
assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
bus-width = <4>;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
/* eMMC */
&usdhc3 {
assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x13
MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x13
MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x13
MX8MN_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x13
MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x13
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
>;
};
pinctrl_fec1_sleep: fec1sleepgrp {
fsl,pins = <
MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16 0x120
MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17 0x120
MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x120
MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19 0x120
MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20 0x120
MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21 0x120
MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x120
MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x120
MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27 0x120
MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26 0x120
MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23 0x120
MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25 0x120
MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x120
MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x120
MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x120
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
>;
};
pinctrl_pmic: pmicirqgrp {
fsl,pins = <
MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x141
>;
};
pinctrl_reg_eth_phy: regethphygrp {
fsl,pins = <
MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x41
>;
};
pinctrl_restouch: restouchgrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MN_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140
MX8MN_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140
MX8MN_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140
MX8MN_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
>;
};
};
arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi
+1 -17
View File
@@ -22,18 +22,6 @@
bootph-pre-ram;
};
&pca9450 {
bootph-all;
};
&pinctrl_i2c1 {
bootph-all;
};
&pinctrl_pmic {
bootph-all;
};
&pinctrl_uart2 {
bootph-pre-ram;
};
@@ -75,7 +63,7 @@
};
&i2c1 {
bootph-all;
bootph-pre-ram;
};
&i2c2 {
@@ -130,7 +118,3 @@
phy-reset-duration = <15>;
phy-reset-post-delay = <100>;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
bootph-all;
};
arch/arm/dts/imx8mp-kontron-bl-osm-s-u-boot.dtsi
-124
View File
@@ -1,124 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2022 Kontron Electronics GmbH
*/
#include "imx8mp-u-boot.dtsi"
/ {
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
bootph-pre-ram;
};
};
&gpio1 {
bootph-pre-ram;
};
&gpio2 {
bootph-pre-ram;
};
&gpio3 {
bootph-pre-ram;
};
&gpio4 {
bootph-pre-ram;
};
&gpio5 {
bootph-pre-ram;
};
/* Enable I2C1 to probe for a touch controller on LVDS connector */
&i2c1 {
status = "okay";
};
&i2c5 {
bootph-pre-ram;
};
&pinctrl_i2c5 {
bootph-pre-ram;
};
&pinctrl_i2c5_gpio {
bootph-pre-ram;
};
&pinctrl_pmic {
bootph-pre-ram;
};
&pinctrl_uart3 {
bootph-pre-ram;
};
&pinctrl_wdog {
bootph-pre-ram;
};
&pca9450 {
bootph-pre-ram;
};
&reg_vdd_soc {
bootph-pre-ram;
};
&reg_vdd_arm {
bootph-pre-ram;
};
&reg_vdd_3v3 {
bootph-pre-ram;
};
&reg_vdd_1v8 {
bootph-pre-ram;
};
&reg_nvcc_dram {
bootph-pre-ram;
};
&reg_nvcc_snvs {
bootph-pre-ram;
};
&reg_vdda {
bootph-pre-ram;
};
&reg_nvcc_sd {
bootph-pre-ram;
};
&uart3 {
bootph-pre-ram;
};
&usb_dwc3_0 {
/*
* OTG role switching is currently not supported in U-Boot, use peripheral
* as default.
*/
dr_mode = "peripheral";
};
&usb3_phy0 {
/*
* Workaround to fix USB in U-Boot until the following commit from
* linux-next-20251111 has landed and been synced to dts/upstream:
* 6504297872c7 ("arm64: dts: imx8mp-kontron: Fix USB OTG role switching")
*/
/delete-property/ vbus-supply;
};
&wdog1 {
bootph-pre-ram;
};
arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi
+2 -20
View File
@@ -33,18 +33,6 @@
};
};
&pinctrl_i2c1 {
bootph-all;
};
&pinctrl_pmic {
bootph-all;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
bootph-all;
};
&reg_usdhc2_vmmc {
bootph-pre-ram;
};
@@ -90,11 +78,11 @@
};
&i2c1 {
bootph-all;
bootph-pre-ram;
};
&pmic {
bootph-all;
bootph-pre-ram;
};
/* USB1 Type-C */
@@ -132,12 +120,6 @@
&usdhc2 {
bootph-pre-ram;
/*
* LDO5 output depends on SD2_VSEL, but no way to read back SD2_VSEL
* when using SDHC controller VSELECT to control SD2_VSEL. So drop
* vqmmc-supply to avoid fsl_esdhc_imx read back wrong voltage.
*/
/delete-property/ vqmmc-supply;
};
&usdhc3 {
arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi
+2 -40
View File
@@ -12,38 +12,6 @@
wdt = <&wdog1>;
bootph-pre-ram;
};
bootstd {
bootph-verify;
compatible = "u-boot,boot-std";
filename-prefixes = "/", "/boot/";
bootdev-order = "mmc2", "mmc1", "ethernet";
efi {
compatible = "u-boot,distro-efi";
};
rauc {
compatible = "u-boot,distro-rauc";
};
script {
compatible = "u-boot,script";
};
};
};
&pinctrl_i2c1 {
bootph-all;
};
&pinctrl_pmic {
bootph-all;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
bootph-all;
};
&reg_usdhc2_vmmc {
@@ -95,11 +63,11 @@
};
&i2c1 {
bootph-all;
bootph-pre-ram;
};
&pmic {
bootph-all;
bootph-pre-ram;
};
&usb_dwc3_0 {
@@ -108,12 +76,6 @@
&usdhc2 {
bootph-pre-ram;
/*
* LDO5 output depends on SD2_VSEL, but no way to read back SD2_VSEL
* when using SDHC controller VSELECT to control SD2_VSEL. So drop
* vqmmc-supply to avoid fsl_esdhc_imx read back wrong voltage.
*/
/delete-property/ vqmmc-supply;
};
&usdhc3 {
arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi
+3 -17
View File
@@ -70,7 +70,7 @@
};
&i2c1 {
bootph-all;
bootph-pre-ram;
eeprom_module: eeprom@50 {
compatible = "i2c-eeprom";
@@ -104,7 +104,7 @@
};
&pca9450 {
bootph-all;
bootph-pre-ram;
};
&pinctrl_ctrl_sleep_moci {
@@ -112,11 +112,7 @@
};
&pinctrl_i2c1 {
bootph-all;
};
&pinctrl_pmic {
bootph-all;
bootph-pre-ram;
};
&pinctrl_usdhc2_pwr_en {
@@ -163,12 +159,6 @@
sd-uhs-ddr50;
sd-uhs-sdr104;
bootph-pre-ram;
/*
* LDO5 output depends on SD2_VSEL, but no way to read back SD2_VSEL
* when using SDHC controller VSELECT to control SD2_VSEL. So drop
* vqmmc-supply to avoid fsl_esdhc_imx read back wrong voltage.
*/
/delete-property/ vqmmc-supply;
};
&usdhc3 {
@@ -183,7 +173,3 @@
&wdog1 {
bootph-pre-ram;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
bootph-all;
};
arch/arm/dts/imx8mq-evk-u-boot.dtsi
+1 -87
View File
@@ -2,105 +2,19 @@
#include "imx8mq-u-boot.dtsi"
&aips1 {
bootph-all;
};
&gpio2 {
bootph-pre-ram;
};
&pinctrl_i2c1 {
bootph-all;
};
&i2c1 {
bootph-all;
};
&soc {
bootph-all;
bootph-pre-ram;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@8} {
bootph-all;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@8/regulators} {
bootph-all;
};
&pinctrl_uart1 {
bootph-pre-ram;
};
&uart1 {
bootph-pre-ram;
};
&usdhc1 {
bootph-pre-ram;
mmc-hs400-1_8v;
/delete-property/ vqmmc-supply;
};
&pinctrl_usdhc1 {
bootph-pre-ram;
};
&pinctrl_usdhc1_100mhz {
bootph-pre-ram;
};
&pinctrl_usdhc1_200mhz {
bootph-pre-ram;
};
&usdhc2 {
bootph-pre-ram;
sd-uhs-sdr104;
sd-uhs-ddr50;
};
&pinctrl_usdhc2 {
&uart1 {
bootph-pre-ram;
};
&pinctrl_usdhc2_100mhz {
bootph-pre-ram;
};
&pinctrl_usdhc2_200mhz {
bootph-pre-ram;
};
&pinctrl_usdhc2_gpio {
bootph-pre-ram;
};
&pinctrl_reg_usdhc2 {
bootph-pre-ram;
};
&reg_usdhc2_vmmc {
bootph-pre-ram;
};
#ifdef CONFIG_FSL_CAAM
&crypto {
bootph-pre-ram;
};
&sec_jr0 {
bootph-pre-ram;
};
&sec_jr1 {
bootph-pre-ram;
};
&sec_jr2 {
bootph-pre-ram;
};
#endif
arch/arm/dts/imx8mq-kontron-pitx-imx8m-u-boot.dtsi
-64
View File
@@ -2,90 +2,26 @@
#include "imx8mq-u-boot.dtsi"
&aips1 {
bootph-all;
};
&gpio2 {
bootph-pre-ram;
};
&pinctrl_i2c1 {
bootph-all;
};
&i2c1 {
bootph-all;
};
&soc {
bootph-all;
bootph-pre-ram;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@8} {
bootph-all;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@8/regulators} {
bootph-all;
};
&pinctrl_uart1 {
bootph-pre-ram;
};
&uart1 {
bootph-pre-ram;
};
&usdhc1 {
bootph-pre-ram;
mmc-hs400-1_8v;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
};
&pinctrl_usdhc1 {
bootph-pre-ram;
};
&usdhc2 {
bootph-pre-ram;
sd-uhs-sdr104;
sd-uhs-ddr50;
};
&pinctrl_usdhc2 {
bootph-pre-ram;
};
&pinctrl_usdhc2_gpio {
bootph-pre-ram;
};
&pinctrl_reg_usdhc2 {
bootph-pre-ram;
};
&reg_usdhc2_vmmc {
bootph-pre-ram;
};
&uart1 {
bootph-pre-ram;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
};
&uart2 {
bootph-pre-ram;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
};
&uart3 {
bootph-pre-ram;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
};
arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi
+1 -1
View File
@@ -10,7 +10,7 @@
bootph-pre-ram;
};
&binman {
&binman_imx_spl {
section {
signed-hdmi-imx8m {
filename = "signed_dp_imx8m.bin";
arch/arm/dts/imx8mq-phanbell-u-boot.dtsi
-41
View File
@@ -2,12 +2,7 @@
#include "imx8mq-u-boot.dtsi"
&gpio2 {
bootph-pre-ram;
};
&reg_usdhc2_vmmc {
bootph-pre-ram;
u-boot,off-on-delay-us = <20000>;
};
@@ -18,39 +13,3 @@
&pinctrl_uart1 {
bootph-pre-ram;
};
&usdhc1 {
bootph-pre-ram;
};
&pinctrl_usdhc1 {
bootph-pre-ram;
};
&pinctrl_usdhc1_100mhz {
bootph-pre-ram;
};
&pinctrl_usdhc1_200mhz {
bootph-pre-ram;
};
&usdhc2 {
bootph-pre-ram;
};
&pinctrl_usdhc2 {
bootph-pre-ram;
};
&pinctrl_usdhc2_100mhz {
bootph-pre-ram;
};
&pinctrl_usdhc2_200mhz {
bootph-pre-ram;
};
&pinctrl_usdhc2_gpio {
bootph-pre-ram;
};
arch/arm/dts/imx8mq-u-boot.dtsi
+117 -141
View File
@@ -41,33 +41,6 @@
filename = "flash.bin";
section {
pad-byte = <0x00>;
/*
* signed_hdmi_imx8m.bin contains a 1KB zero-filled padding at
* its beginning. This padding has no functional purpose, but
* the firmware is provided and signed by NXP, so the head
* must be preserved and should not be removed.
*
* When the signed HDMI firmware is placed at the beginning of
* flash.bin, the IVT header of u-boot-spl must still reside at
* a 4KB-aligned address. Since flash.bin starts with the HDMI
* firmware (including its 1KB padding), there is already a 1KB
* empty region at the head of flash.bin.
*
* The required 4KB alignment is therefore calculated relative
* to the location after this 1KB padding. To achieve this, we
* explicitly set align and align-size to 0x1000, and add an
* additional 0x400 (1KB) fill to account for the padding.
*/
signed-hdmi-imx8m {
filename = "signed_hdmi_imx8m.bin";
type = "blob-ext";
align = <0x1000>;
align-size = <0x1000>;
};
fill {
size = <0x400>;
};
#ifdef CONFIG_IMX_HAB
nxp-imx8mcst@0 {
@@ -78,142 +51,145 @@
#endif
binman_imx_spl: nxp-imx8mimage {
filename = "u-boot-spl-mkimage.bin";
nxp,boot-from = "sd";
nxp,rom-version = <1>;
nxp,loader-address = <CONFIG_SPL_TEXT_BASE>;
args; /* Needed by mkimage etype superclass */
filename = "u-boot-spl-mkimage.bin";
nxp,boot-from = "sd";
nxp,rom-version = <1>;
nxp,loader-address = <CONFIG_SPL_TEXT_BASE>;
args; /* Needed by mkimage etype superclass */
section {
align = <4>;
align-size = <4>;
filename = "u-boot-spl-ddr.bin";
pad-byte = <0xff>;
section {
align = <4>;
align-size = <4>;
filename = "u-boot-spl-ddr.bin";
pad-byte = <0xff>;
u-boot-spl {
align-end = <4>;
filename = "u-boot-spl.bin";
};
u-boot-spl {
align-end = <4>;
filename = "u-boot-spl.bin";
};
ddr-1d-imem-fw {
filename = "lpddr4_pmu_train_1d_imem.bin";
align-end = <4>;
type = "blob-ext";
};
ddr-1d-imem-fw {
filename = "lpddr4_pmu_train_1d_imem.bin";
align-end = <4>;
type = "blob-ext";
};
ddr-1d-dmem-fw {
filename = "lpddr4_pmu_train_1d_dmem.bin";
align-end = <4>;
type = "blob-ext";
};
ddr-1d-dmem-fw {
filename = "lpddr4_pmu_train_1d_dmem.bin";
align-end = <4>;
type = "blob-ext";
};
ddr-2d-imem-fw {
filename = "lpddr4_pmu_train_2d_imem.bin";
align-end = <4>;
type = "blob-ext";
};
ddr-2d-imem-fw {
filename = "lpddr4_pmu_train_2d_imem.bin";
align-end = <4>;
type = "blob-ext";
};
ddr-2d-dmem-fw {
filename = "lpddr4_pmu_train_2d_dmem.bin";
align-end = <4>;
type = "blob-ext";
ddr-2d-dmem-fw {
filename = "lpddr4_pmu_train_2d_dmem.bin";
align-end = <4>;
type = "blob-ext";
};
signed-hdmi-imx8m {
filename = "signed_hdmi_imx8m.bin";
type = "blob-ext";
};
};
};
};
#ifdef CONFIG_IMX_HAB
};
#endif
};
#ifdef CONFIG_IMX_HAB
nxp-imx8mcst@1 {
filename = "u-boot-fit.signed.bin";
nxp,loader-address = <CONFIG_SPL_LOAD_FIT_ADDRESS>;
offset = <0x58400>;
args; /* Needed by mkimage etype superclass */
#endif
binman_imx_fit: fit {
description = "Configuration to load ATF before U-Boot";
filename = "u-boot.itb";
#ifndef CONFIG_IMX_HAB
fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
#endif
#address-cells = <1>;
nxp-imx8mcst@1 {
filename = "u-boot-fit.signed.bin";
nxp,loader-address = <CONFIG_SPL_LOAD_FIT_ADDRESS>;
offset = <0x58000>;
images {
uboot {
arch = "arm64";
compression = "none";
description = "U-Boot (64-bit)";
load = <CONFIG_TEXT_BASE>;
type = "standalone";
uboot-blob {
filename = "u-boot-nodtb.bin";
type = "blob-ext";
};
};
#ifndef CONFIG_ARMV8_PSCI
atf {
arch = "arm64";
compression = "none";
description = "ARM Trusted Firmware";
entry = <0x910000>;
load = <0x910000>;
type = "firmware";
atf-blob {
filename = "bl31.bin";
type = "blob-ext";
};
};
args; /* Needed by mkimage etype superclass */
#endif
tee: tee {
description = "OP-TEE";
type = "tee";
arch = "arm64";
compression = "none";
os = "tee";
load = <CONFIG_IMX8M_OPTEE_LOAD_ADDR>;
entry = <CONFIG_IMX8M_OPTEE_LOAD_ADDR>;
binman_imx_fit: fit {
description = "Configuration to load ATF before U-Boot";
filename = "u-boot.itb";
#ifndef CONFIG_IMX_HAB
fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
#endif
#address-cells = <1>;
tee-os {
filename = "tee.bin";
optional;
offset = <0x57c00>;
images {
uboot {
arch = "arm64";
compression = "none";
description = "U-Boot (64-bit)";
load = <CONFIG_TEXT_BASE>;
type = "standalone";
uboot-blob {
filename = "u-boot-nodtb.bin";
type = "blob-ext";
};
};
#ifndef CONFIG_ARMV8_PSCI
atf {
arch = "arm64";
compression = "none";
description = "ARM Trusted Firmware";
entry = <0x910000>;
load = <0x910000>;
type = "firmware";
atf-blob {
filename = "bl31.bin";
type = "blob-ext";
};
};
#endif
tee: tee {
description = "OP-TEE";
type = "tee";
arch = "arm64";
compression = "none";
os = "tee";
load = <CONFIG_IMX8M_OPTEE_LOAD_ADDR>;
entry = <CONFIG_IMX8M_OPTEE_LOAD_ADDR>;
tee-os {
filename = "tee.bin";
optional;
};
};
fdt {
compression = "none";
description = "NAME";
type = "flat_dt";
uboot-fdt-blob {
filename = "u-boot.dtb";
type = "blob-ext";
};
};
};
fdt {
compression = "none";
description = "NAME";
type = "flat_dt";
configurations {
default = "conf";
uboot-fdt-blob {
filename = "u-boot.dtb";
type = "blob-ext";
conf {
description = "NAME";
fdt = "fdt";
firmware = "uboot";
#ifndef CONFIG_ARMV8_PSCI
loadables = "atf", "tee";
#endif
};
};
};
configurations {
default = "conf";
conf {
description = "NAME";
fdt = "fdt";
firmware = "uboot";
#ifndef CONFIG_ARMV8_PSCI
loadables = "atf", "tee";
#endif
};
};
};
#ifdef CONFIG_IMX_HAB
};
};
#endif
};
};
arch/arm/dts/imx8ulp-evk-u-boot.dtsi
-8
View File
@@ -22,14 +22,6 @@
bootph-all;
};
&mu {
status = "disabled";
};
&wdog3 {
status = "disabled";
};
&per_bridge4 {
bootph-pre-ram;
};
arch/arm/dts/imx8ulp-evk.dts
+125
View File
@@ -0,0 +1,125 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2021 NXP
*/
/dts-v1/;
#include "imx8ulp.dtsi"
/ {
model = "NXP i.MX8ULP EVK";
compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp";
chosen {
stdout-path = &lpuart5;
};
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0 0x80000000>;
};
clock_ext_rmii: clock-ext-rmii {
compatible = "fixed-clock";
clock-frequency = <50000000>;
clock-output-names = "ext_rmii_clk";
#clock-cells = <0>;
};
clock_ext_ts: clock-ext-ts {
compatible = "fixed-clock";
/* External ts clock is 50MHZ from PHY on EVK board. */
clock-frequency = <50000000>;
clock-output-names = "ext_ts_clk";
#clock-cells = <0>;
};
};
&lpuart5 {
/* console */
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_lpuart5>;
pinctrl-1 = <&pinctrl_lpuart5>;
status = "okay";
};
&usdhc0 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_usdhc0>;
pinctrl-1 = <&pinctrl_usdhc0>;
non-removable;
bus-width = <8>;
status = "okay";
};
&fec {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_enet>;
pinctrl-1 = <&pinctrl_enet>;
clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
<&pcc4 IMX8ULP_CLK_ENET>,
<&cgc1 IMX8ULP_CLK_ENET_TS_SEL>,
<&clock_ext_rmii>;
clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
assigned-clocks = <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>;
assigned-clock-parents = <&clock_ext_ts>;
phy-mode = "rmii";
phy-handle = <&ethphy>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy: ethernet-phy@1 {
reg = <1>;
micrel,led-mode = <1>;
};
};
};
&iomuxc1 {
pinctrl_enet: enetgrp {
fsl,pins = <
MX8ULP_PAD_PTE15__ENET0_MDC 0x43
MX8ULP_PAD_PTE14__ENET0_MDIO 0x43
MX8ULP_PAD_PTE17__ENET0_RXER 0x43
MX8ULP_PAD_PTE18__ENET0_CRS_DV 0x43
MX8ULP_PAD_PTF1__ENET0_RXD0 0x43
MX8ULP_PAD_PTE20__ENET0_RXD1 0x43
MX8ULP_PAD_PTE16__ENET0_TXEN 0x43
MX8ULP_PAD_PTE23__ENET0_TXD0 0x43
MX8ULP_PAD_PTE22__ENET0_TXD1 0x43
MX8ULP_PAD_PTE19__ENET0_REFCLK 0x43
MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43
>;
};
pinctrl_lpuart5: lpuart5grp {
fsl,pins = <
MX8ULP_PAD_PTF14__LPUART5_TX 0x3
MX8ULP_PAD_PTF15__LPUART5_RX 0x3
>;
};
pinctrl_usdhc0: usdhc0grp {
fsl,pins = <
MX8ULP_PAD_PTD1__SDHC0_CMD 0x43
MX8ULP_PAD_PTD2__SDHC0_CLK 0x10042
MX8ULP_PAD_PTD10__SDHC0_D0 0x43
MX8ULP_PAD_PTD9__SDHC0_D1 0x43
MX8ULP_PAD_PTD8__SDHC0_D2 0x43
MX8ULP_PAD_PTD7__SDHC0_D3 0x43
MX8ULP_PAD_PTD6__SDHC0_D4 0x43
MX8ULP_PAD_PTD5__SDHC0_D5 0x43
MX8ULP_PAD_PTD4__SDHC0_D6 0x43
MX8ULP_PAD_PTD3__SDHC0_D7 0x43
MX8ULP_PAD_PTD11__SDHC0_DQS 0x10042
>;
};
};
&wdog3 {
status = "disabled";
};
arch/arm/dts/imx8ulp.dtsi
+476
View File
@@ -0,0 +1,476 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2021 NXP
*/
#include <dt-bindings/clock/imx8ulp-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/imx8ulp-power.h>
#include "imx8ulp-pinfunc.h"
/ {
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
ethernet0 = &fec;
gpio0 = &gpiod;
gpio1 = &gpioe;
gpio2 = &gpiof;
mmc0 = &usdhc0;
mmc1 = &usdhc1;
mmc2 = &usdhc2;
serial0 = &lpuart4;
serial1 = &lpuart5;
serial2 = &lpuart6;
serial3 = &lpuart7;
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
A35_0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a35";
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
};
A35_1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a35";
reg = <0x0 0x1>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
};
A35_L2: l2-cache0 {
compatible = "cache";
};
};
gic: interrupt-controller@2d400000 {
compatible = "arm,gic-v3";
reg = <0x0 0x2d400000 0 0x10000>, /* GIC Dist */
<0x0 0x2d440000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
pmu {
compatible = "arm,cortex-a35-pmu";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 7
(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
interrupt-affinity = <&A35_0>, <&A35_1>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
};
frosc: clock-frosc {
compatible = "fixed-clock";
clock-frequency = <192000000>;
clock-output-names = "frosc";
#clock-cells = <0>;
};
lposc: clock-lposc {
compatible = "fixed-clock";
clock-frequency = <1000000>;
clock-output-names = "lposc";
#clock-cells = <0>;
};
rosc: clock-rosc {
compatible = "fixed-clock";
clock-frequency = <32768>;
clock-output-names = "rosc";
#clock-cells = <0>;
};
sosc: clock-sosc {
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "sosc";
#clock-cells = <0>;
};
sram@2201f000 {
compatible = "mmio-sram";
reg = <0x0 0x2201f000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x0 0x2201f000 0x1000>;
scmi_buf: scmi-sram-section@0 {
compatible = "arm,scmi-shmem";
reg = <0x0 0x400>;
};
};
firmware {
scmi {
compatible = "arm,scmi-smc";
arm,smc-id = <0xc20000fe>;
#address-cells = <1>;
#size-cells = <0>;
shmem = <&scmi_buf>;
scmi_devpd: protocol@11 {
reg = <0x11>;
#power-domain-cells = <1>;
};
scmi_sensor: protocol@15 {
reg = <0x15>;
#thermal-sensor-cells = <1>;
};
};
};
soc: soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x0 0x40000000>;
s4muap: mailbox@27020000 {
compatible = "fsl,imx8ulp-mu-s4";
reg = <0x27020000 0x10000>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
};
per_bridge3: bus@29000000 {
compatible = "simple-bus";
reg = <0x29000000 0x800000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
mu: mailbox@29220000 {
compatible = "fsl,imx8ulp-mu";
reg = <0x29220000 0x10000>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
status = "disabled";
};
mu3: mailbox@29230000 {
compatible = "fsl,imx8ulp-mu";
reg = <0x29230000 0x10000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc3 IMX8ULP_CLK_MU3_A>;
#mbox-cells = <2>;
status = "disabled";
};
wdog3: watchdog@292a0000 {
compatible = "fsl,imx8ulp-wdt", "fsl,imx7ulp-wdt";
reg = <0x292a0000 0x10000>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
assigned-clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>;
timeout-sec = <40>;
};
cgc1: clock-controller@292c0000 {
compatible = "fsl,imx8ulp-cgc1";
reg = <0x292c0000 0x10000>;
#clock-cells = <1>;
};
pcc3: clock-controller@292d0000 {
compatible = "fsl,imx8ulp-pcc3";
reg = <0x292d0000 0x10000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
tpm5: tpm@29340000 {
compatible = "fsl,imx8ulp-tpm", "fsl,imx7ulp-tpm";
reg = <0x29340000 0x1000>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc3 IMX8ULP_CLK_TPM5>,
<&pcc3 IMX8ULP_CLK_TPM5>;
clock-names = "ipg", "per";
status = "disabled";
};
lpi2c4: i2c@29370000 {
compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x29370000 0x10000>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>,
<&pcc3 IMX8ULP_CLK_LPI2C4>;
clock-names = "per", "ipg";
assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>;
assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
assigned-clock-rates = <48000000>;
status = "disabled";
};
lpi2c5: i2c@29380000 {
compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x29380000 0x10000>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>,
<&pcc3 IMX8ULP_CLK_LPI2C5>;
clock-names = "per", "ipg";
assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>;
assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
assigned-clock-rates = <48000000>;
status = "disabled";
};
lpuart4: serial@29390000 {
compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
reg = <0x29390000 0x1000>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc3 IMX8ULP_CLK_LPUART4>;
clock-names = "ipg";
status = "disabled";
};
lpuart5: serial@293a0000 {
compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
reg = <0x293a0000 0x1000>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc3 IMX8ULP_CLK_LPUART5>;
clock-names = "ipg";
status = "disabled";
};
lpspi4: spi@293b0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi";
reg = <0x293b0000 0x10000>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>,
<&pcc3 IMX8ULP_CLK_LPSPI4>;
clock-names = "per", "ipg";
assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>;
assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
assigned-clock-rates = <48000000>;
status = "disabled";
};
lpspi5: spi@293c0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi";
reg = <0x293c0000 0x10000>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>,
<&pcc3 IMX8ULP_CLK_LPSPI5>;
clock-names = "per", "ipg";
assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>;
assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
assigned-clock-rates = <48000000>;
status = "disabled";
};
};
per_bridge4: bus@29800000 {
compatible = "simple-bus";
reg = <0x29800000 0x800000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
pcc4: clock-controller@29800000 {
compatible = "fsl,imx8ulp-pcc4";
reg = <0x29800000 0x10000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
lpi2c6: i2c@29840000 {
compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x29840000 0x10000>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>,
<&pcc4 IMX8ULP_CLK_LPI2C6>;
clock-names = "per", "ipg";
assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>;
assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
assigned-clock-rates = <48000000>;
status = "disabled";
};
lpi2c7: i2c@29850000 {
compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x29850000 0x10000>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>,
<&pcc4 IMX8ULP_CLK_LPI2C7>;
clock-names = "per", "ipg";
assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>;
assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
assigned-clock-rates = <48000000>;
status = "disabled";
};
lpuart6: serial@29860000 {
compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
reg = <0x29860000 0x1000>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc4 IMX8ULP_CLK_LPUART6>;
clock-names = "ipg";
status = "disabled";
};
lpuart7: serial@29870000 {
compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
reg = <0x29870000 0x1000>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc4 IMX8ULP_CLK_LPUART7>;
clock-names = "ipg";
status = "disabled";
};
iomuxc1: pinctrl@298c0000 {
compatible = "fsl,imx8ulp-iomuxc1";
reg = <0x298c0000 0x10000>;
};
usdhc0: mmc@298d0000 {
compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
reg = <0x298d0000 0x10000>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
<&cgc1 IMX8ULP_CLK_XBAR_AD_DIVPLAT>,
<&pcc4 IMX8ULP_CLK_USDHC0>;
clock-names = "ipg", "ahb", "per";
power-domains = <&scmi_devpd IMX8ULP_PD_USDHC0>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step = <2>;
bus-width = <4>;
status = "disabled";
};
usdhc1: mmc@298e0000 {
compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
reg = <0x298e0000 0x10000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
<&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>,
<&pcc4 IMX8ULP_CLK_USDHC1>;
clock-names = "ipg", "ahb", "per";
power-domains = <&scmi_devpd IMX8ULP_PD_USDHC1>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step = <2>;
bus-width = <4>;
status = "disabled";
};
usdhc2: mmc@298f0000 {
compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
reg = <0x298f0000 0x10000>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
<&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>,
<&pcc4 IMX8ULP_CLK_USDHC2>;
clock-names = "ipg", "ahb", "per";
power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step = <2>;
bus-width = <4>;
status = "disabled";
};
fec: ethernet@29950000 {
compatible = "fsl,imx8ulp-fec", "fsl,imx6ul-fec", "fsl,imx6q-fec";
reg = <0x29950000 0x10000>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0";
fsl,num-tx-queues = <1>;
fsl,num-rx-queues = <1>;
status = "disabled";
};
};
gpioe: gpio@2d000080 {
compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
reg = <0x2d000080 0x1000>, <0x2d000040 0x40>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pcc4 IMX8ULP_CLK_RGPIOE>,
<&pcc4 IMX8ULP_CLK_PCTLE>;
clock-names = "gpio", "port";
gpio-ranges = <&iomuxc1 0 32 24>;
};
gpiof: gpio@2d010080 {
compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
reg = <0x2d010080 0x1000>, <0x2d010040 0x40>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pcc4 IMX8ULP_CLK_RGPIOF>,
<&pcc4 IMX8ULP_CLK_PCTLF>;
clock-names = "gpio", "port";
gpio-ranges = <&iomuxc1 0 64 32>;
};
per_bridge5: bus@2d800000 {
compatible = "simple-bus";
reg = <0x2d800000 0x800000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
cgc2: clock-controller@2da60000 {
compatible = "fsl,imx8ulp-cgc2";
reg = <0x2da60000 0x10000>;
#clock-cells = <1>;
};
pcc5: clock-controller@2da70000 {
compatible = "fsl,imx8ulp-pcc5";
reg = <0x2da70000 0x10000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
};
gpiod: gpio@2e200080 {
compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
reg = <0x2e200080 0x1000>, <0x2e200040 0x40>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pcc5 IMX8ULP_CLK_RGPIOD>,
<&pcc5 IMX8ULP_CLK_RGPIOD>;
clock-names = "gpio", "port";
gpio-ranges = <&iomuxc1 0 0 24>;
};
};
};
arch/arm/dts/imx91-11x11-frdm-u-boot.dtsi
-34
View File
@@ -1,34 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2025 NXP
*/
#include "imx91-u-boot.dtsi"
/ {
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog3>;
bootph-pre-ram;
bootph-some-ram;
};
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
};
&s4muap {
bootph-pre-ram;
bootph-some-ram;
status = "okay";
};
&clk {
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-rates;
/delete-property/ assigned-clock-parents;
};
arch/arm/dts/imx91-11x11-frdm.dts
-773
View File
@@ -1,773 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2025 NXP
*/
/dts-v1/;
#include <dt-bindings/usb/pd.h>
#include "imx91.dtsi"
/ {
compatible = "fsl,imx91-11x11-frdm", "fsl,imx91";
model = "NXP i.MX91 11X11 FRDM Board";
aliases {
ethernet0 = &fec;
ethernet1 = &eqos;
rtc0 = &pcf2131;
};
chosen {
stdout-path = &lpuart1;
};
reg_vref_1v8: regulator-adc-vref {
compatible = "regulator-fixed";
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
regulator-name = "vref_1v8";
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
off-on-delay-us = <12000>;
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
pinctrl-names = "default";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "VSD_3V3";
gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
bootph-pre-ram;
bootph-some-ram;
};
reg_vdd_12v: regulator-vdd-12v {
compatible = "regulator-fixed";
regulator-max-microvolt = <12000000>;
regulator-min-microvolt = <12000000>;
regulator-name = "reg_vdd_12v";
gpio = <&pcal6524 14 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_vexp_3v3: regulator-vexp-3v3 {
compatible = "regulator-fixed";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "VEXP_3V3";
vin-supply = <&buck4>;
gpio = <&pcal6524 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_vexp_5v: regulator-vexp-5v {
compatible = "regulator-fixed";
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
regulator-name = "VEXP_5V";
gpio = <&pcal6524 8 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reserved-memory {
ranges;
#address-cells = <2>;
#size-cells = <2>;
linux,cma {
compatible = "shared-dma-pool";
alloc-ranges = <0 0x80000000 0 0x40000000>;
reusable;
size = <0 0x10000000>;
linux,cma-default;
};
};
soc@0 {
bootph-all;
bootph-pre-ram;
};
};
&adc1 {
vref-supply = <&reg_vref_1v8>;
status = "okay";
};
&aips1 {
bootph-pre-ram;
bootph-all;
};
&aips2 {
bootph-pre-ram;
bootph-some-ram;
};
&aips3 {
bootph-pre-ram;
bootph-some-ram;
};
&clk {
bootph-all;
bootph-pre-ram;
};
&clk_ext1 {
bootph-all;
bootph-pre-ram;
};
&eqos {
phy-handle = <&ethphy1>;
phy-mode = "rgmii-id";
pinctrl-0 = <&pinctrl_eqos>;
pinctrl-1 = <&pinctrl_eqos_sleep>;
pinctrl-names = "default", "sleep";
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <5000000>;
ethphy1: ethernet-phy@1 {
reg = <1>;
eee-broken-1000t;
reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>;
reset-assert-us = <15000>;
reset-deassert-us = <100000>;
};
};
};
&fec {
phy-handle = <&ethphy2>;
phy-mode = "rgmii-id";
pinctrl-0 = <&pinctrl_fec>;
pinctrl-1 = <&pinctrl_fec_sleep>;
pinctrl-names = "default", "sleep";
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <5000000>;
ethphy2: ethernet-phy@2 {
reg = <2>;
eee-broken-1000t;
reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>;
reset-assert-us = <15000>;
reset-deassert-us = <100000>;
};
};
};
&gpio1 {
bootph-pre-ram;
bootph-some-ram;
};
&gpio2 {
bootph-pre-ram;
bootph-some-ram;
};
&gpio3 {
bootph-pre-ram;
bootph-some-ram;
};
&gpio4 {
bootph-pre-ram;
bootph-some-ram;
};
&lpi2c1 {
bootph-pre-ram;
bootph-some-ram;
};
&lpi2c2 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <400000>;
pinctrl-0 = <&pinctrl_lpi2c2>;
pinctrl-names = "default";
status = "okay";
bootph-pre-ram;
bootph-some-ram;
pcal6524: gpio@22 {
compatible = "nxp,pcal6524";
reg = <0x22>;
#interrupt-cells = <2>;
interrupt-controller;
interrupt-parent = <&gpio3>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
#gpio-cells = <2>;
gpio-controller;
pinctrl-0 = <&pinctrl_pcal6524>;
pinctrl-names = "default";
};
pmic@25 {
compatible = "nxp,pca9451a";
reg = <0x25>;
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
interrupt-parent = <&pcal6524>;
bootph-pre-ram;
bootph-some-ram;
regulators {
bootph-pre-ram;
bootph-some-ram;
buck1: BUCK1 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <2237500>;
regulator-min-microvolt = <650000>;
regulator-name = "BUCK1";
regulator-ramp-delay = <3125>;
};
buck2: BUCK2 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <2187500>;
regulator-min-microvolt = <600000>;
regulator-name = "BUCK2";
regulator-ramp-delay = <3125>;
};
buck4: BUCK4 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3400000>;
regulator-min-microvolt = <600000>;
regulator-name = "BUCK4";
};
buck5: BUCK5 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3400000>;
regulator-min-microvolt = <600000>;
regulator-name = "BUCK5";
};
buck6: BUCK6 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3400000>;
regulator-min-microvolt = <600000>;
regulator-name = "BUCK6";
};
ldo1: LDO1 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <1600000>;
regulator-name = "LDO1";
};
ldo4: LDO4 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <800000>;
regulator-name = "LDO4";
};
ldo5: LDO5 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <1800000>;
regulator-name = "LDO5";
};
};
};
eeprom: at24c256@50 {
compatible = "atmel,24c256";
reg = <0x50>;
pagesize = <64>;
};
};
&lpi2c3 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <400000>;
pinctrl-0 = <&pinctrl_lpi2c3>;
pinctrl-names = "default";
status = "okay";
bootph-pre-ram;
bootph-some-ram;
ptn5110: tcpc@50 {
compatible = "nxp,ptn5110", "tcpci";
reg = <0x50>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&gpio3>;
status = "okay";
typec1_con: connector {
compatible = "usb-c-connector";
data-role = "dual";
label = "USB-C";
op-sink-microwatt = <15000000>;
power-role = "dual";
self-powered;
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
PDO_VAR(5000, 20000, 3000)>;
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
try-power-role = "sink";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
typec1_dr_sw: endpoint {
remote-endpoint = <&usb1_drd_sw>;
};
};
};
};
};
pcf2131: rtc@53 {
compatible = "nxp,pcf2131";
reg = <0x53>;
interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
interrupt-parent = <&pcal6524>;
status = "okay";
};
};
&lpuart1 {
pinctrl-0 = <&pinctrl_uart1>;
pinctrl-names = "default";
status = "okay";
bootph-pre-ram;
bootph-some-ram;
};
&lpuart5 {
pinctrl-0 = <&pinctrl_uart5>;
pinctrl-names = "default";
status = "okay";
};
&osc_32k {
bootph-all;
bootph-pre-ram;
};
&osc_24m {
bootph-all;
bootph-pre-ram;
};
&usbotg1 {
adp-disable;
disable-over-current;
dr_mode = "otg";
hnp-disable;
srp-disable;
usb-role-switch;
samsung,picophy-dc-vol-level-adjust = <7>;
samsung,picophy-pre-emp-curr-control = <3>;
status = "okay";
port {
usb1_drd_sw: endpoint {
remote-endpoint = <&typec1_dr_sw>;
};
};
};
&usbotg2 {
disable-over-current;
dr_mode = "host";
samsung,picophy-dc-vol-level-adjust = <7>;
samsung,picophy-pre-emp-curr-control = <3>;
status = "okay";
};
&usdhc1 {
bus-width = <8>;
non-removable;
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
status = "okay";
bootph-pre-ram;
bootph-some-ram;
};
&usdhc2 {
bus-width = <4>;
cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
no-mmc;
no-sdio;
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
&wdog3 {
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
bootph-pre-ram;
bootph-some-ram;
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX91_PAD_ENET1_MDC__ENET1_MDC 0x57e
MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e
MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x5fe
MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e
MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x57e
MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e
MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e
MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe
MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e
>;
};
pinctrl_eqos_sleep: eqossleepgrp {
fsl,pins = <
MX91_PAD_ENET1_MDC__GPIO4_IO0 0x31e
MX91_PAD_ENET1_MDIO__GPIO4_IO1 0x31e
MX91_PAD_ENET1_RD0__GPIO4_IO10 0x31e
MX91_PAD_ENET1_RD1__GPIO4_IO11 0x31e
MX91_PAD_ENET1_RD2__GPIO4_IO12 0x31e
MX91_PAD_ENET1_RD3__GPIO4_IO13 0x31e
MX91_PAD_ENET1_RXC__GPIO4_IO9 0x31e
MX91_PAD_ENET1_RX_CTL__GPIO4_IO8 0x31e
MX91_PAD_ENET1_TD0__GPIO4_IO5 0x31e
MX91_PAD_ENET1_TD1__GPIO4_IO4 0x31e
MX91_PAD_ENET1_TD2__GPIO4_IO3 0x31e
MX91_PAD_ENET1_TD3__GPIO4_IO2 0x31e
MX91_PAD_ENET1_TXC__GPIO4_IO7 0x31e
MX91_PAD_ENET1_TX_CTL__GPIO4_IO6 0x31e
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX91_PAD_ENET2_MDC__ENET2_MDC 0x57e
MX91_PAD_ENET2_MDIO__ENET2_MDIO 0x57e
MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x57e
MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x57e
MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x57e
MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x57e
MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x5fe
MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x57e
MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x57e
MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x57e
MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x57e
MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x57e
MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x5fe
MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x57e
>;
};
pinctrl_fec_sleep: fecsleepgrp {
fsl,pins = <
MX91_PAD_ENET2_MDC__GPIO4_IO14 0x51e
MX91_PAD_ENET2_MDIO__GPIO4_IO15 0x51e
MX91_PAD_ENET2_RD0__GPIO4_IO24 0x51e
MX91_PAD_ENET2_RD1__GPIO4_IO25 0x51e
MX91_PAD_ENET2_RD2__GPIO4_IO26 0x51e
MX91_PAD_ENET2_RD3__GPIO4_IO27 0x51e
MX91_PAD_ENET2_RXC__GPIO4_IO23 0x51e
MX91_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e
MX91_PAD_ENET2_TD0__GPIO4_IO19 0x51e
MX91_PAD_ENET2_TD1__GPIO4_IO18 0x51e
MX91_PAD_ENET2_TD2__GPIO4_IO17 0x51e
MX91_PAD_ENET2_TD3__GPIO4_IO16 0x51e
MX91_PAD_ENET2_TXC__GPIO4_IO21 0x51e
MX91_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e
>;
};
pinctrl_lcdif_gpio: lcdifgpiogrp {
fsl,pins = <
MX91_PAD_GPIO_IO00__GPIO2_IO0 0x51e
MX91_PAD_GPIO_IO01__GPIO2_IO1 0x51e
MX91_PAD_GPIO_IO02__GPIO2_IO2 0x51e
MX91_PAD_GPIO_IO03__GPIO2_IO3 0x51e
>;
};
pinctrl_lcdif: lcdifgrp {
fsl,pins = <
MX91_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x31e
MX91_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x31e
MX91_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x31e
MX91_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x31e
MX91_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA0 0x31e
MX91_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA1 0x31e
MX91_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA2 0x31e
MX91_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA3 0x31e
MX91_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA4 0x31e
MX91_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA5 0x31e
MX91_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA6 0x31e
MX91_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA7 0x31e
MX91_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA8 0x31e
MX91_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA9 0x31e
MX91_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x31e
MX91_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x31e
MX91_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x31e
MX91_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x31e
MX91_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x31e
MX91_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x31e
MX91_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x31e
MX91_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x31e
MX91_PAD_GPIO_IO27__GPIO2_IO27 0x31e
>;
};
pinctrl_lpi2c1: lpi2c1grp {
fsl,pins = <
MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e
MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e
>;
bootph-pre-ram;
bootph-some-ram;
};
pinctrl_lpi2c2: lpi2c2grp {
fsl,pins = <
MX91_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e
MX91_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e
>;
bootph-pre-ram;
bootph-some-ram;
};
pinctrl_lpi2c3: lpi2c3grp {
fsl,pins = <
MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
>;
bootph-pre-ram;
bootph-some-ram;
};
pinctrl_pcal6524: pcal6524grp {
fsl,pins = <
MX91_PAD_CCM_CLKO2__GPIO3_IO27 0x31e
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x31e
>;
bootph-pre-ram;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX91_PAD_UART1_RXD__LPUART1_RX 0x31e
MX91_PAD_UART1_TXD__LPUART1_TX 0x31e
>;
bootph-pre-ram;
bootph-some-ram;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e
MX91_PAD_DAP_TDI__LPUART5_RX 0x31e
MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e
MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX91_PAD_SD1_CLK__USDHC1_CLK 0x158e
MX91_PAD_SD1_CMD__USDHC1_CMD 0x138e
MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x138e
MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x138e
MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x138e
MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x138e
MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x138e
MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x138e
MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX91_PAD_SD1_CLK__USDHC1_CLK 0x15fe
MX91_PAD_SD1_CMD__USDHC1_CMD 0x13fe
MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX91_PAD_SD1_CLK__USDHC1_CLK 0x1582
MX91_PAD_SD1_CMD__USDHC1_CMD 0x1382
MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x1382
MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x1382
MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x1382
MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x1382
MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x1382
MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x1382
MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x1382
MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x1382
MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x1582
>;
bootph-pre-ram;
bootph-some-ram;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX91_PAD_SD2_CLK__USDHC2_CLK 0x158e
MX91_PAD_SD2_CMD__USDHC2_CMD 0x138e
MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX91_PAD_SD2_CLK__USDHC2_CLK 0x15fe
MX91_PAD_SD2_CMD__USDHC2_CMD 0x13fe
MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe
MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe
MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe
MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe
MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX91_PAD_SD2_CD_B__GPIO3_IO0 0x31e
>;
bootph-pre-ram;
bootph-some-ram;
};
pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp {
fsl,pins = <
MX91_PAD_SD2_CD_B__GPIO3_IO0 0x51e
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX91_PAD_SD2_CLK__USDHC2_CLK 0x1582
MX91_PAD_SD2_CMD__USDHC2_CMD 0x1382
MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x1382
MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x1382
MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x1382
MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x1382
MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
bootph-pre-ram;
bootph-some-ram;
};
pinctrl_usdhc2_sleep: usdhc2sleepgrp {
fsl,pins = <
MX91_PAD_SD2_CLK__GPIO3_IO1 0x51e
MX91_PAD_SD2_CMD__GPIO3_IO2 0x51e
MX91_PAD_SD2_DATA0__GPIO3_IO3 0x51e
MX91_PAD_SD2_DATA1__GPIO3_IO4 0x51e
MX91_PAD_SD2_DATA2__GPIO3_IO5 0x51e
MX91_PAD_SD2_DATA3__GPIO3_IO6 0x51e
MX91_PAD_SD2_VSELECT__GPIO3_IO19 0x51e
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX91_PAD_SD3_CLK__USDHC3_CLK 0x158e
MX91_PAD_SD3_CMD__USDHC3_CMD 0x138e
MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x138e
MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x138e
MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x138e
MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x138e
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX91_PAD_SD3_CLK__USDHC3_CLK 0x15fe
MX91_PAD_SD3_CMD__USDHC3_CMD 0x13fe
MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe
MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe
MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe
MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX91_PAD_SD3_CLK__USDHC3_CLK 0x1582
MX91_PAD_SD3_CMD__USDHC3_CMD 0x1382
MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x1382
MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x1382
MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x1382
MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x1382
>;
};
pinctrl_usdhc3_sleep: usdhc3sleepgrp {
fsl,pins = <
MX91_PAD_SD3_CLK__GPIO3_IO20 0x31e
MX91_PAD_SD3_CMD__GPIO3_IO21 0x31e
MX91_PAD_SD3_DATA0__GPIO3_IO22 0x31e
MX91_PAD_SD3_DATA1__GPIO3_IO23 0x31e
MX91_PAD_SD3_DATA2__GPIO3_IO24 0x31e
MX91_PAD_SD3_DATA3__GPIO3_IO25 0x31e
>;
};
};
arch/arm/dts/imx91-93-phyboard-segin-common-u-boot.dtsi
-228
View File
@@ -1,228 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2026 PHYTEC Messtechnik GmbH
* Author: Primoz Fiser <primoz.fiser@norik.com>
*
*/
/ {
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog3>;
bootph-pre-ram;
bootph-some-ram;
};
aliases {
ethernet0 = &fec;
ethernet1 = &eqos;
};
bootstd {
bootph-verify;
compatible = "u-boot,boot-std";
filename-prefixes = "/", "/boot/";
bootdev-order = "mmc0", "mmc1", "ethernet";
rauc {
compatible = "u-boot,distro-rauc";
};
script {
compatible = "u-boot,script";
};
};
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
};
&{/soc@0} {
bootph-all;
bootph-pre-ram;
};
&aips1 {
bootph-pre-ram;
bootph-all;
};
&aips2 {
bootph-pre-ram;
bootph-some-ram;
};
&aips3 {
bootph-pre-ram;
bootph-some-ram;
};
&iomuxc {
bootph-pre-ram;
bootph-some-ram;
};
&reg_usdhc2_vmmc {
u-boot,off-on-delay-us = <20000>;
bootph-pre-ram;
bootph-some-ram;
};
&pinctrl_lpi2c3 {
bootph-pre-ram;
bootph-some-ram;
};
&pinctrl_pmic {
bootph-pre-ram;
bootph-some-ram;
};
&pinctrl_reg_usdhc2_vmmc {
bootph-pre-ram;
};
&pinctrl_uart1 {
bootph-pre-ram;
bootph-some-ram;
};
&pinctrl_usdhc1 {
bootph-pre-ram;
bootph-some-ram;
};
&pinctrl_usdhc1_100mhz {
bootph-pre-ram;
bootph-some-ram;
};
&pinctrl_usdhc1_200mhz {
bootph-pre-ram;
bootph-some-ram;
};
&pinctrl_usdhc2_cd {
bootph-pre-ram;
bootph-some-ram;
};
&pinctrl_usdhc2_default {
bootph-pre-ram;
bootph-some-ram;
};
&pinctrl_usdhc2_100mhz {
bootph-pre-ram;
bootph-some-ram;
};
&pinctrl_usdhc2_200mhz {
bootph-pre-ram;
bootph-some-ram;
};
&gpio1 {
bootph-pre-ram;
bootph-some-ram;
};
&gpio2 {
bootph-pre-ram;
bootph-some-ram;
};
&gpio3 {
bootph-pre-ram;
bootph-some-ram;
};
&gpio4 {
bootph-pre-ram;
bootph-some-ram;
};
&lpuart1 {
bootph-pre-ram;
bootph-some-ram;
};
&usdhc1 {
bootph-pre-ram;
bootph-some-ram;
};
&usdhc2 {
bootph-pre-ram;
bootph-some-ram;
fsl,signal-voltage-switch-extra-delay-ms = <8>;
};
&lpi2c1 {
bootph-pre-ram;
bootph-some-ram;
};
&lpi2c2 {
bootph-pre-ram;
bootph-some-ram;
};
&lpi2c3 {
bootph-pre-ram;
bootph-some-ram;
pmic@25 {
bootph-pre-ram;
bootph-some-ram;
regulators {
bootph-pre-ram;
bootph-some-ram;
};
};
eeprom@50 {
bootph-pre-ram;
bootph-some-ram;
};
};
&s4muap {
bootph-pre-ram;
bootph-some-ram;
status = "okay";
};
&clk {
bootph-all;
bootph-pre-ram;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-rates;
/delete-property/ assigned-clock-parents;
};
&osc_32k {
bootph-all;
bootph-pre-ram;
};
&osc_24m {
bootph-all;
bootph-pre-ram;
};
&clk_ext1 {
bootph-all;
bootph-pre-ram;
};
&wdog3 {
bootph-all;
bootph-pre-ram;
};

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