forked from OERV-BSP/u-boot
board: spacemit-k3: Add support for boot console and its pinctrl
First usable state reached: SPL booted and console printed
This commit is contained in:
@@ -19,6 +19,10 @@ config SPACEMIT_K3
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imply FIT
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imply SPL_LOAD_FIT
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imply SPL_LOAD_FIT_FULL
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imply PINCTRL
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imply SPL_PINCTRL
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imply PINCTRL_SINGLE
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imply SYS_NS16550
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if SPACEMIT_K3
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46
arch/riscv/dts/k3-pinctrl.dtsi
Normal file
46
arch/riscv/dts/k3-pinctrl.dtsi
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@@ -0,0 +1,46 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/* Copyright (c) 2025 Spacemit, Inc */
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#include <dt-bindings/pinctrl/k3-pinctrl.h>
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&pinctrl {
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pinctrl_uart0_0: uart0_0_grp {
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bootph-all;
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pinctrl-single,pins = <
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K3_PADCONF(149, MUX_MODE2, (PULL_UP | PAD_DS8)) /* tx */
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K3_PADCONF(150, MUX_MODE2, (PULL_UP | PAD_DS8)) /* rx */
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>;
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};
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pinctrl_uart0_1: uart0_1_grp {
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bootph-all;
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pinctrl-single,pins = <
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K3_PADCONF(132, MUX_MODE2, (PULL_UP | PAD_DS8)) /* tx */
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K3_PADCONF(133, MUX_MODE2, (PULL_UP | PAD_DS8)) /* rx */
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>;
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};
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pinctrl_uart0_2: uart0_2_grp {
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bootph-all;
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pinctrl-single,pins = <
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K3_PADCONF(145, MUX_MODE5, (PULL_UP | PAD_DS8)) /* tx */
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K3_PADCONF(146, MUX_MODE5, (PULL_UP | PAD_DS8)) /* rx */
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>;
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};
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pinctrl_uart0_3: uart0_3_grp {
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bootph-all;
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pinctrl-single,pins = <
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K3_PADCONF(42, MUX_MODE2, (PULL_UP | PAD_DS8)) /* tx */
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K3_PADCONF(43, MUX_MODE2, (PULL_UP | PAD_DS8)) /* rx */
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>;
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};
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pinctrl_uart0_4: uart0_4_grp {
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bootph-all;
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pinctrl-single,pins = <
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K3_PADCONF(93, MUX_MODE3, (PULL_UP | PAD_DS8)) /* tx */
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K3_PADCONF(94, MUX_MODE3, (PULL_UP | PAD_DS8)) /* rx */
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>;
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};
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};
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@@ -4,6 +4,7 @@
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*/
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#include "k3.dtsi"
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#include "k3-pinctrl.dtsi"
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#include "binman.dtsi"
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/ {
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@@ -19,3 +20,9 @@
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reg = <0x00000000 0x00000000 0x00000000 0x80000000>;
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};
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};
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&serial0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart0_0>;
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status = "okay";
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};
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@@ -14,6 +14,42 @@
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compatible = "spacemit,k3";
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aliases {
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serial0 = &serial0;
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};
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soc {
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bootph-all;
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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ranges;
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pinctrl: pinctrl@d401e000 {
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bootph-all;
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compatible = "pinctrl-single";
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reg = <0x0 0xd401e000 0x0 0x400>;
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#address-cells = <1>;
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#size-cells = <1>;
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#pinctrl-cells = <1>;
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#gpio-range-cells = <3>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0xffff>;
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range: gpio-range {
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bootph-all;
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#pinctrl-single,gpio-range-cells = <3>;
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};
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};
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serial0: serial@d4017000 {
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bootph-all;
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compatible = "intel,xscale-uart";
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reg = <0x00000000 0xD4017000 0x00000000 0x00000100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clock-frequency = <14745600>;
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status = "disabled";
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};
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};
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};
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@@ -6,6 +6,6 @@
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CFG_SYS_NS16550_IER 0x40
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#endif /* __CONFIG_H */
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229
include/dt-bindings/pinctrl/k3-pinctrl.h
Normal file
229
include/dt-bindings/pinctrl/k3-pinctrl.h
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@@ -0,0 +1,229 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef __DT_BINDINGS_K3_PINCTRL_H
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#define __DT_BINDINGS_K3_PINCTRL_H
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/*
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* For K3:
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* +---------+----------+-----------+--------+--------+----------+--------+
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* | pull | drive | schmitter | slew | edge | strong | mux |
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* | up/down | strength | trigger | rate | detect | pull | mode |
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* +---------+----------+-----------+--------+--------+----------+--------+
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* 3 bits 4 bits 1 bits 1 bit 3 bits 1 bit 3 bits
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*/
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/* pinnum list */
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#define GPIO_00 (0)
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#define GPIO_01 (1)
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#define GPIO_02 (2)
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#define GPIO_03 (3)
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#define GPIO_04 (4)
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#define GPIO_05 (5)
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#define GPIO_06 (6)
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#define GPIO_07 (7)
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#define GPIO_08 (8)
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#define GPIO_09 (9)
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#define GPIO_10 (10)
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#define GPIO_11 (11)
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#define GPIO_12 (12)
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#define GPIO_13 (13)
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#define GPIO_14 (14)
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#define GPIO_15 (15)
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#define GPIO_16 (16)
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#define GPIO_17 (17)
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#define GPIO_18 (18)
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#define GPIO_19 (19)
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#define GPIO_20 (20)
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#define GPIO_21 (21)
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#define GPIO_22 (22)
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#define GPIO_23 (23)
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#define GPIO_24 (24)
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#define GPIO_25 (25)
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#define GPIO_26 (26)
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#define GPIO_27 (27)
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#define GPIO_28 (28)
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#define GPIO_29 (29)
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#define GPIO_30 (30)
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#define GPIO_31 (31)
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#define GPIO_32 (32)
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#define GPIO_33 (33)
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#define GPIO_34 (34)
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#define GPIO_35 (35)
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#define GPIO_36 (36)
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#define GPIO_37 (37)
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#define GPIO_38 (38)
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#define GPIO_39 (39)
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#define GPIO_40 (40)
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#define GPIO_41 (41)
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#define GPIO_42 (42)
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#define GPIO_43 (43)
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#define GPIO_44 (44)
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#define GPIO_45 (45)
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#define GPIO_46 (46)
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#define GPIO_47 (47)
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#define GPIO_48 (48)
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#define GPIO_49 (49)
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#define GPIO_50 (50)
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#define GPIO_51 (51)
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#define GPIO_52 (52)
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#define GPIO_53 (53)
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#define GPIO_54 (54)
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#define GPIO_55 (55)
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#define GPIO_56 (56)
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#define GPIO_57 (57)
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#define GPIO_58 (58)
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#define GPIO_59 (59)
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#define GPIO_60 (60)
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#define GPIO_61 (61)
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#define GPIO_62 (62)
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#define GPIO_63 (63)
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#define GPIO_64 (64)
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#define GPIO_65 (65)
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#define GPIO_66 (66)
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#define GPIO_67 (67)
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#define GPIO_68 (68)
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#define GPIO_69 (69)
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#define GPIO_70 (70)
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#define GPIO_71 (71)
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#define GPIO_72 (72)
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#define GPIO_73 (73)
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#define GPIO_74 (74)
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#define GPIO_75 (75)
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#define GPIO_76 (76)
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#define GPIO_77 (77)
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#define GPIO_78 (78)
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#define GPIO_79 (79)
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#define GPIO_80 (80)
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#define GPIO_81 (81)
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#define GPIO_82 (82)
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#define GPIO_83 (83)
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#define GPIO_84 (84)
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#define GPIO_85 (85)
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#define GPIO_86 (86)
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#define GPIO_87 (87)
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#define GPIO_88 (88)
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#define GPIO_89 (89)
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#define GPIO_90 (90)
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#define GPIO_91 (91)
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#define GPIO_92 (92)
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#define GPIO_93 (93)
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#define GPIO_94 (94)
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#define GPIO_95 (95)
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#define GPIO_96 (96)
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#define GPIO_97 (97)
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#define GPIO_98 (98)
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#define GPIO_99 (99)
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#define GPIO_100 (100)
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#define GPIO_101 (101)
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#define GPIO_102 (102)
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#define GPIO_103 (103)
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#define GPIO_104 (104)
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#define GPIO_105 (105)
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#define GPIO_106 (106)
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#define GPIO_107 (107)
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#define GPIO_108 (108)
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#define GPIO_109 (109)
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#define GPIO_110 (110)
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#define GPIO_111 (111)
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#define GPIO_112 (112)
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#define GPIO_113 (113)
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#define GPIO_114 (114)
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#define GPIO_115 (115)
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#define GPIO_116 (116)
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#define GPIO_117 (117)
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#define GPIO_118 (118)
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#define GPIO_119 (119)
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#define GPIO_120 (120)
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#define GPIO_121 (121)
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#define GPIO_122 (122)
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#define GPIO_123 (123)
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#define GPIO_124 (124)
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#define GPIO_125 (125)
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#define GPIO_126 (126)
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#define GPIO_127 (127)
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#define PWR_SCL (128)
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#define PWR_SDA (129)
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#define VCXO_EN (130)
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#define PMIC_INT_N (131)
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#define MMC1_DAT3 (132)
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#define MMC1_DAT2 (133)
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#define MMC1_DAT1 (134)
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#define MMC1_DAT0 (135)
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#define MMC1_CMD (136)
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#define MMC1_CLK (137)
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#define QSPI_DAT0 (138)
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#define QSPI_DAT1 (139)
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#define QSPI_DAT2 (140)
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#define QSPI_DAT3 (141)
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#define QSPI_CS0 (142)
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#define QSPI_CS1 (143)
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#define QSPI_CLK (144)
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#define PRI_TDI (145)
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#define PRI_TMS (146)
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#define PRI_TCK (147)
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#define PRI_TDO (148)
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#define PWR_SSP_SCLK (149)
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#define PWR_SSP_FRM (150)
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#define PWR_SSP_TXD (151)
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#define PWR_SSP_RXD (152)
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/* pin mux */
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#define PAD_MUX GENMASK(2, 0)
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#define MUX_MODE0 0
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#define MUX_MODE1 1
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#define MUX_MODE2 2
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#define MUX_MODE3 3
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#define MUX_MODE4 4
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#define MUX_MODE5 5
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#define MUX_MODE6 6
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#define MUX_MODE7 7
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#define PAD_STRONG_PULL BIT(3)
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#define PAD_EDGE GENMASK(6, 4)
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#define PAD_EDGE_RISE BIT(4)
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#define PAD_EDGE_FALL BIT(5)
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#define PAD_EDGE_CLEAR BIT(6)
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#define PAD_SLEW_RATE_EN BIT(7)
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#define PAD_SCHMITT BIT(8)
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#define PAD_PULLDOWN BIT(13)
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#define PAD_PULLUP BIT(14)
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#define PAD_PULL_EN BIT(15)
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/*
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* drive strength
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* DRIVE[3:0] -> bits[12:9]
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*/
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#define PAD_DRIVE GENMASK(12, 9)
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#define PAD_DS0 (0 << 9) /* bit[12:9] 0000 */
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#define PAD_DS1 (1 << 9) /* bit[12:9] 0001 */
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#define PAD_DS2 (2 << 9) /* bit[12:9] 0010 */
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#define PAD_DS3 (3 << 9) /* bit[12:9] 0011 */
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#define PAD_DS4 (4 << 9) /* bit[12:9] 0100 */
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#define PAD_DS5 (5 << 9) /* bit[12:9] 0101 */
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#define PAD_DS6 (6 << 9) /* bit[12:9] 0110 */
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#define PAD_DS7 (7 << 9) /* bit[12:9] 0111 */
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#define PAD_DS8 (8 << 9) /* bit[12:9] 1000 */
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#define PAD_DS9 (9 << 9) /* bit[12:9] 1001 */
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#define PAD_DS10 (10 << 9) /* bit[12:9] 1010 */
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#define PAD_DS11 (11 << 9) /* bit[12:9] 1011 */
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#define PAD_DS12 (12 << 9) /* bit[12:9] 1100 */
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#define PAD_DS13 (13 << 9) /* bit[12:9] 1101 */
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#define PAD_DS14 (14 << 9) /* bit[12:9] 1110 */
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#define PAD_DS15 (15 << 9) /* bit[12:9] 1111 */
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/* pull up/down */
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#define PULL_DIS (0 << 13) /* bit[15:13] 000 */
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#define PULL_UP (6 << 13) /* bit[15:13] 110 */
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#define PULL_DOWN (5 << 13) /* bit[15:13] 101 */
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// pin reg offset
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#define PIN_ID(x) ((x) > 130? (x) + 2: (x))
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// pinctrl-single,pins
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#define K3_PADCONF(pinid, mux, conf) ((PIN_ID(pinid)) << 2) ((conf) | (mux))
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#endif /* __DT_BINDINGS_K3_PINCTRL_H */
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