126 lines
2.8 KiB
Plaintext
126 lines
2.8 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2021-2024 Alibaba Group Holding Limited.
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*/
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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model = "A200 HAPS";
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compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,th1520", "thead,light";
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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serial0 = &uart0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x200000 0x0 0xffe00000>;
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numa-node-id = <0>;
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};
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cpus: cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <3000000>;
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c910_0: cpu@0 {
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compatible = "thead,c910", "riscv";
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device_type = "cpu";
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riscv,isa = "rv64imafdcv";
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reg = <0>;
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i-cache-block-size = <64>;
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i-cache-size = <65536>;
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i-cache-sets = <512>;
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d-cache-block-size = <64>;
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d-cache-size = <65536>;
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d-cache-sets = <512>;
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next-level-cache = <&l2_cache>;
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mmu-type = "riscv,sv39";
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video-4k-minfreq = <1848000000>;
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qos-mid-minfreq = <750000000>;
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#cooling-cells = <2>;
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dynamic-power-coefficient = <500>;
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cpu0_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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l2_cache: l2-cache {
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compatible = "cache";
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cache-block-size = <64>;
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cache-level = <2>;
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cache-size = <1048576>;
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cache-sets = <1024>;
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cache-unified;
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};
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};
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uart_sclk: uart-sclk-clock {
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compatible = "fixed-clock";
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clock-frequency = <50000000>;
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clock-output-names = "uart_sclk";
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#clock-cells = <0>;
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};
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soc {
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compatible = "simple-bus";
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interrupt-parent = <&plic>;
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#address-cells = <2>;
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#size-cells = <2>;
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dma-noncoherent;
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ranges;
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uart0: serial@ffe7014000 {
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compatible = "snps,dw-apb-uart", "light,uart0";
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reg = <0xff 0xe7014000 0x0 0x100>;
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interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&uart_sclk>;
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reg-shift = <2>;
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reg-io-width = <4>;
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current-speed = <115200>; /* OpenSBI */
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status = "okay";
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};
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/* OpenSBI */
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reset: reset-sample {
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compatible = "thead,reset-sample";
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plic-delegate = <0xff 0xd81ffffc>;
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entry-reg = <0xff 0xff019050>;
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entry-cnt = <4>;
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control-reg = <0xff 0xff015004>;
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control-val = <0x1c>;
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csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc 0x7ce>;
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};
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plic: interrupt-controller@ffd8000000 {
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compatible = "thead,th1520-plic", "thead,c900-plic", "riscv,plic0";
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reg = <0xff 0xd8000000 0x0 0x01000000>;
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interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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riscv,ndev = <240>;
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};
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clint: timer@ffdc000000 {
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compatible = "thead,th1520-clint", "thead,c900-clint", "riscv,clint0";
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reg = <0xff 0xdc000000 0x0 0x0000d000>;
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interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
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clint,has-no-64bit-mmio;
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};
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};
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};
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