// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (C) 2021-2024 Alibaba Group Holding Limited.
 */

/dts-v1/;

#include <dt-bindings/interrupt-controller/irq.h>

/ {
	model = "A200 HAPS";

	compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,th1520", "thead,light";
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		serial0 = &uart0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x200000 0x0 0xffe00000>;
		numa-node-id = <0>;
	};

	cpus: cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		timebase-frequency = <3000000>;

		c910_0: cpu@0 {
			compatible = "thead,c910", "riscv";
			device_type = "cpu";
			riscv,isa = "rv64imafdcv";
			reg = <0>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			next-level-cache = <&l2_cache>;
			mmu-type = "riscv,sv39";
			video-4k-minfreq = <1848000000>;
			qos-mid-minfreq = <750000000>;
			#cooling-cells = <2>;
			dynamic-power-coefficient = <500>;

			cpu0_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		l2_cache: l2-cache {
			compatible = "cache";
			cache-block-size = <64>;
			cache-level = <2>;
			cache-size = <1048576>;
			cache-sets = <1024>;
			cache-unified;
		};
	};

	uart_sclk: uart-sclk-clock {
		compatible = "fixed-clock";
		clock-frequency = <50000000>;
		clock-output-names = "uart_sclk";
		#clock-cells = <0>;
	};

	soc {
		compatible = "simple-bus";
		interrupt-parent = <&plic>;
		#address-cells = <2>;
		#size-cells = <2>;
		dma-noncoherent;
		ranges;

		uart0: serial@ffe7014000 {
		compatible = "snps,dw-apb-uart", "light,uart0";
		reg = <0xff 0xe7014000 0x0 0x100>;
		interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&uart_sclk>;
		reg-shift = <2>;
		reg-io-width = <4>;
		current-speed = <115200>; /* OpenSBI */
		status = "okay";
		};

		/* OpenSBI */
		reset: reset-sample {
			compatible = "thead,reset-sample";
			plic-delegate = <0xff 0xd81ffffc>;
			entry-reg = <0xff 0xff019050>;
			entry-cnt = <4>;
			control-reg = <0xff 0xff015004>;
			control-val = <0x1c>;
			csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc 0x7ce>;
		};

		plic: interrupt-controller@ffd8000000 {
			compatible = "thead,th1520-plic", "thead,c900-plic", "riscv,plic0";
			reg = <0xff 0xd8000000 0x0 0x01000000>;
			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			riscv,ndev = <240>;
		};

		clint: timer@ffdc000000 {
			compatible = "thead,th1520-clint", "thead,c900-clint", "riscv,clint0";
			reg = <0xff 0xdc000000 0x0 0x0000d000>;
			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
			clint,has-no-64bit-mmio;
		};
		};
};