OERV-BSP/kernel-zhihe-a210
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Release develop 260131

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This commit is contained in:
hongyi
2026-01-31 14:47:59 +08:00
parent 006816cce1
commit d1a0fed7aa
5 changed files with 64 additions and 54 deletions
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24
arch/riscv/boot/dts/zhihe/a210-soc-core.dtsi
View File

@@ -687,7 +687,11 @@
#power-domain-cells = <0>;
id = <A210_PD_TOP>;
iopmps = <&device_pcie_mt_iopmp>,<&device_pcie_iommu_iopmp>, <&device_eip120i_iopmp>,
<&device_eip120ii_iopmp>, <&device_eip120iii_iopmp>, <&device_tee_dmac_iopmp>;
<&device_eip120ii_iopmp>, <&device_eip120iii_iopmp>, <&device_tee_dmac_iopmp>,
<&device_aon_iopmp>, <&device_chip_dbg_iopmp> ,<&device_peri1_iommu_iopmp>,
<&device_gmac_0_iopmp>, <&device_gmac_1_iopmp>, <&device_gmac_2_iopmp>,
<&device_peri1_mt_iopmp>, <&device_dmac_ap_iopmp>, <&device_emmc_iopmp>,
<&device_sd_iopmp>;
};
power_gpu:power_gpu {
reg = <0x00 0x06E00600 0x0 0x200>, <0x00 0x06E00400 0x0 0x200>, <0x00 0x06E00000 0x0 0x200>;
@@ -832,23 +836,6 @@
resets = <&rst VP_VDEC_PRST>, <&rst VP_VDEC_CRST>, <&rst VP_VDEC_ARST>;
iopmps = <&device_vdec_iopmp>;
};
power_peri0:power_peri0 {
power-domains = <&power_top>;
#power-domain-cells = <0>;
id = <A210_PD_PERI0>;
clocks = <&clk_peri PERI0_TIMER1_PCLK_EN>, <&clk_peri PERI0_TIMER1_CCLK_EN>;
resets = <&rst PERI0_TIMER0_CRST>, <&rst PERI0_TIMER0_PRST>, <&rst PERI0_TIMER1_CRST>,
<&rst PERI0_TIMER1_PRST>, <&rst PERI0_WDT0_PRST>, <&rst PERI0_MBOX0_PRST>,
<&rst PERI0_MBOX1_PRST>;
};
power_peri1:power_peri1 {
power-domains = <&power_top>;
#power-domain-cells = <0>;
id = <A210_PD_PERI1>;
iopmps = <&device_aon_iopmp>, <&device_chip_dbg_iopmp> ,<&device_peri1_iommu_iopmp>,
<&device_gmac_0_iopmp>, <&device_gmac_1_iopmp>, <&device_gmac_2_iopmp>,
<&device_peri1_mt_iopmp>;
};
power_peri2:power_peri2 {
power-domains = <&power_top>;
#power-domain-cells = <0>;
@@ -888,7 +875,6 @@
<&clk_peri PERI3_SDIO_HCLK_EN>, <&clk_peri PERI3_SDIO_OSC_CLK_EN>, <&clk_peri PERI3_SDIO_X2X_ACLK_M_EN>,
<&clk_peri PERI3_SDIO_X2X_ACLK_S_EN>, <&clk_peri PERI3_ADC_PCLK_EN>;
resets = <&rst PERI3_DMAC_ARESET>, <&rst PERI3_DMAC_HRESET>, <&rst PERI3_ADC_PRST>;
iopmps = <&device_dmac_ap_iopmp>, <&device_emmc_iopmp>, <&device_sd_iopmp>;
};
};

79
arch/riscv/boot/dts/zhihe/a210-soc-peri.dtsi
View File

@@ -312,7 +312,7 @@
interrupt-parent = <&intc>;
interrupts = <331>;
clocks = <&clk_peri PERI0_WDT0_PCLK_EN>;
power-domains = <&power_peri0>;
power-domains = <&power_top>;
clock-names = "tclk";
resets = <&rst PERI0_WDT0_PRST>;
};
@@ -329,7 +329,7 @@
clocks = <&clk_peri PERI1_CAN0_HIRES_CLK_EN>,
<&clk_peri PERI1_CAN0_PCLK_EN>;
clock-names = "ipg", "per";
power-domains = <&power_peri1>;
power-domains = <&power_top>;
/* fsl,stop-mode = <&gpr 0x34 29 0x10 18>; */
};
@@ -341,7 +341,7 @@
clocks = <&clk_peri PERI1_CAN1_HIRES_CLK_EN>,
<&clk_peri PERI1_CAN1_PCLK_EN>;
clock-names = "ipg", "per";
power-domains = <&power_peri1>;
power-domains = <&power_top>;
/* fsl,stop-mode = <&gpr 0x34 29 0x10 18>; */
};
@@ -411,7 +411,7 @@
interrupts = <321>;
clocks = <&clk_peri PERI1_UART0_PCLK_EN>, <&clk_peri PERI1_UART0_SCLK_EN>;
clock-names = "apb_pclk", "baudclk";
power-domains = <&power_peri1>;
power-domains = <&power_top>;
reg-shift = <2>;
reg-io-width = <4>;
};
@@ -423,7 +423,7 @@
interrupts = <322>;
clocks = <&clk_peri PERI1_UART1_PCLK_EN>, <&clk_peri PERI1_UART1_SCLK_EN>;
clock-names = "apb_pclk", "baudclk";
power-domains = <&power_peri1>;
power-domains = <&power_top>;
reg-shift = <2>;
reg-io-width = <4>;
};
@@ -435,7 +435,7 @@
interrupts = <323>;
clocks = <&clk_peri PERI1_UART2_PCLK_EN>, <&clk_peri PERI1_UART2_SCLK_EN>;
clock-names = "apb_pclk", "baudclk";
power-domains = <&power_peri1>;
power-domains = <&power_top>;
reg-shift = <2>;
reg-io-width = <4>;
};
@@ -447,7 +447,7 @@
interrupts = <324>;
clocks = <&clk_peri PERI1_UART3_PCLK_EN>, <&clk_peri PERI1_UART3_SCLK_EN>;
clock-names = "apb_pclk", "baudclk";
power-domains = <&power_peri1>;
power-domains = <&power_top>;
reg-shift = <2>;
reg-io-width = <4>;
};
@@ -542,7 +542,7 @@
interrupts = <310>;
clocks = <&clk_peri PERI1_SPI0_SSI_CLK_EN>;
clock-names = "sclk";
power-domains = <&power_peri1>;
power-domains = <&power_top>;
dmas = <&dmac0 9>, <&dmac0 8>;
dma-names = "tx", "rx";
dma-tx-addr-incr;
@@ -578,7 +578,7 @@
interrupts = <308>;
clocks = <&clk_peri PERI1_QSPI0_SSI_CLK_EN>;
clock-names = "sclk";
power-domains = <&power_peri1>;
power-domains = <&power_top>;
num-cs = <2>;
#address-cells = <1>;
#size-cells = <0>;
@@ -653,7 +653,7 @@
clocks = <&clk_peri PERI1_GMAC0_ACLK_EN>,
<&clk_peri PERI1_GMAC0_HCLK_EN>;
clock-names = "gmac_aclk", "gmac_hclk";
power-domains = <&power_peri1>;
power-domains = <&power_top>;
snps,pbl = <32>;
snps,fixed-burst;
snps,axi-config = <&stmmac_axi_setup>;
@@ -678,7 +678,7 @@
clocks = <&clk_peri PERI1_GMAC1_ACLK_EN>,
<&clk_peri PERI1_GMAC1_HCLK_EN>;
clock-names = "gmac_aclk", "gmac_hclk";
power-domains = <&power_peri1>;
power-domains = <&power_top>;
snps,pbl = <32>;
snps,fixed-burst;
snps,axi-config = <&stmmac_axi_setup>;
@@ -774,7 +774,7 @@
clocks = <&clk_peri PERI1_GPIO0_PCLK_EN>,
<&clk_peri PERI1_GPIO0_DBCLK_EN>;
clock-names = "bus", "db";
power-domains = <&power_peri1>;
power-domains = <&power_top>;
gpio0: gpio0-controller@0 {
compatible = "snps,dw-apb-gpio-port";
@@ -799,7 +799,7 @@
clocks = <&clk_peri PERI1_GPIO1_PCLK_EN>,
<&clk_peri PERI1_GPIO1_DBCLK_EN>;
clock-names = "bus", "db";
power-domains = <&power_peri1>;
power-domains = <&power_top>;
gpio1: gpio1-controller@0 {
compatible = "snps,dw-apb-gpio-port";
@@ -897,7 +897,7 @@
#pwm-cells = <2>;
clocks = <&clk_peri PERI1_PWM0_CCLK_EN>;
clock-names = "cclk";
power-domains = <&power_peri1>;
power-domains = <&power_top>;
interrupts = <305>;
interrupt-parent = <&intc>;
};
@@ -929,6 +929,7 @@
reg = <0x00 0x00303000 0x0 0x14>;
clocks = <&clk_peri PERI0_TIMER0_PCLK_EN>, <&clk_peri PERI0_TIMER0_CCLK_EN>;
clock-names = "pclk", "timer";
resets = <&rst PERI0_TIMER0_RST>;
interrupts = <313>;
interrupt-parent = <&intc>;
};
@@ -938,6 +939,7 @@
reg = <0x00 0x00303014 0x0 0x14>;
clocks = <&clk_peri PERI0_TIMER0_PCLK_EN>, <&clk_peri PERI0_TIMER0_CCLK_EN>;
clock-names = "pclk", "timer";
resets = <&rst PERI0_TIMER0_RST>;
interrupts = <314>;
interrupt-parent = <&intc>;
};
@@ -947,6 +949,7 @@
reg = <0x00 0x00303028 0x0 0x14>;
clocks = <&clk_peri PERI0_TIMER0_PCLK_EN>, <&clk_peri PERI0_TIMER0_CCLK_EN>;
clock-names = "pclk", "timer";
resets = <&rst PERI0_TIMER0_RST>;
interrupts = <315>;
interrupt-parent = <&intc>;
};
@@ -956,6 +959,7 @@
reg = <0x00 0x0030303c 0x0 0x14>;
clocks = <&clk_peri PERI0_TIMER0_PCLK_EN>, <&clk_peri PERI0_TIMER0_CCLK_EN>;
clock-names = "pclk", "timer";
resets = <&rst PERI0_TIMER0_RST>;
interrupts = <316>;
interrupt-parent = <&intc>;
};
@@ -965,6 +969,7 @@
reg = <0x00 0x00304000 0x0 0x14>;
clocks = <&clk_peri PERI0_TIMER1_PCLK_EN>, <&clk_peri PERI0_TIMER1_CCLK_EN>;
clock-names = "pclk", "timer";
resets = <&rst PERI0_TIMER1_RST>;
interrupts = <317>;
interrupt-parent = <&intc>;
};
@@ -974,6 +979,7 @@
reg = <0x00 0x00304014 0x0 0x14>;
clocks = <&clk_peri PERI0_TIMER1_PCLK_EN>, <&clk_peri PERI0_TIMER1_CCLK_EN>;
clock-names = "pclk", "timer";
resets = <&rst PERI0_TIMER1_RST>;
interrupts = <318>;
interrupt-parent = <&intc>;
};
@@ -983,6 +989,7 @@
reg = <0x00 0x00304028 0x0 0x14>;
clocks = <&clk_peri PERI0_TIMER1_PCLK_EN>, <&clk_peri PERI0_TIMER1_CCLK_EN>;
clock-names = "pclk", "timer";
resets = <&rst PERI0_TIMER1_RST>;
interrupts = <319>;
interrupt-parent = <&intc>;
};
@@ -992,6 +999,7 @@
reg = <0x00 0x0030403c 0x0 0x14>;
clocks = <&clk_peri PERI0_TIMER1_PCLK_EN>, <&clk_peri PERI0_TIMER1_CCLK_EN>;
clock-names = "pclk", "timer";
resets = <&rst PERI0_TIMER1_RST>;
interrupts = <320>;
interrupt-parent = <&intc>;
};
@@ -1003,7 +1011,7 @@
interrupts = <293>;
clocks = <&clk_peri PERI1_I2C0_IC_CLK_EN>, <&clk_peri PERI1_I2C0_PCLK_EN>;
clock-names = "ref", "pclk";
power-domains = <&power_peri1>;
power-domains = <&power_top>;
dma-mode;
dmas = <&dmac0 21>, <&dmac0 20>;
dma-names = "tx", "rx";
@@ -1019,7 +1027,7 @@
interrupts = <294>;
clocks = <&clk_peri PERI1_I2C1_IC_CLK_EN>, <&clk_peri PERI1_I2C1_PCLK_EN>;
clock-names = "ref", "pclk";
power-domains = <&power_peri1>;
power-domains = <&power_top>;
#address-cells = <1>;
#size-cells = <0>;
};
@@ -1031,7 +1039,7 @@
interrupts = <295>;
clocks = <&clk_peri PERI1_I2C2_IC_CLK_EN>, <&clk_peri PERI1_I2C2_PCLK_EN>;
clock-names = "ref", "pclk";
power-domains = <&power_peri1>;
power-domains = <&power_top>;
#address-cells = <1>;
#size-cells = <0>;
};
@@ -1159,7 +1167,7 @@
interrupts = <301>;
clocks = <&clk_peri PERI1_I2S0_SRC_CLK_EN>, <&clk_peri PERI1_I2S0_PCLK_EN>;
clock-names = "sclk", "pclk";
power-domains = <&power_peri1>;
power-domains = <&power_top>;
#sound-dai-cells = <1>;
dmas = <&dmac0 3>, <&dmac0 2>;
dma-names = "tx", "rx";
@@ -1273,7 +1281,7 @@
interrupts = <312>;
clocks = <&clk_peri PERI1_TDM0_SCLK_EN>, <&clk_peri PERI1_TDM0_PCLK_EN>;
clock-names = "sclk", "pclk";
power-domains = <&power_peri1>;
power-domains = <&power_top>;
#sound-dai-cells = <1>;
zhihe,peri1-sys = <&peri1_sys>;
dmas = <&dmac0 4>;
@@ -1287,7 +1295,7 @@
interrupts = <312>;
clocks = <&clk_peri PERI1_TDM0_SCLK_EN>, <&clk_peri PERI1_TDM0_PCLK_EN>;
clock-names = "sclk", "pclk";
power-domains = <&power_peri1>;
power-domains = <&power_top>;
#sound-dai-cells = <1>;
zhihe,peri1-sys = <&peri1_sys>;
dmas = <&dmac0 5>;
@@ -1301,7 +1309,7 @@
interrupts = <312>;
clocks = <&clk_peri PERI1_TDM0_SCLK_EN>, <&clk_peri PERI1_TDM0_PCLK_EN>;
clock-names = "sclk", "pclk";
power-domains = <&power_peri1>;
power-domains = <&power_top>;
#sound-dai-cells = <1>;
zhihe,peri1-sys = <&peri1_sys>;
dmas = <&dmac0 0>;
@@ -1315,7 +1323,7 @@
interrupts = <312>;
clocks = <&clk_peri PERI1_TDM0_SCLK_EN>, <&clk_peri PERI1_TDM0_PCLK_EN>;
clock-names = "sclk", "pclk";
power-domains = <&power_peri1>;
power-domains = <&power_top>;
#sound-dai-cells = <1>;
zhihe,peri1-sys = <&peri1_sys>;
dmas = <&dmac0 1>;
@@ -1329,7 +1337,7 @@
interrupts = <312>;
clocks = <&clk_peri PERI1_TDM0_SCLK_EN>, <&clk_peri PERI1_TDM0_PCLK_EN>;
clock-names = "sclk", "pclk";
power-domains = <&power_peri1>;
power-domains = <&power_top>;
#sound-dai-cells = <1>;
zhihe,peri1-sys = <&peri1_sys>;
dmas = <&dmac0 10>;
@@ -1343,7 +1351,7 @@
interrupts = <312>;
clocks = <&clk_peri PERI1_TDM0_SCLK_EN>, <&clk_peri PERI1_TDM0_PCLK_EN>;
clock-names = "sclk", "pclk";
power-domains = <&power_peri1>;
power-domains = <&power_top>;
#sound-dai-cells = <1>;
zhihe,peri1-sys = <&peri1_sys>;
dmas = <&dmac0 11>;
@@ -1357,7 +1365,7 @@
interrupts = <312>;
clocks = <&clk_peri PERI1_TDM0_SCLK_EN>, <&clk_peri PERI1_TDM0_PCLK_EN>;
clock-names = "sclk", "pclk";
power-domains = <&power_peri1>;
power-domains = <&power_top>;
#sound-dai-cells = <1>;
zhihe,peri1-sys = <&peri1_sys>;
dmas = <&dmac0 12>;
@@ -1371,7 +1379,7 @@
interrupts = <312>;
clocks = <&clk_peri PERI1_TDM0_SCLK_EN>, <&clk_peri PERI1_TDM0_PCLK_EN>;
clock-names = "sclk", "pclk";
power-domains = <&power_peri1>;
power-domains = <&power_top>;
#sound-dai-cells = <1>;
zhihe,peri1-sys = <&peri1_sys>;
dmas = <&dmac0 13>;
@@ -1513,7 +1521,7 @@
interrupts = <339>;
clocks = <&clk_peri PERI1_PDM0_MCLK_EN>, <&clk_peri PERI1_PDM0_PCLK_EN>;
clock-names = "mclk", "pclk";
power-domains = <&power_peri1>;
power-domains = <&power_top>;
#sound-dai-cells = <1>;
zhihe,peri1-sys = <&peri1_sys>;
zhihe,mode = "pdm-master";
@@ -1529,7 +1537,7 @@
interrupts = <339>;
clocks = <&clk_peri PERI1_PDM0_MCLK_EN>, <&clk_peri PERI1_PDM0_PCLK_EN>;
clock-names = "mclk", "pclk";
power-domains = <&power_peri1>;
power-domains = <&power_top>;
#sound-dai-cells = <1>;
zhihe,peri1-sys = <&peri1_sys>;
zhihe,mode = "pdm-master";
@@ -1545,7 +1553,7 @@
interrupts = <339>;
clocks = <&clk_peri PERI1_PDM0_MCLK_EN>, <&clk_peri PERI1_PDM0_PCLK_EN>;
clock-names = "mclk", "pclk";
power-domains = <&power_peri1>;
power-domains = <&power_top>;
#sound-dai-cells = <1>;
zhihe,peri1-sys = <&peri1_sys>;
zhihe,mode = "pdm-master";
@@ -1561,7 +1569,7 @@
interrupts = <339>;
clocks = <&clk_peri PERI1_PDM0_MCLK_EN>, <&clk_peri PERI1_PDM0_PCLK_EN>;
clock-names = "mclk", "pclk";
power-domains = <&power_peri1>;
power-domains = <&power_top>;
#sound-dai-cells = <1>;
zhihe,peri1-sys = <&peri1_sys>;
zhihe,mode = "pdm-master";
@@ -1577,7 +1585,7 @@
interrupts = <339>;
clocks = <&clk_peri PERI1_PDM0_MCLK_EN>, <&clk_peri PERI1_PDM0_PCLK_EN>;
clock-names = "mclk", "pclk";
power-domains = <&power_peri1>;
power-domains = <&power_top>;
#sound-dai-cells = <1>;
zhihe,peri1-sys = <&peri1_sys>;
zhihe,mode = "pdm-master";
@@ -1593,7 +1601,7 @@
interrupts = <339>;
clocks = <&clk_peri PERI1_PDM0_MCLK_EN>, <&clk_peri PERI1_PDM0_PCLK_EN>;
clock-names = "mclk", "pclk";
power-domains = <&power_peri1>;
power-domains = <&power_top>;
#sound-dai-cells = <1>;
zhihe,peri1-sys = <&peri1_sys>;
zhihe,mode = "pdm-master";
@@ -1609,7 +1617,7 @@
interrupts = <339>;
clocks = <&clk_peri PERI1_PDM0_MCLK_EN>, <&clk_peri PERI1_PDM0_PCLK_EN>;
clock-names = "mclk", "pclk";
power-domains = <&power_peri1>;
power-domains = <&power_top>;
#sound-dai-cells = <1>;
zhihe,peri1-sys = <&peri1_sys>;
zhihe,mode = "pdm-master";
@@ -1625,7 +1633,7 @@
interrupts = <339>;
clocks = <&clk_peri PERI1_PDM0_MCLK_EN>, <&clk_peri PERI1_PDM0_PCLK_EN>;
clock-names = "mclk", "pclk";
power-domains = <&power_peri1>;
power-domains = <&power_top>;
#sound-dai-cells = <1>;
zhihe,peri1-sys = <&peri1_sys>;
zhihe,mode = "pdm-master";
@@ -1747,6 +1755,7 @@
reg-names = "interrupt_addr",
"local_addr0",
"remote_icu0";
resets = <&rst PERI0_MBOX0_PRST>, <&rst PERI0_MBOX1_PRST>;
interrupt-parent = <&intc>;
interrupts = <336 IRQ_TYPE_LEVEL_HIGH>;
icu_cpu_id = <0>;
@@ -1828,7 +1837,7 @@
interrupts = <204>, <235>, <66>, <223>, <344>, <174>, <187>;
power-domains = <&power_vi_isp>, <&power_venc>, <&power_vdec>, <&power_npu_ip>,
<&power_vo>, <&power_pcie0>, <&power_pcie1>, <&power_usb>,
<&power_peri1>;
<&power_top>;
#iommu-cells = <1>;
};

11
drivers/mailbox/zhihe-mailbox.c
View File

@@ -16,6 +16,7 @@
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/slab.h>
#include <linux/reset.h>
#define ZHIHE_MBOX_V1 0x0
#define ZHIHE_MBOX_V2 0x1
@@ -100,6 +101,7 @@ struct zhihe_mbox_priv {
struct zhihe_mbox_con_priv con_priv[ZHIHE_MBOX_CHANS];
struct clk *clk;
struct reset_control *reset;
int irq;
int version;
#ifdef CONFIG_PM_SLEEP
@@ -569,6 +571,15 @@ static int zhihe_mbox_probe(struct platform_device *pdev)
dev_err(dev, "Failed to enable clock\n");
return ret;
}
priv->reset = of_reset_control_array_get_optional_exclusive(np);
if (IS_ERR(priv->reset)) {
dev_err(dev, "failed to get reset return %ld\n", PTR_ERR(priv->reset));
return PTR_ERR(priv->reset);
}
reset_control_assert(priv->reset);
reset_control_deassert(priv->reset);
/* init the chans */
if (priv->version == ZHIHE_MBOX_V1) {
for (i = 0; i < ZHIHE_MBOX_CHANS; i++) {

2
drivers/reset/reset-a210.c
View File

@@ -170,6 +170,8 @@ static const struct a210_rst_signal peri0_rst_signals[] = {
[PERI0_WDT0_PRST & RST_SIGNAL_MASK] = {0, BIT(4)},
[PERI0_MBOX0_PRST & RST_SIGNAL_MASK] = {0, BIT(5)},
[PERI0_MBOX1_PRST & RST_SIGNAL_MASK] = {0, BIT(6)},
[PERI0_TIMER0_RST & RST_SIGNAL_MASK] = {0, BIT(0) | BIT(1)},
[PERI0_TIMER1_RST & RST_SIGNAL_MASK] = {0, BIT(2) | BIT(3)},
};
static const struct a210_rst_signal peri1_rst_signals[] = {

2
include/dt-bindings/reset/a210-reset.h
View File

@@ -119,6 +119,8 @@
#define PERI0_WDT0_PRST 0x404
#define PERI0_MBOX0_PRST 0x405
#define PERI0_MBOX1_PRST 0x406
#define PERI0_TIMER0_RST 0x407
#define PERI0_TIMER1_RST 0x408
#define PERI1_GMAC0_ARST 0x500
#define PERI1_GMAC0_HRST 0x501