OERV-BSP/kernel-zhihe-a210
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Release develop 260130

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This commit is contained in:
hongyi
2026-01-30 17:09:03 +08:00
parent b56f19ed96
commit 006816cce1
31 changed files with 668 additions and 243 deletions
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161
arch/riscv/boot/dts/zhihe/a210-dev.dts
View File

@@ -1,6 +1,8 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/usb/pd.h>
#include <dt-bindings/input/linux-event-codes.h>
#include "a210-soc-core.dtsi"
#include "a210-soc-peri.dtsi"
#include "a210-platform-dev.dtsi"
@@ -219,6 +221,26 @@
AVDD2-supply = <&avdd2_mipicsi1_reg>;
status = "okay";
};
reg_usb_typec_vbus: regulator-typec-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_typec_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio0 27 GPIO_ACTIVE_HIGH>;
enable-active-high;
status = "okay";
};
gpio-keys {
compatible = "gpio-keys";
key-sleep {
label = "KEY_SLEEP";
linux,code = <KEY_SLEEP>;
debounce-interval = <1>;
gpios = <&ao_gpio0 1 GPIO_ACTIVE_LOW>;
};
};
};
&ao_gpio0 {
@@ -422,6 +444,17 @@
slew-rate = <0>;
};
};
usbc0_int: usbc0-int {
usbcc-int-pins {
pins = "AOGPIO0_28";
function = "aogpio0";
bias-pull-up;
drive-strength = <13>;
input-enable;
input-schmitt-enable; /* 启用施密特触发器以稳定低电平中断信号 */
slew-rate = <0>;
};
};
};
&peri1_padctrl {
@@ -562,17 +595,6 @@
slew-rate = <0>;
};
};
usb3_pins: usb3-1 {
usb3-pins {
pins = "GPIO0_27";
function = "gpio0";
bias-disable;
drive-strength = <13>;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
};
};
&peri2_padctrl {
@@ -771,14 +793,14 @@
cs-gpios = <&gpio0 19 0>;
rx-sample-dly = <2>;
spi-swap-data = <1>;
spi-max-frequency = <55000000>;
spi-max-frequency = <42000000>;
pinctrl-names = "default";
pinctrl-0 = <&qspi0_pins>;
status = "disabled";
spi_norflash@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <55000000>;
spi-max-frequency = <42000000>;
#address-cells = <1>;
#size-cells = <1>;
spi-tx-bus-width = <4>;
@@ -970,6 +992,65 @@
"USBCON_PWREN_IO8", "USBCON1_PWREN_IO9", "NULL_IO10", "SDIO_3V3_PWREN_IO11", // index 8..11
"SDIO_1V8_PWREN_IO12","PI6C557_PWREN_IO13","MIPI_DSI_PWREN_IO14","BL_EN_IO15"; // index 12..15
};
fusb302: typec-portc@22 {
compatible = "fcs,fusb302";
reg = <0x22>;
interrupt-parent = <&ao_gpio0>;
interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&usbc0_int>;
vbus-supply = <&reg_usb_typec_vbus>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usbc0_role_sw: endpoint@0 {
remote-endpoint = <&dwc3_0_role_switch>;
};
};
};
connector {
compatible = "usb-c-connector";
label = "USB-C";
data-role = "dual";
power-role = "dual";
try-power-role = "sink";
op-sink-microwatt = <1000000>;
sink-pdos =
<PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>;
source-pdos =
<PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
altmodes {
#address-cells = <1>;
#size-cells = <0>;
altmode@0 {
reg = <0>;
svid = <0xff01>;
vdo = <0xffffffff>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usbc0_orien_sw: endpoint {
remote-endpoint = <&usbdp_phy0_orientation_switch>;
};
};
};
};
};
};
&uart4 {
@@ -1068,12 +1149,6 @@
pwren-gpios = <&aw9535_1 9 GPIO_ACTIVE_HIGH>;
};
&usb3 {
pinctrl-names = "default";
pinctrl-0 = <&usb3_pins>;
typec-pwren-gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>;
};
&sata {
status = "okay";
};
@@ -1103,21 +1178,11 @@
};
//config dsi display: dpu_disp0->dup_enc0->dsi0->lcd_plane
&dpu_enc0 {
status = "okay";
ports {
/* output */
port@1 {
reg = <1>;
enc0_out: endpoint {
remote-endpoint = <&dsi0_in>;
};
};
};
&dsi_enc_out {
remote-endpoint = <&dsi0_in>;
};
&dhost_0 {
&dsi_host0 {
status = "okay";
ports {
#address-cells = <1>;
@@ -1125,7 +1190,7 @@
port@0 {
reg = <0>;
dsi0_in: endpoint {
remote-endpoint = <&enc0_out>;
remote-endpoint = <&dsi_enc_out>;
};
};
port@1 {
@@ -1188,3 +1253,33 @@
&gpu {
dvdd-supply = <&dvdd_gpu_reg>;
};
&usb3 {
dr_mode = "otg";
usb-role-switch;
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
dwc3_0_role_switch: endpoint@0 {
reg = <0>;
remote-endpoint = <&usbc0_role_sw>;
};
};
};
/* USB3.1/DP Combo PHY0 */
&usb31_c10phy {
orientation-switch;
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
usbdp_phy0_orientation_switch: endpoint@0 {
reg = <0>;
remote-endpoint = <&usbc0_orien_sw>;
};
};
};

2
arch/riscv/boot/dts/zhihe/a210-emu.dts
View File

@@ -70,7 +70,7 @@
};
&clk {
compatible = "zhihe,p100-clk-emu";
compatible = "zhihe,a210-clk-emu";
};
&vidmem {

16
arch/riscv/boot/dts/zhihe/a210-evb-d2d.dts
View File

@@ -245,13 +245,13 @@
cs-gpios = <&gpio0 19 0>;
rx-sample-dly = <2>;
spi-swap-data = <1>;
spi-max-frequency = <55000000>;
spi-max-frequency = <42000000>;
pinctrl-names = "default";
pinctrl-0 = <&qspi0_pins>;
spi_norflash@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <55000000>;
spi-max-frequency = <42000000>;
#address-cells = <1>;
#size-cells = <1>;
spi-tx-bus-width = <4>;
@@ -265,13 +265,13 @@
cs-gpios = <&gpio2 29 0>;
rx-sample-dly = <2>;
spi-swap-data = <1>;
spi-max-frequency = <55000000>;
spi-max-frequency = <42000000>;
pinctrl-names = "default";
pinctrl-0 = <&qspi1_pins>;
spi_norflash@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <55000000>;
spi-max-frequency = <42000000>;
#address-cells = <1>;
#size-cells = <1>;
spi-tx-bus-width = <4>;
@@ -373,13 +373,13 @@
cs-gpios = <&gpio0_die1 19 0>;
rx-sample-dly = <2>;
spi-swap-data = <1>;
spi-max-frequency = <55000000>;
spi-max-frequency = <42000000>;
pinctrl-names = "default";
pinctrl-0 = <&qspi0_pins_die1>;
spi_norflash@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <55000000>;
spi-max-frequency = <42000000>;
#address-cells = <1>;
#size-cells = <1>;
spi-tx-bus-width = <4>;
@@ -393,13 +393,13 @@
cs-gpios = <&gpio2_die1 29 0>;
rx-sample-dly = <2>;
spi-swap-data = <1>;
spi-max-frequency = <55000000>;
spi-max-frequency = <42000000>;
pinctrl-names = "default";
pinctrl-0 = <&qspi1_pins_die1>;
spi_norflash@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <55000000>;
spi-max-frequency = <42000000>;
#address-cells = <1>;
#size-cells = <1>;
spi-tx-bus-width = <4>;

33
arch/riscv/boot/dts/zhihe/a210-evb.dts
View File

@@ -1044,11 +1044,11 @@
&spi0 {
cs-gpios = <&gpio0 30 0>;
rx-sample-delay-ns = <4>;
spi-max-frequency = <55000000>;
spi-max-frequency = <42000000>;
spi_norflash@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <55000000>;
spi-max-frequency = <42000000>;
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
@@ -1059,13 +1059,13 @@
&spi1 {
cs-gpios = <&gpio2 18 0>;
rx-sample-delay-ns = <4>;
spi-max-frequency = <55000000>;
spi-max-frequency = <42000000>;
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins>;
spi_norflash@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <55000000>;
spi-max-frequency = <42000000>;
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
@@ -1077,13 +1077,13 @@
cs-gpios = <&gpio0 19 0>;
rx-sample-dly = <2>;
spi-swap-data = <1>;
spi-max-frequency = <55000000>;
spi-max-frequency = <42000000>;
pinctrl-names = "default";
pinctrl-0 = <&qspi0_pins>;
spi_norflash@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <55000000>;
spi-max-frequency = <42000000>;
#address-cells = <1>;
#size-cells = <1>;
spi-tx-bus-width = <4>;
@@ -1097,13 +1097,13 @@
cs-gpios = <&gpio2 29 0>;
rx-sample-dly = <2>;
spi-swap-data = <1>;
spi-max-frequency = <55000000>;
spi-max-frequency = <42000000>;
pinctrl-names = "default";
pinctrl-0 = <&qspi1_pins>;
spi_norflash@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <55000000>;
spi-max-frequency = <42000000>;
#address-cells = <1>;
#size-cells = <1>;
spi-tx-bus-width = <4>;
@@ -1647,20 +1647,11 @@
};
//config dsi display: auxdisp->enc0->dsi0->lcd_lt8819_plane
&dpu_enc0 {
status = "okay";
ports {
/* output */
port@1 {
reg = <1>;
enc0_out: endpoint {
remote-endpoint = <&dsi0_in>;
};
};
};
&dsi_enc_out {
remote-endpoint = <&dsi0_in>;
};
&dhost_0 {
&dsi_host0 {
status = "okay";
ports {
#address-cells = <1>;
@@ -1668,7 +1659,7 @@
port@0 {
reg = <0>;
dsi0_in: endpoint {
remote-endpoint = <&enc0_out>;
remote-endpoint = <&dsi_enc_out>;
};
};
port@1 {

2
arch/riscv/boot/dts/zhihe/a210-haps.dts
View File

@@ -201,7 +201,7 @@
};
&clk {
compatible = "zhihe,p100-clk-haps";
compatible = "zhihe,a210-clk-haps";
/* pll */
audio0_pll_foutvco_frequency = <150000000>;
audio1_pll_foutvco_frequency = <80000000>;

10
arch/riscv/boot/dts/zhihe/a210-platform-d2d.dtsi
View File

@@ -270,7 +270,7 @@
status = "disabled";
};
&dhost_0 {
&dsi_host0 {
status = "disabled";
};
@@ -318,3 +318,11 @@
&uart4_die1 {
status = "disabled";
};
&auxdisp {
status = "disabled";
};
&dpu_enc0 {
status = "disabled";
};

8
arch/riscv/boot/dts/zhihe/a210-platform-dev.dtsi
View File

@@ -106,6 +106,14 @@
status = "okay";
};
&auxdisp {
status = "disabled";
};
&dpu_enc0 {
status = "disabled";
};
&audio_i2s0 {
status = "disabled";
};

8
arch/riscv/boot/dts/zhihe/a210-platform-emu.dtsi
View File

@@ -262,6 +262,14 @@
status = "disabled";
};
&auxdisp {
status = "disabled";
};
&dpu_enc0 {
status = "disabled";
};
&audio_i2s0 {
status = "disabled";
};

8
arch/riscv/boot/dts/zhihe/a210-platform-evb.dtsi
View File

@@ -175,6 +175,14 @@
status = "disabled";
};
&auxdisp {
status = "disabled";
};
&dpu_enc0 {
status = "disabled";
};
&audio_i2s0 {
status = "disabled";
};

8
arch/riscv/boot/dts/zhihe/a210-platform-haps.dtsi
View File

@@ -186,6 +186,14 @@
status = "disabled";
};
&auxdisp {
status = "disabled";
};
&dpu_enc0 {
status = "disabled";
};
&clk_gpu {
status = "disabled";
};

2
arch/riscv/boot/dts/zhihe/a210-sec-tee.dtsi
View File

@@ -1,7 +1,7 @@
//sec-tee.dtsi
/ {
//compatible = "zhihe,p100,tee";//update dst compatible value for tee
//compatible = "zhihe,a210,tee";//update dst compatible value for tee
chosen {
opensbi-domains {
compatible = "opensbi,domain,config";

24
arch/riscv/boot/dts/zhihe/a210-soc-core.dtsi
View File

@@ -496,28 +496,6 @@
entry-cnt = <4 4>; /* The number of CPUs in each cluster */
control-reg = <0x00 0x10144004 0x00 0x10144008>;/* SWRST C908 C920*/
control-val = <0x1f 0x1f>; /* bit0:clust, bit1~4:core0~core3 */
csr-init = < /* 0x00 0x00, Magic New Cluster start */
0x00 0x00 /* Cluster0 init CSR Register */
0x00 0x7c5 0x00 0x212A10C /* mhint*/
0x01 0x7cc 0x02 0x00000000 /* mhint2 bit33: When the CPU hangs, it is possible to obtain the CPU's internal context register through jtag */
0x01 0x7cd 0x00 0x06 /* mhint3 bit1~2: Fix the stuttering issue on multi-core processors*/
0x01 0x7ce 0x00 0x00002000 /* mhint4 bit13:enabled L2 cache free write to reduce L2 miss latency, bit7,28: enable cpu wirte-evict function o enable cpu to write clean data to LLC(L3) 0x10002080*/
0x00 0x7c3 0x00 0xA2490008 /* mccr2 */
0x00 0x7f3 0x00 0x01 /* msmpr(smpen) */
0x00 0x7c1 0x00 0x10011FF /* mhcr */
0x00 0x7c0 0x00 0x438000 /* mxstatus CONFIG_STD_SVPBMT */
0x00 0x30a 0x40000000 0x00000000 /* menvcfg PBMTE=1 */
0x00 0x00 /* Cluster1 init CSR Register */
0x00 0x7c5 0x00 0x316A32C /* mhint*/
0x00 0x7cc 0x1000 0x00000180 /* mhint2*/
0x01 0x7cd 0x00 0x06 /* mhint3 bit1~2: Fix the stuttering issue on multi-core processors*/
0x01 0x7ce 0x00 0x00002000 /* mhint4 bit13:enabled L2 cache free write to reduce L2 miss latency, bit7,28: enable cpu wirte-evict function o enable cpu to write clean data to LLC(L3) 0x10002080*/
0x00 0x7c3 0x00 0xE2490009 /* mccr2 */
0x00 0x7f3 0x00 0x01 /* msmpr */
0x00 0x7c1 0x00 0x11FF /* mhcr */
0x00 0x7c0 0x00 0x438000 /* mxstatus CONFIG_STD_SVPBMT */
0x00 0x30a 0x40000000 0x00000000 /* menvcfg PBMTE=1 */
>;
};
clint0: clint@001c000000 {
@@ -915,7 +893,7 @@
};
rst: reset-controller {
compatible = "zhihe,p100-reset-controller";
compatible = "zhihe,a210-reset-controller";
reg = <0x00 0x06B20400 0x0 0x200>,
<0x00 0x063A0400 0x0 0x200>,
<0x00 0x07112200 0x0 0x10>,

48
arch/riscv/boot/dts/zhihe/a210-soc-peri.dtsi
View File

@@ -19,17 +19,23 @@
/* default encoder is DSI. */
compatible = "verisilicon,dsi-encoder";
reg = <0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
/* input */
port@0 {
reg = <0>;
enc0_in: endpoint {
dsi_enc_in: endpoint {
remote-endpoint = <&auxdisp_to_dsi>;
};
};
/* output */
port@1 {
reg = <1>;
dsi_enc_out: endpoint {
// remote-endpoint = <&dsi0_in>;
};
};
};
};
};
@@ -91,7 +97,7 @@
};
nvmem_controller: efuse@0027410000 {
compatible = "zhihe,p100-fm-efuse", "syscon";
compatible = "zhihe,a210-fm-efuse", "syscon";
reg = <0x00 0x27410000 0x0 0x10000>;
zhihe,teesys = <&teesys_syscon>;
#address-cells = <1>;
@@ -124,7 +130,7 @@
#phy-cells = <0>;
};
dhost_0: dsi0-host {
dsi_host0: dsi0-host {
compatible = "verisilicon,dw-mipi-dsi";
regmap = <&dsi0>;
interrupt-parent = <&intc>;
@@ -267,7 +273,7 @@
auxdisp_out: port@0 {
reg = <0>;
auxdisp_to_dsi: endpoint@0 {
remote-endpoint = <&enc0_in>;
remote-endpoint = <&dsi_enc_in>;
};
};
};
@@ -363,7 +369,7 @@
};
dmac0: dmac@0000520000 {
compatible = "zhihe,p100-axi-dma";
compatible = "zhihe,a210-axi-dma";
reg = <0x00 0x00520000 0x0 0x4000>;
interrupt-parent = <&intc>;
interrupts = <264>;
@@ -382,7 +388,7 @@
};
dmac1: tee_dmac@27540000 {
compatible = "zhihe,p100-axi-dma";
compatible = "zhihe,a210-axi-dma";
reg = <0x00 0x27540000 0x0 0x4000>;
interrupt-parent = <&intc>;
interrupts = <259>;
@@ -638,7 +644,7 @@
};
gmac0: ethernet@0002100000{
compatible = "zhihe,p100-dwmac", "snps,dwmac-5.40a";
compatible = "zhihe,a210-dwmac", "snps,dwmac-5.40a";
reg = <0x00 0x02100000 0x0 0x10000>;
reg-names = "gmac";
interrupt-parent = <&intc>;
@@ -663,7 +669,7 @@
};
gmac1: ethernet@02110000 {
compatible = "zhihe,p100-dwmac", "snps,dwmac-5.40a";
compatible = "zhihe,a210-dwmac", "snps,dwmac-5.40a";
reg = <0x00 0x02110000 0x0 0x10000>;
reg-names = "gmac";
interrupt-parent = <&intc>;
@@ -1369,14 +1375,16 @@
#sound-dai-cells = <1>;
zhihe,peri1-sys = <&peri1_sys>;
dmas = <&dmac0 13>;
dma-names = "rx";
};
usb31_c10phy: phy@8040000 {
compatible = "zhihe,a210-c10phy";
reg = <0x00 0x08040000 0x0 0x3C000>,
<0x00 0x0807C000 0x0 0x2000>,
<0x00 0x0807E000 0x0 0x2000>;
reg-names = "phy_ctrl", "tca", "sysreg";
<0x00 0x0807E000 0x0 0x100>,
<0x00 0x08014000 0x0 0x200>;
reg-names = "phy_ctrl", "tca", "sysreg", "dptx_sys";
resets = <&rst USB_C10PHY_PHY_RST>;
reset-names = "phy-rst";
#phy-cells = <0>;
@@ -2063,7 +2071,7 @@
};
bmu0: ddr-bmu@0004850000 {
compatible = "zhihe,p100-ddr-bmu";
compatible = "zhihe,a210-ddr-bmu";
reg = <0x00 0x04850000 0x0 0x10000>,
<0x00 0x05850000 0x0 0x10000>;
zhihe,bm-num = <2>;
@@ -2073,7 +2081,7 @@
};
bmu1: gpu-bmu@0006d14000 {
compatible = "zhihe,p100-gpu-bmu";
compatible = "zhihe,a210-gpu-bmu";
reg = <0x00 0x06d14000 0x0 0x400>;
zhihe,bm-num = <1>;
zhihe,bm-name ="bmu_gpu";
@@ -2083,7 +2091,7 @@
};
bmu2: npu-bmu@0007104000 {
compatible = "zhihe,p100-npu-bmu";
compatible = "zhihe,a210-npu-bmu";
reg = <0x00 0x07104000 0x0 0x400>;
zhihe,bm-num = <1>;
zhihe,bm-name ="bmu_npu";
@@ -2093,7 +2101,7 @@
};
bmu3: pcie-bmu@000a014000 {
compatible = "zhihe,p100-pcie-bmu";
compatible = "zhihe,a210-pcie-bmu";
reg = <0x00 0x0a014000 0x0 0x400>;
zhihe,bm-num = <1>;
zhihe,bm-name ="bmu_pcie";
@@ -2111,7 +2119,7 @@
};
bmu5: vo-bmu@0006714000 {
compatible = "zhihe,p100-vo-bmu";
compatible = "zhihe,a210-vo-bmu";
reg = <0x00 0x06714000 0x0 0x400>;
zhihe,bm-num = <1>;
zhihe,bm-name ="bmu_vo";
@@ -2121,7 +2129,7 @@
};
bmu6: vi-bmu@0006374000 {
compatible = "zhihe,p100-vi-bmu";
compatible = "zhihe,a210-vi-bmu";
reg = <0x00 0x06374000 0x0 0x400>;
zhihe,bm-num = <1>;
zhihe,bm-name ="bmu_vi";
@@ -2131,7 +2139,7 @@
};
bmu7: vp-bmu@0006b14000 {
compatible = "zhihe,p100-vp-bmu";
compatible = "zhihe,a210-vp-bmu";
reg = <0x00 0x06b14000 0x0 0x400>;
zhihe,bm-num = <1>;
zhihe,bm-name ="bmu_vp";
@@ -2141,7 +2149,7 @@
};
bmu8: peri-bmu@0002034000 {
compatible = "zhihe,p100-peri-bmu";
compatible = "zhihe,a210-peri-bmu";
reg = <0x00 0x02034000 0x0 0x400>;
zhihe,bm-num = <1>;
zhihe,bm-name ="bmu_peri";
@@ -2150,7 +2158,7 @@
};
bmu9: d2d-bmu@0009034000 {
compatible = "zhihe,p100-d2d-bmu";
compatible = "zhihe,a210-d2d-bmu";
reg = <0x00 0x09034000 0x0 0x400>;
zhihe,bm-num = <1>;
zhihe,bm-name ="bmu_d2d";

4
arch/riscv/boot/dts/zhihe/a210-som-v1.dts
View File

@@ -508,13 +508,13 @@
cs-gpios = <&gpio0 19 0>;
rx-sample-dly = <2>;
spi-swap-data = <1>;
spi-max-frequency = <55000000>;
spi-max-frequency = <42000000>;
pinctrl-names = "default";
pinctrl-0 = <&qspi0_pins>;
spi_norflash@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <55000000>;
spi-max-frequency = <42000000>;
#address-cells = <1>;
#size-cells = <1>;
spi-tx-bus-width = <4>;

2
arch/riscv/boot/dts/zhihe/a210-usb-aistick.dts
View File

@@ -621,7 +621,7 @@
status = "disabled";
};
&dhost_0 {
&dsi_host0 {
status = "disabled";
};

1
arch/riscv/kernel/smpboot.c
View File

@@ -239,6 +239,7 @@ asmlinkage __visible void smp_callin(void)
mmgrab(mm);
current->active_mm = mm;
rcu_cpu_starting(curr_cpuid);
store_cpu_topology(curr_cpuid);
notify_cpu_starting(curr_cpuid);

6
drivers/clk/zhihe/clk-a210.c
View File

@@ -12,7 +12,6 @@
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_address.h>
#include <linux/pm_runtime.h>
#include <linux/types.h>
#include <dt-bindings/clock/a210-clock.h>
@@ -982,9 +981,6 @@ static int a210_clocks_probe(struct platform_device *pdev)
struct zhihe_clk_subsys *priv;
int ret;
pm_runtime_enable(dev);
pm_runtime_get_sync(dev);
struct clk_onecell_data *clk_data = devm_kzalloc(dev, sizeof(*clk_data), GFP_KERNEL);
if (!clk_data) {
ret = -ENOMEM;
@@ -1028,13 +1024,11 @@ static int a210_clocks_probe(struct platform_device *pdev)
}
dev_info(dev, "succeed to register a210 %s driver on die%d\n", priv->name, priv->die_num);
pm_runtime_put_sync(dev);
return 0;
unregister_clks:
zhihe_unregister_clocks(priv->clk_data->clks, CLK_END);
fail:
pm_runtime_put_sync(dev);
return ret;
}

4
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
View File

@@ -616,7 +616,7 @@ static void set_desc_dest_master(struct axi_dma_hw_desc *hw_desc,
* dma_burst_len_to_enum - Convert burst length value to AXI DMA burst length enum
* @burst_len: Burst length value to convert
*
* This function maps a numeric burst length value to the corresponding
* This function maps a numeric burst length value to the corresponding
* DWAXIDMAC_BURST_TRANS_LEN_* enumeration constant used in the DesignWare AXI DMA controller.
*
* Return:
@@ -1728,7 +1728,7 @@ static const struct of_device_id dw_dma_of_id_table[] = {
.compatible = "xuantie,th1520-axi-dma",
.data = (void *)(AXI_DMA_FLAG_USE_CFG2),
}, {
.compatible = "zhihe,p100-axi-dma",
.compatible = "zhihe,a210-axi-dma",
.data = (void *)(AXI_DMA_FLAG_USE_CFG2),
},
{}

12
drivers/gpio/gpio-dwapb.c
View File

@@ -283,13 +283,15 @@ static void dwapb_irq_enable(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
unsigned long flags;
u32 val;
raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
val = dwapb_read(gpio, GPIO_INTEN);
val |= BIT(irqd_to_hwirq(d));
val = dwapb_read(gpio, GPIO_INTEN) | BIT(hwirq);
dwapb_write(gpio, GPIO_INTEN, val);
val = dwapb_read(gpio, GPIO_INTMASK) & ~BIT(hwirq);
dwapb_write(gpio, GPIO_INTMASK, val);
raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
}
@@ -297,12 +299,14 @@ static void dwapb_irq_disable(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
unsigned long flags;
u32 val;
raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
val = dwapb_read(gpio, GPIO_INTEN);
val &= ~BIT(irqd_to_hwirq(d));
val = dwapb_read(gpio, GPIO_INTMASK) | BIT(hwirq);
dwapb_write(gpio, GPIO_INTMASK, val);
val = dwapb_read(gpio, GPIO_INTEN) & ~BIT(hwirq);
dwapb_write(gpio, GPIO_INTEN, val);
raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
}

15
drivers/gpu/drm/panel/panel-lt8911.c
View File

@@ -505,6 +505,9 @@ static int panel_prepare(struct drm_panel *panel)
DBG_FUNC("lt8911exb enter\n");
if (md->prepared)
return 0;
if (g_is_std_suspend) {
DBG_FUNC("lt8911exb prepare under std mode, do not prepare\n");
return 0;
@@ -540,9 +543,12 @@ static int panel_prepare(struct drm_panel *panel)
lt8911_i2c_read(client, 0x01),
lt8911_i2c_read(client, 0x02));
md->prepared = true;
return 0;
fail:
dev_err(&md->client->dev, "lt8911exb prepare failed: %d\n", ret);
if (gpio_is_valid(md->reset_pin))
gpio_set_value(md->reset_pin, 0);
if (md->hsvcc)
@@ -557,6 +563,9 @@ static int panel_unprepare(struct drm_panel *panel)
int ret = 0;
struct i2c_mipi_dsi *md = panel_to_md(panel);
if (!md->prepared)
return 0;
DBG_FUNC("panel_unprepare enter\n");
if (gpio_is_valid(md->reset_pin))
gpio_set_value(md->reset_pin, 0);
@@ -566,6 +575,7 @@ static int panel_unprepare(struct drm_panel *panel)
if (md->vspn3v3)
regulator_disable(md->vspn3v3);
md->prepared = false;
return ret;
}
@@ -649,6 +659,11 @@ static int backlight_update(struct backlight_device *bd)
struct i2c_mipi_dsi *md = bl_get_data(bd);
int brightness = bd->props.brightness;
if (!md->prepared) {
dev_dbg(&bd->dev, "lcd not ready yet for setting its backlight!\n");
return -ENXIO;
}
if (bd->props.power != FB_BLANK_UNBLANK ||
bd->props.fb_blank != FB_BLANK_UNBLANK ||
(bd->props.state & (BL_CORE_SUSPENDED | BL_CORE_FBBLANK))) {

1
drivers/gpu/drm/panel/panel-lt8911.h
View File

@@ -82,6 +82,7 @@ struct i2c_mipi_dsi {
// backlight
int brightness;
bool prepared;
};
#define panel_to_md(_p) container_of(_p, struct i2c_mipi_dsi, panel)

82
drivers/gpu/drm/verisilicon/auxdisp_crtc.c
View File

@@ -182,6 +182,7 @@ struct auxdisp_crtc {
struct clk *aclk; /* AXI 总线时钟 */
struct clk *pclk; /* APB 配置时钟 */
struct clk *pixclk; /* 像素时钟 */
struct clk *current_pixclk; /* 当前使用的像素时钟 */
struct clk *hdmi_pixclk; /* HDMI 输出像素时钟 */
struct clk *mipi_pixclk; /* MIPI 输出像素时钟 */
struct clk *dptx_pixclk; /* DPTX 输出像素时钟 */
@@ -524,7 +525,6 @@ static void auxdisp_configure_timing(struct auxdisp_crtc *auxdisp)
static int auxdisp_configure_clocks(struct auxdisp_crtc *auxdisp, unsigned long pixel_clock_hz)
{
int ret;
ret = clk_set_rate(auxdisp->pixclk, pixel_clock_hz);
if (ret) {
dev_err(auxdisp->dev, "Failed to set pixel clock rate: %d\n", ret);
@@ -636,42 +636,16 @@ static void auxdisp_crtc_disable(struct drm_crtc *crtc,
struct drm_atomic_state *state)
{
struct auxdisp_crtc *auxdisp = to_auxdisp_crtc(crtc);
u32 idle_status;
int timeout = 100;
auxdisp_write(auxdisp, AUXDISP_INT_ENABLE, 0);
auxdisp_write(auxdisp, AUXDISP_EN, 0);
auxdisp->display_enabled = false;
auxdisp_write(auxdisp, AUXDISP_ABNORMAL_CTRL, AUXDISP_ABNORMAL_STOP);
while (timeout--) {
idle_status = auxdisp_read(auxdisp, AUXDISP_IDLE);
if (idle_status & 0x1) {
break;
}
usleep_range(100, 200);
}
auxdisp_write(auxdisp, AUXDISP_ABNORMAL_CTRL, 0);
auxdisp_write(auxdisp, AUXDISP_ABNORMAL_CTRL, AUXDISP_ABNORMAL_RESET);
usleep_range(10, 20);
auxdisp_write(auxdisp, AUXDISP_ABNORMAL_CTRL, 0);
auxdisp_write(auxdisp, AUXDISP_INT_CLEAR, 0xFFFFFFFF);
auxdisp_write(auxdisp, AUXDISP_CFG_DONE, 1);
auxdisp->pending_timing.valid = false;
auxdisp->pending_timing.fb_configured = false;
drm_crtc_vblank_off(crtc);
if (__clk_is_enabled(auxdisp->pixclk))
clk_disable_unprepare(auxdisp->pixclk);
spin_lock_irq(&crtc->dev->event_lock);
if (crtc->state->event && !crtc->state->active) {
drm_crtc_send_vblank_event(crtc, crtc->state->event);
@@ -703,12 +677,12 @@ static void auxdisp_set_display_path(struct drm_crtc *crtc, struct drm_atomic_st
default:
return;
}
if (!output_clk) {
auxdisp->current_pixclk = output_clk;
if (auxdisp->current_pixclk == NULL) {
return;
}
ret = clk_set_parent(output_clk, auxdisp->pixclk);
ret = clk_set_parent(auxdisp->current_pixclk, auxdisp->pixclk);
if (ret) {
dev_err(auxdisp->dev, "Failed to set %s clock parent: %d\n", if_name, ret);;
}
@@ -925,7 +899,7 @@ static void auxdisp_plane_atomic_update(struct drm_plane *plane,
if (!fb || !new_state->crtc)
return;
mutex_lock(&auxdisp->config_lock);
mutex_lock(&auxdisp->config_lock);
initial_config_done = auxdisp->pending_timing.fb_configured &&
(auxdisp->pending_timing.fb_width == fb->width) &&
(auxdisp->pending_timing.fb_height == fb->height) &&
@@ -996,7 +970,7 @@ static void auxdisp_plane_atomic_update(struct drm_plane *plane,
}
end:
mutex_unlock(&auxdisp->config_lock);
mutex_unlock(&auxdisp->config_lock);
}
static const struct drm_plane_helper_funcs auxdisp_plane_helper_funcs = {
@@ -1067,7 +1041,7 @@ static void auxdisp_crtc_unbind(struct device *dev, struct device *master, void
if (!auxdisp->bound)
return;
mutex_lock(&auxdisp->config_lock);
mutex_lock(&auxdisp->config_lock);
if (auxdisp->crtc.port) {
of_node_put(auxdisp->crtc.port);
auxdisp->crtc.port = NULL;
@@ -1075,7 +1049,7 @@ static void auxdisp_crtc_unbind(struct device *dev, struct device *master, void
auxdisp->bound = false;
auxdisp->drm_dev = NULL;
mutex_unlock(&auxdisp->config_lock);
mutex_unlock(&auxdisp->config_lock);
}
static const struct component_ops auxdisp_crtc_component_ops = {
@@ -1207,8 +1181,6 @@ MODULE_DEVICE_TABLE(of, auxdisp_crtc_dt_ids);
static int auxdisp_crtc_suspend(struct device *dev)
{
struct auxdisp_crtc *auxdisp = dev_get_drvdata(dev);
u32 idle_status;
int timeout = 100;
if (!auxdisp || !auxdisp->bound) {
return 0;
@@ -1228,23 +1200,6 @@ static int auxdisp_crtc_suspend(struct device *dev)
auxdisp_write(auxdisp, AUXDISP_EN, 0);
auxdisp->display_enabled = false;
auxdisp_write(auxdisp, AUXDISP_ABNORMAL_CTRL, AUXDISP_ABNORMAL_STOP);
while (timeout--) {
idle_status = auxdisp_read(auxdisp, AUXDISP_IDLE);
if (idle_status & 0x1) {
break;
}
usleep_range(100, 200);
}
auxdisp_write(auxdisp, AUXDISP_ABNORMAL_CTRL, 0);
auxdisp_write(auxdisp, AUXDISP_ABNORMAL_CTRL, AUXDISP_ABNORMAL_RESET);
usleep_range(10, 20);
auxdisp_write(auxdisp, AUXDISP_ABNORMAL_CTRL, 0);
auxdisp_write(auxdisp, AUXDISP_INT_CLEAR, 0xFFFFFFFF);
if (__clk_is_enabled(auxdisp->pixclk))
@@ -1272,11 +1227,10 @@ static int auxdisp_crtc_runtime_suspend(struct device *dev)
{
struct auxdisp_crtc *auxdisp = dev_get_drvdata(dev);
if (!auxdisp)
return 0;
if (auxdisp->current_pixclk) {
clk_disable_unprepare(auxdisp->current_pixclk);
}
clk_disable_unprepare(auxdisp->pclk);
clk_disable_unprepare(auxdisp->aclk);
return 0;
@@ -1286,10 +1240,6 @@ static int auxdisp_crtc_runtime_resume(struct device *dev)
{
struct auxdisp_crtc *auxdisp = dev_get_drvdata(dev);
int ret;
if (!auxdisp)
return 0;
ret = clk_prepare_enable(auxdisp->aclk);
if (ret) {
dev_err(dev, "Failed to enable aclk in runtime resume: %d\n", ret);
@@ -1302,7 +1252,15 @@ static int auxdisp_crtc_runtime_resume(struct device *dev)
clk_disable_unprepare(auxdisp->aclk);
return ret;
}
if (auxdisp->current_pixclk) {
ret = clk_prepare_enable(auxdisp->current_pixclk);
if (ret) {
dev_err(dev, "Failed to enable current_pixclk in runtime resume: %d\n", ret);
clk_disable_unprepare(auxdisp->pclk);
clk_disable_unprepare(auxdisp->aclk);
return ret;
}
}
return 0;
}
static const struct dev_pm_ops auxdisp_crtc_pm_ops = {

25
drivers/iommu/riscv/iommu-platform.c
View File

@@ -59,6 +59,22 @@ static int riscv_iommu_platform_probe(struct platform_device *pdev)
}
}
/*
* Get and prepare clocks early, before any hardware access.
* Do NOT use pm_runtime_get_sync() before this, as it may trigger power
* domain operations that themselves need to prepare clocks, causing
* circular locking: prepare_lock → genpd_runtime_resume → genpd->mlock
* → a210_pd_power_on → clk_prepare → prepare_lock (deadlock).
*/
iommus->num_clks = devm_clk_bulk_get_all(dev, &iommus->clks);
if (iommus->num_clks < 0)
return dev_err_probe(dev, iommus->num_clks,
"Failed to get iommus's clocks\n");
ret = clk_bulk_prepare_enable(iommus->num_clks, iommus->clks);
if (ret)
return ret;
pm_runtime_enable(dev);
pm_runtime_get_sync(dev);
@@ -145,15 +161,6 @@ static int riscv_iommu_platform_probe(struct platform_device *pdev)
list_add_tail(&iommu->list, &iommus->iommus);
}
iommus->num_clks = devm_clk_bulk_get_all(dev, &iommus->clks);
if (iommus->num_clks < 0)
return dev_err_probe(dev, iommus->num_clks,
"Failed to get iommus's clocks\n");
ret = clk_bulk_prepare_enable(iommus->num_clks, iommus->clks);
if (ret)
return ret;
dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
riscv_iommu_register(iommus);

4
drivers/net/ethernet/stmicro/stmmac/dwmac-zhihe.c
View File

@@ -206,7 +206,7 @@ int zhihe_dwmac_clk_enable(struct platform_device *pdev, void *bsp_priv)
int zhihe_dwmac_clk_init(struct platform_device *pdev, void *bsp_priv)
{
struct zhihe_dwmac_priv_data *zhihe_plat_dat = bsp_priv;
struct zhihe_dwmac_priv_data *zhihe_plat_dat = bsp_priv;
struct device *dev = &pdev->dev;
int ret = 0;
unsigned int reg = 0;
@@ -475,7 +475,7 @@ static struct zhihe_dwmac_ops zhihe_dwmac_data = {
};
static const struct of_device_id zhihe_dwmac_match[] = {
{ .compatible = "zhihe,p100-dwmac", .data = &zhihe_dwmac_data },
{ .compatible = "zhihe,a210-dwmac", .data = &zhihe_dwmac_data },
{}
};
MODULE_DEVICE_TABLE(of, zhihe_dwmac_match);

4
drivers/nvme/host/pci.c
View File

@@ -370,7 +370,7 @@ static bool nvme_dbbuf_update_and_check_event(u16 value, __le32 *dbbuf_db,
* ordering to ensure the envent index is updated before reading
* the doorbell.
*/
mb();
dma_mb();
event_idx = le32_to_cpu(*dbbuf_ei);
if (!nvme_dbbuf_need_event(event_idx, value, old_value))
@@ -858,7 +858,7 @@ static blk_status_t nvme_prep_rq(struct nvme_dev *dev, struct request *req)
if (ret)
goto out_unmap_data;
}
dma_mb();
nvme_start_request(req);
return BLK_STS_OK;
out_unmap_data:

10
drivers/nvmem/zh-efuse.c
View File

@@ -1139,7 +1139,7 @@ static const struct attribute_group dev_attr_efuse_sysfs_group = {
};
static const struct of_device_id zh_efuse_of_match[] = {
{.compatible = "zhihe,p100-fm-efuse"},
{.compatible = "zhihe,a210-fm-efuse"},
{ /* sentinel */},
};
MODULE_DEVICE_TABLE(of, zh_efuse_of_match);
@@ -1165,7 +1165,7 @@ static int __maybe_unused zh_efuse_runtime_suspend(struct device *dev)
dev_dbg(dev, "[%s,%d] ret = %d, pd status: 0x%lx\n", __func__, __LINE__, ret,
readl(priv->base + CON) & EFUSE_CON_POWER_MSK);
clk_disable_unprepare(priv->clk);
return ret;
@@ -1183,7 +1183,7 @@ static int __maybe_unused zh_efuse_runtime_resume(struct device *dev)
dev_err(dev, "failed to get efuse clk\n");
return ret;
}
return efuse_poweron(priv->base);
}
@@ -1208,7 +1208,7 @@ static int __maybe_unused zh_efuse_suspend(struct device *dev)
dev_dbg(dev, "[%s,%d] ret = %d, pd status: 0x%lx\n", __func__, __LINE__, ret,
readl(priv->base + CON) & EFUSE_CON_POWER_MSK);
clk_disable_unprepare(priv->clk);
return ret;
@@ -1226,7 +1226,7 @@ static int __maybe_unused zh_efuse_resume(struct device *dev)
dev_err(dev, "failed to get efuse clk\n");
return ret;
}
return efuse_poweron(priv->base);
}

328
drivers/phy/zhihe/phy-zhihe-snps-c10phy.c
View File

@@ -3,6 +3,7 @@
* phy-zhihe_c10phy.c - ZHIHE C10PHY USB3.1 PHY driver
*/
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
@@ -14,41 +15,219 @@
#include <linux/platform_device.h>
#include <linux/reset.h>
#include <linux/slab.h>
#include <linux/mutex.h>
#include <linux/regulator/consumer.h>
#include <linux/gpio/consumer.h>
/* C10PHY TCA registers (Base: 0x807C000) */
#define TCA_INTR_EN 0x4
#define TCA_INTR_STS 0x8
#define TCA_TCPC 0x14
#include <linux/usb/typec_mux.h>
#include <linux/usb/typec_dp.h>
#include <linux/gpio/consumer.h>
#include <linux/extcon-provider.h>
#include <linux/usb/role.h>
#include <linux/sysfs.h>
#include <linux/kobject.h>
/* Base DWC3 Control Register */
#define DWC3_LCSR_TX_DEEMPH_2 0xd068
/*
* DPTX_SYS Register Offsets - From soc sys databook
*/
#define DPTX_CTRL 0x00
#define DPTX_LSFR_CTRL 0x10
#define DPTX_LSFR_SEED 0x14
#define DPTX_MTN_LINK 0x20
#define DPTX_AUX_CTRL 0x40
#define DPTX_DBG0 0x100
#define DPTX_DBG1 0x104
/* DPTX_AUX_CTRL bits*/
#define AUX_DP_DN_SWAP BIT(8)
/*
* TCA Register Offsets - From Databook Section 3.2 (Page 36)
* These are VERIFIED from the databook
*/
#define TCA_CLK_RST 0x00
#define TCA_CLK_RST_SW BIT(9)
#define TCA_CLK_RST_REF_CLK_EN BIT(1)
#define TCA_CLK_RST_SUSPEND_CLK_EN BIT(0)
#define TCA_INTR_EN 0x04
#define TCA_INTR_STS 0x08
#define TCA_GCFG 0x10
#define TCA_GCFG_ROLE_HSTDEV BIT(4)
#define TCA_GCFG_OP_MODE GENMASK(1, 0)
#define TCA_GCFG_OP_MODE_SYSMODE 0
#define TCA_GCFG_OP_MODE_SYNCMODE 1
#define TCA_TCPC 0x14
#define TCA_TCPC_VALID BIT(4)
#define TCA_TCPC_LOW_POWER_EN BIT(3)
#define TCA_TCPC_ORIENTATION_NORMAL BIT(2)
#define TCA_TCPC_MUX_CONTRL GENMASK(1, 0)
#define TCA_TCPC_MUX_CONTRL_NO_CONN 0
#define TCA_TCPC_MUX_CONTRL_USB_CONN 1
#define TCA_SYSMODE_CFG 0x18
#define TCA_SYSMODE_TCPC_DISABLE BIT(3)
#define TCA_SYSMODE_TCPC_FLIP BIT(2)
#define TCA_CTRLSYNCMODE_CFG0 0x20
#define TCA_CTRLSYNCMODE_CFG1 0x20
#define TCA_PSTATE 0x30
#define TCA_PSTATE_CM_STS BIT(4)
#define TCA_PSTATE_TX_STS BIT(3)
#define TCA_PSTATE_RX_PLL_STS BIT(2)
#define TCA_PSTATE_PIPE0_POWER_DOWN GENMASK(1, 0)
#define TCA_GEN_STATUS 0x34
#define TCA_GEN_DEV_POR BIT(12)
#define TCA_GEN_REF_CLK_SEL BIT(8)
#define TCA_GEN_TYPEC_FLIP_INVERT BIT(4)
#define TCA_GEN_PHY_TYPEC_DISABLE BIT(3)
#define TCA_GEN_PHY_TYPEC_FLIP BIT(2)
#define TCA_VBUS_CTRL 0x40
#define TCA_VBUS_STATUS 0x44
#define TCA_INFO 0xfc
/* PHY Operation Modes - Custom flags for internal use */
#define PHY_MODE_DISABLED 0
#define PHY_MODE_USB3 BIT(0)
#define PHY_MODE_DP_CUSTOM BIT(1)
#define PHY_MODE_USB3_DP (BIT(0) | BIT(1))
struct zhihe_c10phy_priv {
struct device *dev;
struct phy *phy;
void __iomem *phy_ctrl_base;
void __iomem *tca_base;
void __iomem *sysreg_base;
void __iomem *dptxsys_base;
struct reset_control *c10phy_rst;
enum typec_orientation orientation; /* Type-C orientation */
/* GPIO for AUX control */
struct gpio_desc *aux_p_gpio; /* AUX_P pull-down control */
struct gpio_desc *aux_n_gpio; /* AUX_N pull-up control */
enum usb_role usb_role; /* Current USB role: host or device */
struct typec_switch_dev *sw;
struct mutex lock;
};
static void tca_blk_orientation_set(struct zhihe_c10phy_priv *priv,
enum typec_orientation orientation);
static int tca_blk_typec_switch_set(struct typec_switch_dev *sw,
enum typec_orientation orientation)
{
struct zhihe_c10phy_priv *priv = typec_switch_get_drvdata(sw);
if (priv->orientation == orientation)
return 0;
tca_blk_orientation_set(priv, orientation);
return 0;
}
static void tca_blk_orientation_set(struct zhihe_c10phy_priv *priv,
enum typec_orientation orientation)
{
u32 val;
mutex_lock(&priv->lock);
if (orientation == TYPEC_ORIENTATION_NONE) {
/*
* use Controller Synced Mode for TCA low power enable and
* put PHY to USB safe state.
*/
val = FIELD_PREP(TCA_GCFG_OP_MODE, TCA_GCFG_OP_MODE_SYNCMODE);
writel(val, priv->tca_base + TCA_GCFG);
val = TCA_TCPC_VALID | TCA_TCPC_LOW_POWER_EN;
writel(val, priv->tca_base + TCA_TCPC);
goto out;
}
/* use System Configuration Mode for TCA mux control. */
val = FIELD_PREP(TCA_GCFG_OP_MODE, TCA_GCFG_OP_MODE_SYSMODE);
writel(val, priv->tca_base + TCA_GCFG);
/* Disable TCA module */
val = readl(priv->tca_base + TCA_SYSMODE_CFG);
val |= TCA_SYSMODE_TCPC_DISABLE;
writel(val, priv->tca_base + TCA_SYSMODE_CFG);
if (orientation == TYPEC_ORIENTATION_REVERSE)
val |= TCA_SYSMODE_TCPC_FLIP;
else if (orientation == TYPEC_ORIENTATION_NORMAL)
val &= ~TCA_SYSMODE_TCPC_FLIP;
writel(val, priv->tca_base + TCA_SYSMODE_CFG);
/* Enable TCA module */
val &= ~TCA_SYSMODE_TCPC_DISABLE;
writel(val, priv->tca_base + TCA_SYSMODE_CFG);
out:
priv->orientation = orientation;
mutex_unlock(&priv->lock);
}
static void tca_blk_init(struct zhihe_c10phy_priv *priv)
{
u32 val;
/* reset XBar block */
val = readl(priv->tca_base + TCA_CLK_RST);
val &= ~TCA_CLK_RST_SW;
writel(val, priv->tca_base + TCA_CLK_RST);
udelay(100);
/* clear reset */
val |= TCA_CLK_RST_SW;
writel(val, priv->tca_base + TCA_CLK_RST);
tca_blk_orientation_set(priv, priv->orientation);
}
/* Setup Type-C orientation switch */
static int zhihe_setup_typec_switch(struct zhihe_c10phy_priv *priv)
{
struct typec_switch_desc sw_desc = {};
sw_desc.drvdata = priv;
sw_desc.fwnode = dev_fwnode(priv->dev);
sw_desc.set = tca_blk_typec_switch_set;
sw_desc.name = NULL;
priv->sw = typec_switch_register(priv->dev, &sw_desc);
if (IS_ERR(priv->sw)) {
dev_err(priv->dev, "Failed to register typec switch: %ld\n", PTR_ERR(priv->sw));
return PTR_ERR(priv->sw);
}
return 0;
}
static void zhihe_switch_unregister(void *data)
{
struct zhihe_c10phy_priv *priv = data;
typec_switch_unregister(priv->sw);
}
static int c10phy_init(struct phy *phy)
{
struct zhihe_c10phy_priv *priv = phy_get_drvdata(phy);
/* Deassert resets */
reset_control_deassert(priv->c10phy_rst);
/* Configure PHY control registers */
writel(0x3d0, priv->phy_ctrl_base + 0x3c);
writel(0x10540, priv->phy_ctrl_base + DWC3_LCSR_TX_DEEMPH_2);
/* Configure TCA (Type-C Adapter) */
writel(0x11, priv->tca_base + TCA_TCPC);
writel(0xffff, priv->tca_base + TCA_INTR_STS);
/* Assert resets to complete initialization sequence */
tca_blk_init(priv);
reset_control_assert(priv->c10phy_rst);
return 0;
@@ -71,8 +250,68 @@ static const struct phy_ops c10phy_ops = {
.owner = THIS_MODULE,
};
/* Sysfs attribute for orientation control */
static ssize_t orientation_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct phy *phy = dev_get_drvdata(dev);
struct zhihe_c10phy_priv *priv = phy_get_drvdata(phy);
const char *orientation_str;
switch (priv->orientation) {
case TYPEC_ORIENTATION_NONE:
orientation_str = "none";
break;
case TYPEC_ORIENTATION_NORMAL:
orientation_str = "normal";
break;
case TYPEC_ORIENTATION_REVERSE:
orientation_str = "reverse";
break;
default:
orientation_str = "unknown";
break;
}
return sprintf(buf, "%s\n", orientation_str);
}
static ssize_t orientation_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct phy *phy = dev_get_drvdata(dev);
struct zhihe_c10phy_priv *priv = phy_get_drvdata(phy);
enum typec_orientation orientation;
if (sysfs_streq(buf, "none"))
orientation = TYPEC_ORIENTATION_NONE;
else if (sysfs_streq(buf, "normal"))
orientation = TYPEC_ORIENTATION_NORMAL;
else if (sysfs_streq(buf, "reverse"))
orientation = TYPEC_ORIENTATION_REVERSE;
else
return -EINVAL;
tca_blk_orientation_set(priv, orientation);
return count;
}
static DEVICE_ATTR_RW(orientation);
static struct attribute *c10phy_attrs[] = {
&dev_attr_orientation.attr,
NULL,
};
static const struct attribute_group c10phy_attr_group = {
.attrs = c10phy_attrs,
};
static int c10phy_probe(struct platform_device *pdev)
{
int ret = 0;
struct device *dev = &pdev->dev;
struct zhihe_c10phy_priv *priv;
struct phy_provider *phy_provider;
@@ -84,6 +323,7 @@ static int c10phy_probe(struct platform_device *pdev)
priv->dev = dev;
platform_set_drvdata(pdev, priv);
priv->usb_role = USB_ROLE_HOST; /* Default to host mode, can be changed dynamically */
/* Get TCA register base */
priv->tca_base = devm_platform_ioremap_resource_byname(pdev, "tca");
if (IS_ERR(priv->tca_base))
@@ -102,11 +342,50 @@ static int c10phy_probe(struct platform_device *pdev)
return dev_err_probe(dev, PTR_ERR(priv->sysreg_base),
"Couldn't get SYSREG register base\n");
/* Get dptx SYSREG register base */
priv->dptxsys_base = devm_platform_ioremap_resource_byname(pdev, "dptx_sys");
if (IS_ERR(priv->sysreg_base))
return dev_err_probe(dev, PTR_ERR(priv->sysreg_base),
"Couldn't get SYSREG register base\n");
priv->c10phy_rst = devm_reset_control_get_shared(dev, "phy-rst");
if (IS_ERR(priv->c10phy_rst))
return dev_err_probe(dev, PTR_ERR(priv->c10phy_rst),
"Couldn't get phy-rst\n");
/* Get GPIO for AUX control (optional) */
priv->aux_p_gpio = devm_gpiod_get_optional(dev, "aux-p", GPIOD_OUT_LOW);
if (IS_ERR(priv->aux_p_gpio)) {
dev_err(dev, "Failed to get AUX_P GPIO\n");
return PTR_ERR(priv->aux_p_gpio);
}
if (priv->aux_p_gpio)
dev_info(dev, "AUX_P GPIO configured for pull-down control\n");
priv->aux_n_gpio = devm_gpiod_get_optional(dev, "aux-n", GPIOD_OUT_HIGH);
if (IS_ERR(priv->aux_n_gpio)) {
dev_err(dev, "Failed to get AUX_N GPIO\n");
return PTR_ERR(priv->aux_n_gpio);
}
if (priv->aux_n_gpio)
dev_info(dev, "AUX_N GPIO configured for pull-up control\n");
/* Setup Type-C support if enabled */
if (device_property_present(dev, "orientation-switch")) {
ret = zhihe_setup_typec_switch(priv);
if (ret) {
return ret;
}
ret = devm_add_action_or_reset(dev, zhihe_switch_unregister, priv);
if (ret)
return ret;
}
priv->orientation = TYPEC_ORIENTATION_NORMAL;
mutex_init(&priv->lock);
/* Create PHY */
priv->phy = devm_phy_create(dev, NULL, &c10phy_ops);
if (IS_ERR(priv->phy))
@@ -122,6 +401,22 @@ static int c10phy_probe(struct platform_device *pdev)
return dev_err_probe(dev, PTR_ERR(phy_provider),
"failed to register phy provider\n");
/* Create sysfs attribute for orientation control */
ret = sysfs_create_group(&dev->kobj, &c10phy_attr_group);
if (ret) {
dev_err(dev, "Failed to create sysfs group: %d\n", ret);
return ret;
}
return 0;
}
static int c10phy_remove(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
sysfs_remove_group(&dev->kobj, &c10phy_attr_group);
return 0;
}
@@ -133,6 +428,7 @@ MODULE_DEVICE_TABLE(of, c10phy_of_match);
static struct platform_driver c10phy_driver = {
.probe = c10phy_probe,
.remove = c10phy_remove,
.driver = {
.name = "phy-zhihe-a210-c10phy",
.of_match_table = c10phy_of_match,

4
drivers/reset/reset-a210.c
View File

@@ -605,14 +605,14 @@ fail:
}
static const struct of_device_id a210_reset_of_match[] = {
{.compatible = "zhihe,p100-reset-controller"},
{.compatible = "zhihe,a210-reset-controller"},
{ /* Sentinel */ },
};
struct platform_driver a210_reset_driver = {
.probe = a210_reset_probe,
.driver = {
.name = "p100-reset",
.name = "a210-reset",
.of_match_table = of_match_ptr(a210_reset_of_match),
},
};

18
drivers/soc/zhihe/a210-bmu.c
View File

@@ -974,19 +974,19 @@ static struct bmu3_para bmu3_para_data[] = {
static const struct of_device_id a210_bmu_dt_ids[] = {
{
.compatible = "zhihe,p100-ddr-bmu",
.compatible = "zhihe,a210-ddr-bmu",
.data = &bmu3_para_data[BMU_DDR],
},
{
.compatible = "zhihe,p100-gpu-bmu",
.compatible = "zhihe,a210-gpu-bmu",
.data = &bmu3_para_data[BMU_GPU],
},
{
.compatible = "zhihe,p100-npu-bmu",
.compatible = "zhihe,a210-npu-bmu",
.data = &bmu3_para_data[BMU_NPU],
},
{
.compatible = "zhihe,p100-pcie-bmu",
.compatible = "zhihe,a210-pcie-bmu",
.data = &bmu3_para_data[BMU_PCIE],
},
{
@@ -994,23 +994,23 @@ static const struct of_device_id a210_bmu_dt_ids[] = {
.data = &bmu3_para_data[BMU_USB],
},
{
.compatible = "zhihe,p100-vo-bmu",
.compatible = "zhihe,a210-vo-bmu",
.data = &bmu3_para_data[BMU_VO],
},
{
.compatible = "zhihe,p100-vi-bmu",
.compatible = "zhihe,a210-vi-bmu",
.data = &bmu3_para_data[BMU_VI],
},
{
.compatible = "zhihe,p100-vp-bmu",
.compatible = "zhihe,a210-vp-bmu",
.data = &bmu3_para_data[BMU_VP],
},
{
.compatible = "zhihe,p100-peri-bmu",
.compatible = "zhihe,a210-peri-bmu",
.data = &bmu3_para_data[BMU_PERI],
},
{
.compatible = "zhihe,p100-d2d-bmu",
.compatible = "zhihe,a210-d2d-bmu",
.data = &bmu3_para_data[BMU_D2D],
},
};

58
drivers/usb/dwc3/dwc3-zhihe.c
View File

@@ -19,6 +19,7 @@
#include <linux/reset.h>
#include <linux/of_address.h>
#include <linux/gpio/consumer.h>
#include <linux/pm_runtime.h>
#include "core.h"
@@ -26,7 +27,6 @@ struct dwc3_zhihe {
struct device *dev;
struct regmap *usb31_sysreg;
struct reset_control *usb31_arst;
struct gpio_desc *pwren;
struct platform_device *dwc3;
struct platform_device *usb20_phy;
struct clk_bulk_data *clks;
@@ -76,27 +76,30 @@ static int dwc3_zhihe_probe(struct platform_device *pdev)
if (!zhihe->dwc3)
return dev_err_probe(dev, -ENODEV, "failed to get dwc3 platform device\n");
zhihe->pwren = devm_gpiod_get_optional(&pdev->dev, "typec-pwren", GPIOD_OUT_LOW);
if (IS_ERR(zhihe->pwren))
zhihe->pwren = NULL;
else if (zhihe->pwren)
gpiod_set_value(zhihe->pwren, 1);
else
dev_info(dev, "Type-C power enable GPIO not defined in device tree\n");
ret = clk_bulk_prepare_enable(zhihe->num_clocks, zhihe->clks);
if (ret)
return dev_err_probe(dev, ret, "failed to enable DWC3 bulk clks\n");
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
pm_runtime_get_noresume(dev);
return 0;
}
static int dwc3_zhihe_remove(struct platform_device *pdev)
{
struct dwc3_zhihe *zhihe = platform_get_drvdata(pdev);
struct device *dev = &pdev->dev;
of_platform_depopulate(zhihe->dev);
pm_runtime_put_sync(dev);
pm_runtime_disable(dev);
pm_runtime_set_suspended(dev);
clk_bulk_disable_unprepare(zhihe->num_clocks, zhihe->clks);
return 0;
}
@@ -106,11 +109,48 @@ static const struct of_device_id dwc3_zhihe_of_match[] = {
};
MODULE_DEVICE_TABLE(of, dwc3_zhihe_of_match);
#ifdef CONFIG_PM
static int __maybe_unused dwc3_zhihe_suspend(struct device *dev)
{
/* Keep clocks enabled, do nothing */
return 0;
}
static int __maybe_unused dwc3_zhihe_resume(struct device *dev)
{
/* Clocks already enabled, do nothing */
return 0;
}
static int __maybe_unused dwc3_zhihe_runtime_suspend(struct device *dev)
{
/* Keep clocks enabled, do nothing */
return 0;
}
static int __maybe_unused dwc3_zhihe_runtime_resume(struct device *dev)
{
/* Clocks already enabled, do nothing */
return 0;
}
static const struct dev_pm_ops dwc3_zhihe_dev_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(dwc3_zhihe_suspend, dwc3_zhihe_resume)
SET_RUNTIME_PM_OPS(dwc3_zhihe_runtime_suspend,
dwc3_zhihe_runtime_resume, NULL)
};
#define DEV_PM_OPS (&dwc3_zhihe_dev_pm_ops)
#else
#define DEV_PM_OPS NULL
#endif /* CONFIG_PM */
static struct platform_driver dwc3_zhihe_driver = {
.probe = dwc3_zhihe_probe,
.remove = dwc3_zhihe_remove,
.driver = {
.name = "dwc3-zhihe",
.pm = DEV_PM_OPS,
.of_match_table = dwc3_zhihe_of_match,
},
};

3
drivers/usb/typec/tcpm/tcpm.c
View File

@@ -3727,9 +3727,6 @@ static void tcpm_detach(struct tcpm_port *port)
if (tcpm_port_is_disconnected(port))
port->hard_reset_count = 0;
port->try_src_count = 0;
port->try_snk_count = 0;
if (!port->attached)
return;