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@@ -519,26 +519,26 @@ static void th1520_set_uhs_signaling(struct sdhci_host *host,
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* - center phase select code driven in block gap interval
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* - disable reporting of framing errors
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* - disable software managed tuning
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* - disable sampling window threshold
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* Choose largest sampling window tuning schema, do not care AT_CTRL_SWIN_TH_VAL
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* - disable user selection of sampling window edges,
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* instead tuning calculated edges are used
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*/
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val = sdhci_readl(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
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val &= ~(AT_CTRL_CI_SEL | AT_CTRL_RPT_TUNE_ERR | AT_CTRL_SW_TUNE_EN |
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FIELD_PREP(AT_CTRL_WIN_EDGE_SEL_MASK, AT_CTRL_WIN_EDGE_SEL));
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val &= ~(AT_CTRL_CI_SEL | AT_CTRL_RPT_TUNE_ERR | AT_CTRL_SW_TUNE_EN | AT_CTRL_SWIN_TH_EN |
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AT_CTRL_WIN_EDGE_SEL_MASK | AT_CTRL_SWIN_TH_VAL_MASK);
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/*
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* Configure tuning settings:
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* - enable auto-tuning
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* - enable sampling window threshold
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* - stop clocks during phase code change
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* - set max latency in cycles between tx and rx clocks
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* - set max latency in cycles to switch output phase
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* - set max sampling window threshold value
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*/
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val |= AT_CTRL_AT_EN | AT_CTRL_SWIN_TH_EN | AT_CTRL_TUNE_CLK_STOP_EN;
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val |= AT_CTRL_AT_EN | AT_CTRL_TUNE_CLK_STOP_EN;
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val |= FIELD_PREP(AT_CTRL_PRE_CHANGE_DLY_MASK, AT_CTRL_PRE_CHANGE_DLY);
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val |= FIELD_PREP(AT_CTRL_POST_CHANGE_DLY_MASK, AT_CTRL_POST_CHANGE_DLY);
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val |= FIELD_PREP(AT_CTRL_SWIN_TH_VAL_MASK, AT_CTRL_SWIN_TH_VAL);
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sdhci_writel(host, val, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
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/* Update tx delay */
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