OERV-BSP/kernel-zhihe-a210
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Release develop 260120

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hongyi
2026-01-20 10:49:13 +08:00
parent 7a3477fcec
commit b56f19ed96
5 changed files with 6 additions and 9 deletions
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1
arch/riscv/boot/dts/zhihe/a210-dev.dts
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@@ -1041,7 +1041,6 @@
pull_up; pull_up;
bus-width = <8>; bus-width = <8>;
cap-mmc-highspeed; cap-mmc-highspeed;
clk-delay-mmc-hs200 = <60>;
}; };
&sdhci0 { &sdhci0 {

1
arch/riscv/boot/dts/zhihe/a210-evb.dts
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@@ -1379,7 +1379,6 @@
pull_up; pull_up;
bus-width = <8>; bus-width = <8>;
cap-mmc-highspeed; cap-mmc-highspeed;
clk-delay-mmc-hs200 = <60>;
}; };
&sdhci0 { &sdhci0 {

2
arch/riscv/boot/dts/zhihe/a210-soc-peri.dtsi
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@@ -602,7 +602,7 @@
clock-names = "core", "bus"; clock-names = "core", "bus";
power-domains = <&power_peri3>; power-domains = <&power_peri3>;
//iommus = <&iommu DEVID_DIE0_EMMC>; //iommus = <&iommu DEVID_DIE0_EMMC>;
clk-delay-mmc-hs200 = <45>; clk-delay-mmc-hs200 = <50>;
clk-delay-mmc-hs400 = <24>; clk-delay-mmc-hs400 = <24>;
}; };

1
arch/riscv/boot/dts/zhihe/a210-usb-aistick.dts
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@@ -578,7 +578,6 @@
pull_up; pull_up;
bus-width = <8>; bus-width = <8>;
cap-mmc-highspeed; cap-mmc-highspeed;
clk-delay-mmc-hs200 = <60>;
}; };
&sdhci0 { &sdhci0 {

10
drivers/mmc/host/sdhci-of-dwcmshc.c
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@@ -519,26 +519,26 @@ static void th1520_set_uhs_signaling(struct sdhci_host *host,
* - center phase select code driven in block gap interval * - center phase select code driven in block gap interval
* - disable reporting of framing errors * - disable reporting of framing errors
* - disable software managed tuning * - disable software managed tuning
* - disable sampling window threshold
* Choose largest sampling window tuning schema, do not care AT_CTRL_SWIN_TH_VAL
* - disable user selection of sampling window edges, * - disable user selection of sampling window edges,
* instead tuning calculated edges are used * instead tuning calculated edges are used
*/ */
val = sdhci_readl(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); val = sdhci_readl(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
val &= ~(AT_CTRL_CI_SEL | AT_CTRL_RPT_TUNE_ERR | AT_CTRL_SW_TUNE_EN | val &= ~(AT_CTRL_CI_SEL | AT_CTRL_RPT_TUNE_ERR | AT_CTRL_SW_TUNE_EN | AT_CTRL_SWIN_TH_EN |
FIELD_PREP(AT_CTRL_WIN_EDGE_SEL_MASK, AT_CTRL_WIN_EDGE_SEL)); AT_CTRL_WIN_EDGE_SEL_MASK | AT_CTRL_SWIN_TH_VAL_MASK);
/* /*
* Configure tuning settings: * Configure tuning settings:
* - enable auto-tuning * - enable auto-tuning
* - enable sampling window threshold
* - stop clocks during phase code change * - stop clocks during phase code change
* - set max latency in cycles between tx and rx clocks * - set max latency in cycles between tx and rx clocks
* - set max latency in cycles to switch output phase * - set max latency in cycles to switch output phase
* - set max sampling window threshold value * - set max sampling window threshold value
*/ */
val |= AT_CTRL_AT_EN | AT_CTRL_SWIN_TH_EN | AT_CTRL_TUNE_CLK_STOP_EN; val |= AT_CTRL_AT_EN | AT_CTRL_TUNE_CLK_STOP_EN;
val |= FIELD_PREP(AT_CTRL_PRE_CHANGE_DLY_MASK, AT_CTRL_PRE_CHANGE_DLY); val |= FIELD_PREP(AT_CTRL_PRE_CHANGE_DLY_MASK, AT_CTRL_PRE_CHANGE_DLY);
val |= FIELD_PREP(AT_CTRL_POST_CHANGE_DLY_MASK, AT_CTRL_POST_CHANGE_DLY); val |= FIELD_PREP(AT_CTRL_POST_CHANGE_DLY_MASK, AT_CTRL_POST_CHANGE_DLY);
val |= FIELD_PREP(AT_CTRL_SWIN_TH_VAL_MASK, AT_CTRL_SWIN_TH_VAL);
sdhci_writel(host, val, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); sdhci_writel(host, val, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
/* Update tx delay */ /* Update tx delay */