OERV-BSP/kernel-zhihe-a210
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Release develop 251227

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hongyi
2025-12-27 14:21:38 +08:00
parent ca4f09cd41
commit 8add2b4251
3 changed files with 10 additions and 10 deletions
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4
arch/riscv/boot/dts/zhihe/a210-dev.dts
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@@ -67,7 +67,7 @@
pcie3x4 = &dm3x4;
pcie3x1 = &rp3x1;
vi_sensor0 = &mipicsi0_4lane_port;
vi_sensor1 = &mipicsi1_a_port;
vi_sensor1 = &mipi1csi1_a_port;
};
/* The actual capacity will be adjusted through SPL */
@@ -203,7 +203,7 @@
status = "okay";
};
mipicsi1_a_port: mipicsi1_a_port@0 {
mipi1csi1_a_port: mipi1csi1_a_port@0 {
compatible = "zhihe,vi_sensor";
clocks = <&clk SW_TOP_PAD_SENSOR_VCLK1_EN>;
clock-names = "core_clk";

8
arch/riscv/boot/dts/zhihe/a210-evb.dts
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@@ -262,17 +262,17 @@
mipi1csi0_b_port: mipi1csi0_b_port@0 {
compatible = "zhihe,vi_sensor";
clocks = <&clk SW_TOP_PAD_SENSOR_VCLK1_EN>;
clock-names = "core_clk";
clock-frequency = <24000000>;
pinctrl-names = "default";
pinctrl-0 = <&sen_vclk_pin1>;
status = "okay";
};
mipi1csi1_a_port: mipi1csi1_a_port@0 {
compatible = "zhihe,vi_sensor";
clocks = <&clk SW_TOP_PAD_SENSOR_VCLK1_EN>;
clock-names = "core_clk";
clock-frequency = <24000000>;
pinctrl-names = "default";
pinctrl-0 = <&sen_vclk_pin1>;
status = "okay";
};
};

8
arch/riscv/boot/dts/zhihe/a210-soc-peri.dtsi
View File

@@ -1182,8 +1182,8 @@
interrupt-parent = <&intc>;
interrupts = <229>, <231>;
power-domains = <&power_vdec>;
clocks = <&clk_vp VP_VDEC_CCLK_EN>, <&clk_vp VP_VDEC_ACLK_EN>;
clock-names = "vdec_cclk", "vp_aclk";
clocks = <&clk_vp VP_VDEC_CCLK_EN>, <&clk_vp VP_VDEC_ACLK_EN>, <&clk_vp VP_VDEC_PCLK_EN>;
clock-names = "vdec_cclk", "vp_aclk", "vdec_pclk";
operating-points-v2 = <&vdec_opp_table>;
aclk-freq-low = <528000000>;
aclk-freq-high = <880000000>;
@@ -1200,8 +1200,8 @@
interrupt-parent = <&intc>;
interrupts = <230>, <350>;
power-domains = <&power_venc>;
clocks = <&clk_vp VP_VENC_CCLK_EN>, <&clk_vp VP_VENC_ACLK_EN>;
clock-names = "venc_cclk", "vp_aclk";
clocks = <&clk_vp VP_VENC_CCLK_EN>, <&clk_vp VP_VENC_ACLK_EN>, <&clk_vp VP_VENC_PCLK_EN>;
clock-names = "venc_cclk", "vp_aclk", "venc_pclk";
operating-points-v2 = <&venc_opp_table>;
aclk-freq-low = <528000000>;
aclk-freq-high = <880000000>;