OERV-BSP/kernel-zhihe-a210
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Release develop 251226

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This commit is contained in:
hongyi
2025-12-26 11:41:00 +08:00
parent e31acb1b2d
commit ca4f09cd41
2 changed files with 56 additions and 12 deletions
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46
arch/riscv/boot/dts/zhihe/a210-evb.dts
View File

@@ -60,6 +60,9 @@
spi3 = &spi1;
pcie3x4 = &dm3x4;
pcie3x1 = &rp3x1;
vi_sensor0 = &mipicsi0_4lane_port;
vi_sensor1 = &mipi1csi0_b_port;
vi_sensor2 = &mipi1csi1_a_port;
};
/* The actual capacity will be adjusted through SPL */
@@ -246,6 +249,32 @@
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
};
mipicsi0_4lane_port: mipicsi0_4lane_port@0 {
compatible = "zhihe,vi_sensor";
clocks = <&clk SW_TOP_PAD_SENSOR_VCLK0_EN>;
clock-names = "core_clk";
clock-frequency = <24000000>;
pinctrl-names = "default";
pinctrl-0 = <&sen_vclk_pin0>;
status = "okay";
};
mipi1csi0_b_port: mipi1csi0_b_port@0 {
compatible = "zhihe,vi_sensor";
clocks = <&clk SW_TOP_PAD_SENSOR_VCLK1_EN>;
clock-names = "core_clk";
clock-frequency = <24000000>;
pinctrl-names = "default";
pinctrl-0 = <&sen_vclk_pin1>;
status = "okay";
};
mipi1csi1_a_port: mipi1csi1_a_port@0 {
compatible = "zhihe,vi_sensor";
clock-frequency = <24000000>;
status = "okay";
};
};
&peri1_padctrl {
@@ -869,9 +898,20 @@
slew-rate = <0>;
};
};
sen_vclk_pins: sen_vclk-1 {
sen_vclk-pins {
pins = "GPIO3_0", "GPIO3_1";
sen_vclk_pin0: sen_vclk0 {
sen_vclk0-pins {
pins = "GPIO3_0";
function = "sen_vclk";
bias-disable;
drive-strength = <7>;
input-enable;
input-schmitt-enable;
slew-rate = <0>;
};
};
sen_vclk_pin1: sen_vclk1 {
sen_vclk1-pins {
pins = "GPIO3_1";
function = "sen_vclk";
bias-disable;
drive-strength = <7>;

22
arch/riscv/boot/dts/zhihe/a210-soc-peri.dtsi
View File

@@ -49,11 +49,11 @@
opp00 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <750000>;
opp-microvolt = <750000 750000 800000>;
};
opp01 {
opp-hz = /bits/ 64 <786432000>;
opp-microvolt = <800000>;
opp-microvolt = <800000 750000 800000>;
};
};
@@ -62,11 +62,11 @@
opp00 {
opp-hz = /bits/ 64 <528000000>;
opp-microvolt = <750000>;
opp-microvolt = <750000 750000 800000>;
};
opp01 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <800000>;
opp-microvolt = <800000 750000 800000>;
};
};
@@ -75,11 +75,13 @@
opp00 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <750000>;
aclk-hz = /bits/ 64 <528000000>;
opp-microvolt = <750000 750000 800000>;
};
opp01 {
opp-hz = /bits/ 64 <786432000>;
opp-microvolt = <800000>;
aclk-hz = /bits/ 64 <880000000>;
opp-microvolt = <800000 750000 800000>;
};
};
@@ -651,6 +653,8 @@
clock-names = "core", "bus";
power-domains = <&power_peri3>;
//iommus = <&iommu DEVID_DIE0_SD>;
clk-delay-default = <46>;
clk-delay-uhs-sdr104 = <46>;
status = "okay";
};
@@ -1910,10 +1914,10 @@
interrupt-parent = <&intc>;
interrupts = <240>;
interrupt-names = "irq_2d";
clocks = <&clk_vp VP_G2D_PCLK_EN>,
clocks = <&clk_vp VP_G2D_CCLK_EN>,
<&clk_vp VP_G2D_ACLK_EN>,
<&clk_vp VP_G2D_CCLK_EN>;
clock-names = "pclk", "aclk", "cclk";
<&clk_vp VP_G2D_PCLK_EN>;
clock-names = "cclk", "aclk", "pclk";
operating-points-v2 = <&g2d_opp_table>;
power-domains = <&power_vp_wrapper>;
status = "okay";