OERV-BSP/kernel-zhihe-a210
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Release develop 260115

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This commit is contained in:
hongyi
2026-01-15 11:06:49 +08:00
parent 1225339fca
commit 2ac7095ee6
5 changed files with 119 additions and 79 deletions
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38
arch/riscv/boot/dts/zhihe/a210-soc-peri.dtsi
View File

@@ -1417,27 +1417,25 @@
};
usb2phy0: phy@08300000 {
compatible = "zhihe,a210-usb2-phy";
reg = <0x00 0x8300000 0x0 0x001000>;
#address-cells = <2>;
#size-cells = <2>;
compatible = "zhihe,a210-usb2-phy0";
reg = <0x00 0x8300000 0x0 0x1000>;
reg-names = "usb20-blk-sysreg";
resets = <&rst USB_USB20_BLK_USB0_PHY_PON_RESET>;
reset-names = "usb-phy-rst";
#phy-cells = <0>;
power-domains = <&power_usb>;
zhihe,init-seq = /bits/ 32 <0x000 0x40b67b5b>;
};
usb2phy1: phy@08301000 {
compatible = "zhihe,a210-usb2-phy";
reg = <0x00 0x8301000 0x0 0x001000>;
#address-cells = <2>;
#size-cells = <2>;
compatible = "zhihe,a210-usb2-phy1";
reg = <0x00 0x8301000 0x0 0x1000>;
reg-names = "usb20-blk-sysreg";
resets = <&rst USB_USB20_BLK_USB1_PHY_PON_RESET>;
reset-names = "usb-phy-rst";
#phy-cells = <0>;
power-domains = <&power_usb>;
zhihe,init-seq = /bits/ 32 <0x000 0x40b67b5b>;
};
usb2_0: dwc2@8200000 {
@@ -1445,18 +1443,22 @@
reg = <0x00 0x8200000 0x0 0x40000>;
interrupt-parent = <&intc>;
interrupts = <181>;
clocks = <&clk_usb USB20_BUS_CLK>;
clock-names = "otg";
resets = <&rst USB_USB20_BLK_USB2_WRAP0_HRST>;
reset-names = "dwc2";
phys = <&usb2phy0>;
phy-names = "usb2-phy";
dr_mode = "host";
maximum-speed = "high-speed";
reg-shift = <2>;
reg-io-width = <4>;
g-np-tx-fifo-size = <16>;
g-rx-fifo-size = <275>;
g-tx-fifo-size = <256 128 128 64 64 32>;
maximum-speed = "high-speed";
dr_mode = "host";
power-domains = <&power_usb>;
// iommus = <&iommu DEVID_DIE0_USB2_0>;
snps,need-phy-for-wake;
phys = <&usb2phy0>;
phy-names = "usb";
};
usb2_1: dwc2@8240000 {
@@ -1464,18 +1466,22 @@
reg = <0x00 0x8240000 0x0 0x40000>;
interrupt-parent = <&intc>;
interrupts = <182>;
clocks = <&clk_usb USB20_BUS_CLK>;
clock-names = "otg";
resets = <&rst USB_USB20_BLK_USB2_WRAP1_HRST>;
reset-names = "dwc2";
phys = <&usb2phy0>, <&usb2phy1>;
phy-names = "usb2-phy0", "usb2-phy1";
dr_mode = "host";
maximum-speed = "high-speed";
reg-shift = <2>;
reg-io-width = <4>;
g-np-tx-fifo-size = <16>;
g-rx-fifo-size = <275>;
g-tx-fifo-size = <256 128 128 64 64 32>;
maximum-speed = "high-speed";
dr_mode = "host";
power-domains = <&power_usb>;
// iommus = <&iommu DEVID_DIE0_USB2_1>;
snps,need-phy-for-wake;
phys = <&usb2phy1>;
phy-names = "usb";
};
audio_pdm0: audio_pdm0@0002008000 {

1
arch/riscv/configs/a210_evb_defconfig
View File

@@ -84,6 +84,7 @@ CONFIG_NF_TABLES=m
CONFIG_NF_TABLES_INET=y
CONFIG_BPFILTER=y
CONFIG_BRIDGE=y
CONFIG_VLAN_8021Q=m
CONFIG_DNS_RESOLVER=y
CONFIG_NETLINK_DIAG=y
CONFIG_CAN=m

2
drivers/mmc/host/sdhci-of-dwcmshc.c
View File

@@ -928,7 +928,7 @@ static const struct sdhci_pltfm_data sdhci_dwcmshc_th1520_pdata = {
static const struct sdhci_pltfm_data sdhci_dwcmshc_a210_pdata = {
.ops = &sdhci_dwcmshc_th1520_ops,
.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
SDHCI_QUIRK_SINGLE_POWER_WRITE | SDHCI_QUIRK_BROKEN_ADMA,
SDHCI_QUIRK_SINGLE_POWER_WRITE,
.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
};

32
drivers/phy/zhihe/phy-zhihe-snps-e16phy.c
View File

@@ -21,28 +21,6 @@
#include <linux/gpio/consumer.h>
/* Registers definition for ZHIHE A210 */
#define E16PHY_GLB_CTRL_REG 0x00000000
#define PYH_SATA_MODE BIT(0)
#define PHY_PCIE_X1_MODE BIT(8)
#define PHY0_CR_PARA_SEL BIT(16)
#define PHY1_CR_PARA_SEL BIT(20)
#define E16PHY_SRC_SEL_REG 0x00000004
#define PIPE_LANE0_PHY_SRC_SEL_SHIFT 0
#define PIPE_LANE1_PHY_SRC_SEL_SHIFT 4
#define PIPE_LINE2_PHY_SRC_SEL_SHIFT 8
#define PIPE_LINE3_PHY_SRC_SEL_SHIFT 12
#define PHY0 0
#define PHY1 1
#define E16PHY_PROTLCOL_REG 0x00000008
#define LANE0_PROTOCOL_SHIFT 0
#define LANE1_PROTOCOL_SHIFT 4
#define LINE2_PROTOCOL_SHIFT 8
#define LINE3_PROTOCOL_SHIFT 12
#define SATA_MODE 2
#define PCIE_MODE 0
#define E16PHY_RES_RTUNE_REG 0x00000048
#define PHY_RTUNE_REQ BIT(0)
#define PHY_RTUNE_ACK BIT(4)
@@ -51,16 +29,6 @@
#define PHY_RES_ACK_IN BIT(16)
#define PHY_RES_ACK_OUT BIT(20)
#define E16PHY_PCIE_EXT_CTRL_REG2 0x00000108
#define E16PHY_PHY0_MPLL_REG 0x00000034
#define E16PHY_PHY1_MPLL_REG 0x00000038
#define MPLLA_STATE BIT(12)
#define MPLLB_STATE BIT(28)
#define E16PHY_PHY0_PPM_REG 0x00000050
#define E16PHY_PHY1_PPM_REG 0x00000054
struct e16phy_seq {
u32 addr;
u32 val;

125
drivers/phy/zhihe/phy-zhihe-snps-usb2.c
View File

@@ -21,53 +21,91 @@
#include <linux/gpio/consumer.h>
/* USB20 BLK SYSREG registers */
#define PHY_ANA_CFG 0x0
#define PHY_CFG 0x4
/* Bit fields */
#define PHY_DM_PULLDOWN BIT(1)
#define PHY_DP_PULLDOWN BIT(0)
#define PHY_DMDP_PULLDOWN (PHY_DM_PULLDOWN | PHY_DP_PULLDOWN)
/* USB2.0 PHY TxVRefTune Mask */
#define USB20_PHY_TXVREFTUNE_MASK 0x1E0000
#define HS_DV_VOLTAGE_LEVEL_POS_16_PER (0xB << 17)
struct usb2_phy_seq {
u32 addr;
u32 val;
};
struct zhihe_usb2_phy {
struct device *dev;
struct phy *phy;
void __iomem *base;
enum phy_mode mode;
int num_clks;
struct clk_bulk_data *clks;
struct reset_control *phy_rst;
struct gpio_desc *pwren;
struct usb2_phy_seq *init_seq;
int num_init_seq;
void (*usb_phy_config)(struct zhihe_usb2_phy *zhphy);
};
static inline void zhihe_snps_set_bits(void __iomem *reg, u32 bits)
{
writel(readl(reg) | bits, reg);
}
static inline void zhihe_snps_clr_bits(void __iomem *reg, u32 bits)
{
writel(readl(reg) & ~bits, reg);
}
static void usb_phy0_config(struct zhihe_usb2_phy *zhphy)
{
zhihe_snps_set_bits(zhphy->base + PHY_CFG, PHY_DMDP_PULLDOWN);
}
static void usb_phy1_config(struct zhihe_usb2_phy *zhphy)
{
zhihe_snps_set_bits(zhphy->base + PHY_CFG, PHY_DMDP_PULLDOWN << 2);
}
static int zhihe_usb2_phy_init(struct phy *phy)
{
struct zhihe_usb2_phy *zhphy = phy_get_drvdata(phy);
int val;
int ret;
/* Set PHY power enable */
if (zhphy->pwren)
gpiod_set_value(zhphy->pwren, 1);
/* Deassert PHY reset */
reset_control_assert(zhphy->phy_rst);
ret = clk_bulk_prepare_enable(zhphy->num_clks, zhphy->clks);
if (ret)
return ret;
/* Pull-up the PHY reset */
// if (zhphy->usb_phy_config)
// zhphy->usb_phy_config(zhphy);
ret = reset_control_assert(zhphy->phy_rst);
if (ret)
goto disable_clocks;
usleep_range(100, 150);
for (int i = 0; i < zhphy->num_init_seq; i++) {
struct usb2_phy_seq *seq = &zhphy->init_seq[i];
writel(seq->val, zhphy->base + seq->addr);
}
ret = reset_control_deassert(zhphy->phy_rst);
if (ret)
goto disable_clocks;
usleep_range(80, 100);
/* Pull-up the PHY reset */
val = readl(zhphy->base + PHY_CFG);
val |= PHY_DM_PULLDOWN | PHY_DP_PULLDOWN;
writel(val, zhphy->base + PHY_CFG);
/* Configure PHY analog - Set TxVRefTune */
val = readl(zhphy->base + PHY_ANA_CFG);
val &= ~USB20_PHY_TXVREFTUNE_MASK;
val |= HS_DV_VOLTAGE_LEVEL_POS_16_PER;
writel(val, zhphy->base + PHY_ANA_CFG);
/* Assert PHY reset to complete initialization */
reset_control_deassert(zhphy->phy_rst);
if (zhphy->usb_phy_config)
zhphy->usb_phy_config(zhphy);
return 0;
disable_clocks:
clk_bulk_disable_unprepare(zhphy->num_clks, zhphy->clks);
return ret;
}
static int zhihe_usb2_phy_exit(struct phy *phy)
@@ -83,9 +121,18 @@ static int zhihe_usb2_phy_exit(struct phy *phy)
return 0;
}
static int zhihe_usb2_set_mode(struct phy *phy, enum phy_mode mode, int submode)
{
struct zhihe_usb2_phy *zhphy = phy_get_drvdata(phy);
zhphy->mode = mode;
return 0;
}
static const struct phy_ops zhihe_usb2_phy_ops = {
.init = zhihe_usb2_phy_init,
.exit = zhihe_usb2_phy_exit,
.set_mode = zhihe_usb2_set_mode,
.owner = THIS_MODULE,
};
@@ -94,13 +141,17 @@ static int zhihe_usb2_phy_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct zhihe_usb2_phy *zhphy;
struct phy_provider *phy_provider;
struct phy *generic_phy;
int ret, size;
zhphy = devm_kzalloc(dev, sizeof(*zhphy), GFP_KERNEL);
if (!zhphy)
return -ENOMEM;
zhphy->dev = dev;
zhphy->usb_phy_config = device_get_match_data(&pdev->dev);
if (!zhphy->usb_phy_config) {
return -EINVAL;
}
/* Get USB20 BLK SYSREG base address */
zhphy->base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
@@ -121,16 +172,29 @@ static int zhihe_usb2_phy_probe(struct platform_device *pdev)
return PTR_ERR(zhphy->pwren);
}
size = of_property_count_u32_elems(dev->of_node, "zhihe,init-seq");
if (size < 0)
size = 0;
zhphy->num_init_seq = size / 2;
zhphy->init_seq = devm_kmalloc_array(dev, zhphy->num_init_seq,
sizeof(*zhphy->init_seq), GFP_KERNEL);
if (!zhphy->init_seq)
return -ENOMEM;
ret = of_property_read_u32_array(dev->of_node, "zhihe,init-seq",
(u32 *)zhphy->init_seq, size);
if (ret) {
return ret;
}
/* Create PHY */
generic_phy = devm_phy_create(dev, NULL, &zhihe_usb2_phy_ops);
if (IS_ERR(generic_phy)) {
dev_err(dev, "failed to create phy: %ld\n", PTR_ERR(generic_phy));
return PTR_ERR(generic_phy);
zhphy->phy = devm_phy_create(dev, NULL, &zhihe_usb2_phy_ops);
if (IS_ERR(zhphy->phy)) {
dev_err(dev, "failed to create phy: %ld\n", PTR_ERR(zhphy->phy));
return PTR_ERR(zhphy->phy);
}
zhphy->phy = generic_phy;
dev_set_drvdata(dev, zhphy);
phy_set_drvdata(generic_phy, zhphy);
phy_set_drvdata(zhphy->phy, zhphy);
/* Register PHY provider */
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
@@ -144,7 +208,8 @@ static int zhihe_usb2_phy_probe(struct platform_device *pdev)
}
static const struct of_device_id zhihe_usb2_phy_of_match[] = {
{ .compatible = "zhihe,a210-usb2-phy", },
{ .compatible = "zhihe,a210-usb2-phy0", .data = usb_phy0_config},
{ .compatible = "zhihe,a210-usb2-phy1", .data = usb_phy1_config},
{ }
};
MODULE_DEVICE_TABLE(of, zhihe_usb2_phy_of_match);