OERV-BSP/kernel-zhihe-a210
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Release develop 260114

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hongyi
2026-01-14 11:49:10 +08:00
parent 434ae3d5fc
commit 1225339fca
3 changed files with 24 additions and 23 deletions
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24
arch/riscv/boot/dts/zhihe/a210-soc-core-die1.dtsi
View File

@@ -429,7 +429,7 @@
reg-names = "GPU_SS_PWRAP_CLK_EN","GPU_SS_TOP_CLK_EN";
#clock-cells = <1>;
assigned-clocks = <&clk_die1 TOP_GPU_CORE_CLK_DIV>;
assigned-clock-rates = <528000000>;
assigned-clock-rates = <792000000>;
status = "okay";
};
@@ -476,8 +476,8 @@
#clock-cells = <1>;
assigned-clocks = <&clk_die1 TOP_VP_ACLK_DIV>, <&clk_die1 TOP_VP_VDEC_CCLK_DIV>,
<&clk_die1 TOP_VP_VENC_CCLK_DIV>, <&clk_die1 TOP_VP_G2D_CCLK_DIV>;
assigned-clock-rates = <528000000>, <600000000>,
<528000000>, <600000000>;
assigned-clock-rates = <880000000>, <786432000>,
<600000000>, <786432000>;
status = "okay";
};
@@ -503,7 +503,7 @@
reg-names = "NPU_CLK","NPU_TOP_CLK";
#clock-cells = <1>;
assigned-clocks = <&clk_die1 TOP_NPU_CCLK_DIV>, <&clk_die1 TOP_NPU_ACLK_DIV>;
assigned-clock-rates = <472000000>, <472000000>;
assigned-clock-rates = <880000000>, <880000000>;
status = "okay";
};
@@ -625,7 +625,7 @@
reg-names = "GPU_SS_PWRAP_CLK_EN","GPU_SS_TOP_CLK_EN";
#clock-cells = <1>;
assigned-clocks = <&clk_die2 TOP_GPU_CORE_CLK_DIV>;
assigned-clock-rates = <528000000>;
assigned-clock-rates = <792000000>;
status = "okay";
};
@@ -672,8 +672,8 @@
#clock-cells = <1>;
assigned-clocks = <&clk_die2 TOP_VP_ACLK_DIV>, <&clk_die2 TOP_VP_VDEC_CCLK_DIV>,
<&clk_die2 TOP_VP_VENC_CCLK_DIV>, <&clk_die2 TOP_VP_G2D_CCLK_DIV>;
assigned-clock-rates = <528000000>, <600000000>,
<528000000>, <600000000>;
assigned-clock-rates = <880000000>, <786432000>,
<600000000>, <786432000>;
status = "okay";
};
@@ -699,7 +699,7 @@
reg-names = "NPU_CLK","NPU_TOP_CLK";
#clock-cells = <1>;
assigned-clocks = <&clk_die2 TOP_NPU_CCLK_DIV>, <&clk_die2 TOP_NPU_ACLK_DIV>;
assigned-clock-rates = <472000000>, <472000000>;
assigned-clock-rates = <880000000>, <880000000>;
status = "okay";
};
@@ -821,7 +821,7 @@
reg-names = "GPU_SS_PWRAP_CLK_EN","GPU_SS_TOP_CLK_EN";
#clock-cells = <1>;
assigned-clocks = <&clk_die3 TOP_GPU_CORE_CLK_DIV>;
assigned-clock-rates = <528000000>;
assigned-clock-rates = <792000000>;
status = "okay";
};
@@ -868,8 +868,8 @@
#clock-cells = <1>;
assigned-clocks = <&clk_die3 TOP_VP_ACLK_DIV>, <&clk_die3 TOP_VP_VDEC_CCLK_DIV>,
<&clk_die3 TOP_VP_VENC_CCLK_DIV>, <&clk_die3 TOP_VP_G2D_CCLK_DIV>;
assigned-clock-rates = <528000000>, <600000000>,
<528000000>, <600000000>;
assigned-clock-rates = <880000000>, <786432000>,
<600000000>, <786432000>;
status = "okay";
};
@@ -895,7 +895,7 @@
reg-names = "NPU_CLK","NPU_TOP_CLK";
#clock-cells = <1>;
assigned-clocks = <&clk_die3 TOP_NPU_CCLK_DIV>, <&clk_die3 TOP_NPU_ACLK_DIV>;
assigned-clock-rates = <472000000>, <472000000>;
assigned-clock-rates = <880000000>, <880000000>;
status = "okay";
};

8
arch/riscv/boot/dts/zhihe/a210-soc-core.dtsi
View File

@@ -574,7 +574,7 @@
reg-names = "GPU_SS_PWRAP_CLK_EN","GPU_SS_TOP_CLK_EN";
#clock-cells = <1>;
assigned-clocks = <&clk TOP_GPU_CORE_CLK_DIV>;
assigned-clock-rates = <528000000>;
assigned-clock-rates = <792000000>;
power-domains = <&power_gpu>;
status = "okay";
};
@@ -623,8 +623,8 @@
#clock-cells = <1>;
assigned-clocks = <&clk TOP_VP_ACLK_DIV>, <&clk TOP_VP_VDEC_CCLK_DIV>,
<&clk TOP_VP_VENC_CCLK_DIV>, <&clk TOP_VP_G2D_CCLK_DIV>;
assigned-clock-rates = <528000000>, <600000000>,
<528000000>, <600000000>;
assigned-clock-rates = <880000000>, <786432000>,
<600000000>, <786432000>;
power-domains = <&power_vp_wrapper>;
status = "okay";
};
@@ -654,7 +654,7 @@
reg-names = "NPU_CLK","NPU_TOP_CLK";
#clock-cells = <1>;
assigned-clocks = <&clk TOP_NPU_CCLK_DIV>, <&clk TOP_NPU_ACLK_DIV>;
assigned-clock-rates = <472000000>, <472000000>;
assigned-clock-rates = <880000000>, <880000000>;
power-domains = <&power_npu_wrapper>;
status = "okay";
};

15
drivers/pmdomain/zhihe/a210-pd.c
View File

@@ -518,17 +518,18 @@ static int a210_pd_parse_regulators(struct device *dev)
if (of_property_present(child, "pmic-supply")) {
child_regulator = of_parse_phandle(child, "pmic-supply", 0);
pd_soc->regulators[id] = devm_regulator_get_optional(dev, child_regulator->name);
pd_soc->regulators[id] = regulator_get_optional(dev, child_regulator->name);
if (IS_ERR(pd_soc->regulators[id])) {
dev_dbg(dev, "Regulator for %s deferred %ld\n", child->name, PTR_ERR(pd_soc->regulators[id]));
return -EPROBE_DEFER;
} else {
u32 min_uV, max_uV;
if (of_property_read_u32(child_regulator, "regulator-min-microvolt", &min_uV) == 0 &&
of_property_read_u32(child_regulator, "regulator-max-microvolt", &max_uV) == 0) {
regulator_set_voltage(pd_soc->regulators[id], min_uV, max_uV);
dev_info(dev, "Set %s voltage range [%d, %d]uV\n",
child->name, min_uV, max_uV);
u32 max_uV = 0;
if (of_property_read_u32(child_regulator, "regulator-max-microvolt", &max_uV) == 0) {
regulator_set_voltage(pd_soc->regulators[id], max_uV, max_uV);
dev_info(dev, "Set %s voltage target %duV\n",
child->name, max_uV);
regulator_put(pd_soc->regulators[id]);
pd_soc->regulators[id] = devm_regulator_get_optional(dev, child_regulator->name);
}
}
}