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tools/perf: pmu-events: fix X60 L2 cache events

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The previous names and descriptions of L2 cache events on SpacemiT X60
are incorrect, now fix them.

Change-Id: I847eac354dc493f195d2f02bc1598bffb13ff74d
Signed-off-by: linjunyan <junyan.lin@spacemit.com>
This commit is contained in:
linjunyan
2025-05-14 14:24:31 +08:00
committed by 张猛
parent 242c03e7a6
commit e25c7f169c
1 changed files with 15 additions and 15 deletions
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30
tools/perf/pmu-events/arch/riscv/spacemit/x60/cache.json
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@@ -89,25 +89,25 @@
"EventCode": "175", "EventCode": "175",
"BriefDescription": "L1 D-cache prefetch hits" "BriefDescription": "L1 D-cache prefetch hits"
}, },
{
"EventName": "l2_access",
"EventCode": "184",
"BriefDescription": "L2 cache accesses"
},
{
"EventName": "l2_miss",
"EventCode": "185",
"BriefDescription": "L2 cache misses"
},
{ {
"EventName": "l2_load_access", "EventName": "l2_load_access",
"EventCode": "186", "EventCode": "184",
"BriefDescription": "L2 cache load accesses" "BriefDescription": "L2 cache load accesses"
}, },
{ {
"EventName": "l2_load_stall", "EventName": "l2_load_miss",
"EventCode": "185",
"BriefDescription": "L2 cache load misses"
},
{
"EventName": "l2_ar_channel_request",
"EventCode": "186",
"BriefDescription": "Total number of L2 cache AR channel requests, including read accesses, non-coherent read accesses and DVM accesses"
},
{
"EventName": "l2_ar_channel_stall_cycle",
"EventCode": "187", "EventCode": "187",
"BriefDescription": "L2 cache load stalls" "BriefDescription": "L2 cache AR channel stall cycles"
}, },
{ {
"EventName": "l2_store_access", "EventName": "l2_store_access",
@@ -115,8 +115,8 @@
"BriefDescription": "L2 cache store accesses" "BriefDescription": "L2 cache store accesses"
}, },
{ {
"EventName": "l2_store_stall", "EventName": "l2_aw_channel_stall_cycle",
"EventCode": "189", "EventCode": "189",
"BriefDescription": "L2 cache store stalls" "BriefDescription": "L2 cache AW channel stall cycles"
} }
] ]