e25c7f169c
The previous names and descriptions of L2 cache events on SpacemiT X60 are incorrect, now fix them. Change-Id: I847eac354dc493f195d2f02bc1598bffb13ff74d Signed-off-by: linjunyan <junyan.lin@spacemit.com>
123 lines
2.9 KiB
JSON
123 lines
2.9 KiB
JSON
[
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{
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"EventName": "l1d_load_miss",
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"EventCode": "5",
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"BriefDescription": "L1 D-cache load misses"
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},
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{
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"EventName": "l1d_load_access",
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"EventCode": "6",
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"BriefDescription": "L1 D-cache load accesses"
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},
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{
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"EventName": "l1d_store_miss",
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"EventCode": "9",
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"BriefDescription": "L1 D-cache store misses"
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},
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{
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"EventName": "l1d_store_access",
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"EventCode": "10",
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"BriefDescription": "L1 D-cache store accesses"
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},
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{
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"EventName": "l1i_load_miss",
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"EventCode": "11",
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"BriefDescription": "L1 I-cache load misses"
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},
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{
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"EventName": "l1i_load_access",
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"EventCode": "12",
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"BriefDescription": "L1 I-cache load accesses"
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},
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{
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"EventName": "l1i_prefetch_miss",
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"EventCode": "13",
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"BriefDescription": "L1 I-cache prefetch misses"
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},
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{
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"EventName": "l1i_prefetch",
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"EventCode": "14",
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"BriefDescription": "L1 I-cache prefetches"
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},
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{
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"EventName": "dtlb_load_miss",
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"EventCode": "21",
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"BriefDescription": "DTLB load misses"
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},
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{
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"EventName": "dtlb_store_miss",
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"EventCode": "25",
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"BriefDescription": "DTLB store misses"
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},
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{
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"EventName": "itlb_load_miss",
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"EventCode": "27",
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"BriefDescription": "ITLB load misses"
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},
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{
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"EventName": "jtlb_miss",
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"EventCode": "163",
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"BriefDescription": "JTLB misses"
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},
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{
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"EventName": "l1d_access",
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"EventCode": "170",
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"BriefDescription": "L1 D-cache accesses"
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},
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{
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"EventName": "l1d_miss",
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"EventCode": "171",
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"BriefDescription": "L1 D-cache misses"
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},
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{
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"EventName": "l1d_excl_evict",
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"EventCode": "172",
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"BriefDescription": "L1 D-cache exclusive evictions to L2"
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},
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{
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"EventName": "l1d_amr_active",
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"EventCode": "173",
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"BriefDescription": "L1 D-cache AMR actives"
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},
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{
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"EventName": "l1d_prefetch_refill",
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"EventCode": "174",
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"BriefDescription": "L1 D-cache prefetch refills"
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},
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{
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"EventName": "l1d_prefetch_hit",
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"EventCode": "175",
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"BriefDescription": "L1 D-cache prefetch hits"
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},
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{
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"EventName": "l2_load_access",
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"EventCode": "184",
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"BriefDescription": "L2 cache load accesses"
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},
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{
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"EventName": "l2_load_miss",
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"EventCode": "185",
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"BriefDescription": "L2 cache load misses"
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},
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{
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"EventName": "l2_ar_channel_request",
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"EventCode": "186",
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"BriefDescription": "Total number of L2 cache AR channel requests, including read accesses, non-coherent read accesses and DVM accesses"
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},
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{
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"EventName": "l2_ar_channel_stall_cycle",
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"EventCode": "187",
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"BriefDescription": "L2 cache AR channel stall cycles"
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},
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{
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"EventName": "l2_store_access",
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"EventCode": "188",
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"BriefDescription": "L2 cache store accesses"
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},
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{
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"EventName": "l2_aw_channel_stall_cycle",
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"EventCode": "189",
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"BriefDescription": "L2 cache AW channel stall cycles"
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}
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]
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