RISC-V: Support Sstvecd extension.

Support the Sstvecd extension, which allows Supervisor Trap Vector
Base Address register (stvec) to support Direct mode.

gcc/ChangeLog:

	* config/riscv/riscv-ext.def: New extension definition.
	* config/riscv/riscv-ext.opt: New extension mask.
	* doc/riscv-ext.texi: Document the new extension.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/arch-sstvecd.c: New test.

Signed-off-by: Jiawei <jiawei@iscas.ac.cn>

gcc/config/riscv/riscv-ext.def

@@ -1922,6 +1922,19 @@ DEFINE_RISCV_EXT(
   /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
   /* EXTRA_EXTENSION_FLAGS */ 0)
 
+DEFINE_RISCV_EXT(
+  /* NAME */ sstvecd,
+  /* UPPERCASE_NAME */ SSTVECD,
+  /* FULL_NAME */ "Stvec supports Direct mode",
+  /* DESC */ "",
+  /* URL */ ,
+  /* DEP_EXTS */ ({"zicsr"}),
+  /* SUPPORTED_VERSIONS */ ({{1, 0}}),
+  /* FLAG_GROUP */ ss,
+  /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+  /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+  /* EXTRA_EXTENSION_FLAGS */ 0)
+
 DEFINE_RISCV_EXT(
   /* NAME */ ssstrict,
   /* UPPERCASE_NAME */ SSSTRICT,

gcc/config/riscv/riscv-ext.opt

@@ -373,6 +373,8 @@ Mask(SSTC) Var(riscv_ss_subext)
 
 Mask(SSTVALA) Var(riscv_ss_subext)
 
+Mask(SSTVECD) Var(riscv_ss_subext)
+
 Mask(SSSTRICT) Var(riscv_ss_subext)
 
 Mask(SSDBLTRP) Var(riscv_ss_subext)

gcc/doc/riscv-ext.texi

@@ -570,6 +570,10 @@
 @tab 1.0
 @tab Stval provides all needed values
 
+@item sstvecd
+@tab 1.0
+@tab Stvec supports Direct mode
+
 @item ssstrict
 @tab 1.0
 @tab ssstrict extension

gcc/testsuite/gcc.target/riscv/arch-sstvecd.c

@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_sstvecd -mabi=lp64" } */
+int foo()
+{
+}