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https://github.com/openRuyi-Project/gcc.git
synced 2026-09-06 22:11:37 +00:00
RISC-V: Drop riscv_ext_version_table in favor of riscv_ext_info_t data
This commit drops the riscv_ext_version_table and instead uses the riscv_ext_info_t data structure to provide the version information for RISC-V extensions. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_ext_version_table): Remove. (standard_extensions_p): Use riscv_ext_info_t. (get_default_version): Use riscv_ext_info_t. (riscv_arch_help): Ditto.
This commit is contained in:
Kito Cheng
@@ -269,225 +269,6 @@ struct riscv_profiles
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const char *profile_string;
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};
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/* All standard extensions defined in all supported ISA spec. */
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static const struct riscv_ext_version riscv_ext_version_table[] =
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{
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/* name, ISA spec, major version, minor_version. */
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{"e", ISA_SPEC_CLASS_20191213, 2, 0},
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{"e", ISA_SPEC_CLASS_20190608, 2, 0},
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{"e", ISA_SPEC_CLASS_2P2, 2, 0},
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{"i", ISA_SPEC_CLASS_20191213, 2, 1},
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{"i", ISA_SPEC_CLASS_20190608, 2, 1},
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{"i", ISA_SPEC_CLASS_2P2, 2, 0},
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{"m", ISA_SPEC_CLASS_20191213, 2, 0},
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{"m", ISA_SPEC_CLASS_20190608, 2, 0},
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{"m", ISA_SPEC_CLASS_2P2, 2, 0},
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{"a", ISA_SPEC_CLASS_20191213, 2, 1},
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{"a", ISA_SPEC_CLASS_20190608, 2, 0},
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{"a", ISA_SPEC_CLASS_2P2, 2, 0},
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{"f", ISA_SPEC_CLASS_20191213, 2, 2},
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{"f", ISA_SPEC_CLASS_20190608, 2, 2},
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{"f", ISA_SPEC_CLASS_2P2, 2, 0},
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{"d", ISA_SPEC_CLASS_20191213, 2, 2},
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{"d", ISA_SPEC_CLASS_20190608, 2, 2},
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{"d", ISA_SPEC_CLASS_2P2, 2, 0},
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{"c", ISA_SPEC_CLASS_20191213, 2, 0},
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{"c", ISA_SPEC_CLASS_20190608, 2, 0},
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{"c", ISA_SPEC_CLASS_2P2, 2, 0},
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{"b", ISA_SPEC_CLASS_NONE, 1, 0},
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{"h", ISA_SPEC_CLASS_NONE, 1, 0},
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{"v", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zicsr", ISA_SPEC_CLASS_20191213, 2, 0},
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{"zicsr", ISA_SPEC_CLASS_20190608, 2, 0},
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{"zifencei", ISA_SPEC_CLASS_20191213, 2, 0},
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{"zifencei", ISA_SPEC_CLASS_20190608, 2, 0},
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{"zicond", ISA_SPEC_CLASS_NONE, 1, 0},
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{"za64rs", ISA_SPEC_CLASS_NONE, 1, 0},
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{"za128rs", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zawrs", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zaamo", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zalrsc", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zabha", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zacas", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zama16b", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zba", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zbb", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zbc", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zbs", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zfinx", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zdinx", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zhinx", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zhinxmin", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zbkb", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zbkc", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zbkx", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zkne", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zknd", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zknh", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zkr", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zksed", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zksh", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zkt", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zihintntl", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zihintpause", ISA_SPEC_CLASS_NONE, 2, 0},
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{"zicboz",ISA_SPEC_CLASS_NONE, 1, 0},
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{"zicbom",ISA_SPEC_CLASS_NONE, 1, 0},
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{"zicbop",ISA_SPEC_CLASS_NONE, 1, 0},
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{"zic64b", ISA_SPEC_CLASS_NONE, 1, 0},
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{"ziccamoa", ISA_SPEC_CLASS_NONE, 1, 0},
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{"ziccif", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zicclsm", ISA_SPEC_CLASS_NONE, 1, 0},
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{"ziccrse", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zicfiss", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zicfilp", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zimop", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zcmop", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zicntr", ISA_SPEC_CLASS_NONE, 2, 0},
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{"zihpm", ISA_SPEC_CLASS_NONE, 2, 0},
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{"zilsd", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zclsd", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zk", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zkn", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zks", ISA_SPEC_CLASS_NONE, 1, 0},
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{"ztso", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zve32x", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zve32f", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zve64x", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zve64f", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zve64d", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zvbb", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zvbc", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zvkb", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zvkg", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zvkned", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zvknha", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zvknhb", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zvksed", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zvksh", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zvkn", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zvknc", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zvkng", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zvks", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zvksc", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zvksg", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zvkt", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zvl32b", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zvl64b", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zvl128b", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zvl256b", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zvl512b", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zvl1024b", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zvl2048b", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zvl4096b", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zvl8192b", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zvl16384b", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zvl32768b", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zvl65536b", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zfbfmin", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zfh", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zfhmin", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zvfbfmin", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zvfbfwma", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zvfhmin", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zvfh", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zfa", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zmmul", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zca", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zcb", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zce", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zcf", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zcd", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zcmp", ISA_SPEC_CLASS_NONE, 1, 0},
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{"zcmt", ISA_SPEC_CLASS_NONE, 1, 0},
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{"sdtrig", ISA_SPEC_CLASS_NONE, 1, 0},
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{"smaia", ISA_SPEC_CLASS_NONE, 1, 0},
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{"smepmp", ISA_SPEC_CLASS_NONE, 1, 0},
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{"smstateen", ISA_SPEC_CLASS_NONE, 1, 0},
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{"ssaia", ISA_SPEC_CLASS_NONE, 1, 0},
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{"sscofpmf", ISA_SPEC_CLASS_NONE, 1, 0},
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{"ssstateen", ISA_SPEC_CLASS_NONE, 1, 0},
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{"sstc", ISA_SPEC_CLASS_NONE, 1, 0},
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{"ssstrict", ISA_SPEC_CLASS_NONE, 1, 0},
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{"ssnpm", ISA_SPEC_CLASS_NONE, 1, 0},
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{"smnpm", ISA_SPEC_CLASS_NONE, 1, 0},
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{"smmpm", ISA_SPEC_CLASS_NONE, 1, 0},
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{"sspm", ISA_SPEC_CLASS_NONE, 1, 0},
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{"supm", ISA_SPEC_CLASS_NONE, 1, 0},
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{"svade", ISA_SPEC_CLASS_NONE, 1, 0},
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{"svadu", ISA_SPEC_CLASS_NONE, 1, 0},
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{"svinval", ISA_SPEC_CLASS_NONE, 1, 0},
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{"svnapot", ISA_SPEC_CLASS_NONE, 1, 0},
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{"svpbmt", ISA_SPEC_CLASS_NONE, 1, 0},
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{"svvptc", ISA_SPEC_CLASS_NONE, 1, 0},
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{"xcvmac", ISA_SPEC_CLASS_NONE, 1, 0},
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{"xcvalu", ISA_SPEC_CLASS_NONE, 1, 0},
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{"xcvelw", ISA_SPEC_CLASS_NONE, 1, 0},
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{"xcvsimd", ISA_SPEC_CLASS_NONE, 1, 0},
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{"xcvbi", ISA_SPEC_CLASS_NONE, 1, 0},
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{"xtheadba", ISA_SPEC_CLASS_NONE, 1, 0},
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{"xtheadbb", ISA_SPEC_CLASS_NONE, 1, 0},
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{"xtheadbs", ISA_SPEC_CLASS_NONE, 1, 0},
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{"xtheadcmo", ISA_SPEC_CLASS_NONE, 1, 0},
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{"xtheadcondmov", ISA_SPEC_CLASS_NONE, 1, 0},
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{"xtheadfmemidx", ISA_SPEC_CLASS_NONE, 1, 0},
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{"xtheadfmv", ISA_SPEC_CLASS_NONE, 1, 0},
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{"xtheadint", ISA_SPEC_CLASS_NONE, 1, 0},
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{"xtheadmac", ISA_SPEC_CLASS_NONE, 1, 0},
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{"xtheadmemidx", ISA_SPEC_CLASS_NONE, 1, 0},
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{"xtheadmempair", ISA_SPEC_CLASS_NONE, 1, 0},
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{"xtheadsync", ISA_SPEC_CLASS_NONE, 1, 0},
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{"xtheadvector", ISA_SPEC_CLASS_NONE, 1, 0},
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{"xventanacondops", ISA_SPEC_CLASS_NONE, 1, 0},
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{"xsfvcp", ISA_SPEC_CLASS_NONE, 1, 0},
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{"xsfcease", ISA_SPEC_CLASS_NONE, 1, 0},
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{"xsfvqmaccqoq", ISA_SPEC_CLASS_NONE, 1, 0},
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{"xsfvqmaccdod", ISA_SPEC_CLASS_NONE, 1, 0},
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{"xsfvfnrclipxfqf", ISA_SPEC_CLASS_NONE, 1, 0},
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/* Terminate the list. */
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{NULL, ISA_SPEC_CLASS_NONE, 0, 0}
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};
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/* This table records the mapping form RISC-V Profiles into march string. */
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static const riscv_profiles riscv_profiles_table[] =
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{
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@@ -762,11 +543,8 @@ subset_cmp (const std::string &a, const std::string &b)
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static bool
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standard_extensions_p (const char *ext)
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{
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const riscv_ext_version *ext_ver;
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for (ext_ver = &riscv_ext_version_table[0]; ext_ver->name != NULL; ++ext_ver)
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if (strcmp (ext, ext_ver->name) == 0)
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return true;
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return false;
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auto itr = riscv_ext_infos.find (ext);
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return itr != riscv_ext_infos.end ();
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}
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/* Add new subset to list. */
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@@ -896,24 +674,19 @@ get_default_version (const char *ext,
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unsigned int *major_version,
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unsigned int *minor_version)
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{
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const riscv_ext_version *ext_ver;
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for (ext_ver = &riscv_ext_version_table[0];
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ext_ver->name != NULL;
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++ext_ver)
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if (strcmp (ext, ext_ver->name) == 0)
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{
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if ((ext_ver->isa_spec_class == riscv_isa_spec) ||
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(ext_ver->isa_spec_class == ISA_SPEC_CLASS_NONE))
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{
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*major_version = ext_ver->major_version;
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*minor_version = ext_ver->minor_version;
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return;
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}
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}
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auto itr = riscv_ext_infos.find (ext);
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if (itr == riscv_ext_infos.end ())
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{
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/* Not found version info. */
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*major_version = 0;
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*minor_version = 0;
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return;
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}
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/* Not found version info. */
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*major_version = 0;
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*minor_version = 0;
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riscv_version_t ver = itr->second.default_version ();
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/* Get the version info from riscv_ext_infos. */
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*major_version = ver.major_version;
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*minor_version = ver.minor_version;
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}
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/* Add new subset to list, but using default version from ISA spec version. */
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@@ -2601,16 +2374,15 @@ riscv_arch_help (int, const char **)
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}
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};
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std::map<std::string, std::set<unsigned>, extension_comparator> all_exts;
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for (const riscv_ext_version &ext : riscv_ext_version_table)
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for (const auto &[ext_name, ext_info] : riscv_ext_infos)
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{
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if (!ext.name)
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break;
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if (ext.name[0] == 'g')
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continue;
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unsigned version_value = (ext.major_version * RISCV_MAJOR_VERSION_BASE)
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+ (ext.minor_version
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* RISCV_MINOR_VERSION_BASE);
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all_exts[ext.name].insert(version_value);
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for (auto &supported_version : ext_info.supported_versions ())
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{
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unsigned version_value
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= (supported_version.major_version * RISCV_MAJOR_VERSION_BASE)
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+ (supported_version.minor_version * RISCV_MINOR_VERSION_BASE);
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all_exts[ext_name].insert (version_value);
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}
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}
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printf("All available -march extensions for RISC-V:\n");
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