Commit Graph
9 Commits
Author SHA1 Message Date
Pritesh Raithatha 933d87a56e ARM: tegra: add SDHCI nodes with common properties
This patch adds in the SDHCI nodes for the busses supported on Tegra114
boards.

Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
[Rhyland added clk refs to & reordered sdhci nodes and removed spaces]
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
[swarren: fixed DT node sort order]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-04-04 17:17:39 -06:00
Pritesh Raithatha 2c314d5c2a ARM: tegra: add default pinctrl nodes for Dalmore
This change adds the default pinctrl nodes for the Dalmore Tegra114
platform.

Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
[Rhyland added patch description]
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
[swarren: fixed DT node sort order]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-04-04 17:17:39 -06:00
Pritesh Raithatha b6ae7a2653 pinctrl: tegra114: add pinctrl driver for NVIDIA's Tegra114 SoC
This adds a driver for the Tegra114 pinmux, and required
parameterization data for Tegra114.

The driver uses the common Tegra pincontrol driver utility
functions to implement the majority of the driver.

This driver is not compatible with the earlier NVIDIA's SoCs,
hence add new compatibile as "nvidia,tegra114-pinmux".

Originally written by Pritesh.
ldewangan:
	- cleanup the patches,
	- remove non-require tables.
	- Use module_platform_driver() for driver registartion.

Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-01-18 16:14:54 +01:00
Pritesh Raithatha 348d1bf75c pinctrl: tegra: add support for rcv-sel and drive type
NVIDIA's Tegra114 added two more configuration parameter in pinmux i.e.
rcv-sel and drive type.

rcv-sel: Select between High and Normal VIL/VIH receivers.
	RCVR_SEL=1: High VIL/VIH
	RCVR_SEL=0: Normal VIL/VIH

drv_type: Ouptput drive type:
	33-50 ohm driver: 0x1
	66-100ohm driver: 0x0

Add support of these parameters to be configure from DTS file.

Tegra20 and Tegra30 does not support this configuration and hence initialize their
pinmux structure with reg = -1.

Originally written by Pritesh Raithatha.
Changes by ldewangan:
	- remove drvtype_width as it is always 2.
	- Better describe the change.

Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-01-18 16:13:52 +01:00
Pritesh Raithatha 322337b8fb ARM: dt: tegra: fix length of pad control and mux registers
The reg property contains <base length> not <base last_offset>. Fix
the length values to be length not last_offset.

Cc: stable@vger.kernel.org
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-10-30 14:37:06 -06:00
Pritesh Raithatha a03690e444 pinctrl: tegra: correct bank for pingroup and drv pingroup
Cc: stable@kernel.org
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-10-17 19:49:28 +02:00
Pritesh Raithatha 154f3ebf53 pinctrl: tegra: set low power mode bank width to 2
Cc: stable@kernel.org
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-10-17 19:47:06 +02:00
Pritesh Raithatha d6ec6b60a5 dt: Document: correct tegra20/30 pinctrl slew-rate name
change nvidia,slew_rate* to nvidia,slew-rate*

Cc: stable@kernel.org
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-10-17 19:45:35 +02:00
Pritesh Raithatha ecb7a8ebdc gpio-charger: Use cansleep version of gpio_set_value
Context of gpio_charger_get_property is sleepable so we should
use gpio_set_value_cansleep instead of gpio_set_value.

It will remove WARN_ON incase of using gpio from i2c-to-gpio
expander like pca953x.

Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Acked-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Anton Vorontsov <cbouatmailru@gmail.com>
2012-06-19 20:48:37 -07:00