Documentation: Update the CXL Maturity Map

Changes for extended-linear cache, hetero-interleave, and HPA->DPA
address translation.

Signed-off-by: Alison Schofield <alison.schofield@intel.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Link: https://patch.msgid.link/20250512214225.1389484-1-alison.schofield@intel.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>

Documentation/driver-api/cxl/maturity-map.rst

@@ -51,9 +51,9 @@ in place, but there are several corner cases that are pending closure.
 
 * [2] CXL Window Enumeration
 
-  * [0] :ref:`Extended-linear memory-side cache <extended-linear>`
+  * [2] :ref:`Extended-linear memory-side cache <extended-linear>`
   * [0] Low Memory-hole
-  * [0] Hetero-interleave
+  * [X] Hetero-interleave
 
 * [2] Switch Enumeration
 
@@ -173,7 +173,7 @@ Accelerator
 User Flow Support
 -----------------
 
-* [0] HPA->DPA Address translation (need xormaps export solution)
+* [0] Inject & clear poison by HPA
 
 Details
 =======

Documentation/driver-api/cxl/theory-of-operation.rst

@@ -392,8 +392,7 @@ CXL Core
 .. kernel-doc:: drivers/cxl/core/features.c
    :doc: cxl features
 
-.. kernel-doc:: drivers/cxl/core/features.c
-   :identifiers:
+See :c:func:`devm_cxl_setup_features` for API details.
 
 CXL Regions
 -----------

drivers/cxl/core/features.c

@@ -12,6 +12,7 @@
 /**
  * DOC: cxl features
  *
+ * CXL Features:
  * A CXL device that includes a mailbox supports commands that allows
  * listing, getting, and setting of optionally defined features such
  * as memory sparing or post package sparing. Vendors may define custom