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drm/amd/display: Don't reserve pipe for underlay on ASIC without underlay

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Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Harry Wentland
2017-09-26 17:11:28 -04:00
committed by Alex Deucher
parent adc9b14139
commit f0e3db90a6
5 changed files with 7 additions and 5 deletions
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drivers/gpu/drm/amd/display/dc/core/dc.c
+1 -1
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@@ -621,7 +621,7 @@ struct dc *dc_create(const struct dc_init_data *init_params)
core_dc->hwss.init_hw(core_dc);
full_pipe_count = core_dc->res_pool->pipe_count;
if (core_dc->res_pool->underlay_pipe_index >= 0)
if (core_dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE)
full_pipe_count--;
core_dc->public.caps.max_streams = min(
full_pipe_count,
drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+2 -2
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@@ -934,7 +934,7 @@ static bool construct(
pool->base.res_cap = &res_cap;
pool->base.funcs = &dce100_res_pool_funcs;
pool->base.underlay_pipe_index = -1;
pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
bp = ctx->dc_bios;
@@ -1004,7 +1004,7 @@ static bool construct(
/*************************************************
* Resource + asic cap harcoding *
*************************************************/
pool->base.underlay_pipe_index = -1;
pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
pool->base.pipe_count = res_cap.num_timing_generator;
dc->public.caps.max_downscale_ratio = 200;
dc->public.caps.i2c_speed_in_khz = 40;
drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+1 -1
View File
@@ -1243,7 +1243,7 @@ static bool construct(
/*************************************************
* Resource + asic cap harcoding *
*************************************************/
pool->base.underlay_pipe_index = -1;
pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
dc->public.caps.max_downscale_ratio = 200;
dc->public.caps.i2c_speed_in_khz = 100;
drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+1 -1
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@@ -931,7 +931,7 @@ static bool construct(
/*************************************************
* Resource + asic cap harcoding *
*************************************************/
pool->base.underlay_pipe_index = -1;
pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
pool->base.pipe_count = res_cap.num_timing_generator;
dc->public.caps.max_downscale_ratio = 200;
dc->public.caps.i2c_speed_in_khz = 40;
drivers/gpu/drm/amd/display/dc/inc/core_types.h
+2
View File
@@ -230,6 +230,8 @@ struct audio_support{
bool hdmi_audio_native;
};
#define NO_UNDERLAY_PIPE -1
struct resource_pool {
struct mem_input *mis[MAX_PIPES];
struct input_pixel_processor *ipps[MAX_PIPES];