Merge tag 'dmaengine-6.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine
Pull dmaengine updates from Vinod Koul: "A couple of new device support and small driver updates for this round. New support: - Intel idxd Wildcat Lake family support - SpacemiT K1 PDMA controller support - Renesas RZ/G3E family support Updates: - Xilinx shutdown support and dma client properties update - Designware edma callback_result support" * tag 'dmaengine-6.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: dt-bindings: dma: rz-dmac: Document RZ/G3E family of SoCs dmaengine: dw-edma: Set status for callback_result dmaengine: mv_xor: match alloc_wc and free_wc dmaengine: mmp_pdma: Add SpacemiT K1 PDMA support with 64-bit addressing dmaengine: mmp_pdma: Add operations structure for controller abstraction dmaengine: mmp_pdma: Add reset controller support dmaengine: mmp_pdma: Add clock support dt-bindings: dma: Add SpacemiT K1 PDMA controller dt-bindings: dmaengine: xilinx_dma: Remove DMA client properties dmaengine: Fix dma_async_tx_descriptor->tx_submit documentation dmaengine: xilinx_dma: Support descriptor setup from dma_vecs dmaengine: sh: setup_xref error handling dmaengine: Replace zero-length array with flexible-array dmaengine: ppc4xx: Remove space before newline dmaengine: idxd: Add a new IAA device ID for Wildcat Lake family platforms dmaengine: idxd: Replace memset(0) + strscpy() with strscpy_pad() dt-bindings: dma: nvidia,tegra20-apbdma: Add undocumented compatibles and "clock-names" dmaengine: zynqmp_dma: Add shutdown operation support
This commit is contained in:
Linus Torvalds
@@ -18,10 +18,17 @@ maintainers:
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properties:
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compatible:
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oneOf:
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- const: nvidia,tegra20-apbdma
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- enum:
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- nvidia,tegra114-apbdma
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- nvidia,tegra20-apbdma
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- items:
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- const: nvidia,tegra30-apbdma
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- const: nvidia,tegra20-apbdma
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- items:
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- enum:
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- nvidia,tegra124-apbdma
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- nvidia,tegra210-apbdma
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- const: nvidia,tegra148-apbdma
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reg:
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maxItems: 1
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@@ -32,6 +39,9 @@ properties:
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clocks:
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maxItems: 1
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clock-names:
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const: dma
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interrupts:
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description:
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Should contain all of the per-channel DMA interrupts in
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@@ -21,6 +21,11 @@ properties:
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- renesas,r9a08g045-dmac # RZ/G3S
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- const: renesas,rz-dmac
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- items:
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- enum:
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- renesas,r9a09g047-dmac # RZ/G3E
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- const: renesas,r9a09g057-dmac
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- const: renesas,r9a09g057-dmac # RZ/V2H(P)
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reg:
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@@ -0,0 +1,68 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/dma/spacemit,k1-pdma.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: SpacemiT K1 PDMA Controller
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maintainers:
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- Guodong Xu <guodong@riscstar.com>
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allOf:
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- $ref: dma-controller.yaml#
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properties:
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compatible:
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const: spacemit,k1-pdma
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reg:
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maxItems: 1
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interrupts:
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description: Shared interrupt for all DMA channels
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maxItems: 1
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clocks:
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maxItems: 1
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resets:
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maxItems: 1
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dma-channels:
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maximum: 16
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'#dma-cells':
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const: 1
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description:
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The DMA request number for the peripheral device.
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- resets
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- dma-channels
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- '#dma-cells'
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/spacemit,k1-syscon.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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dma-controller@d4000000 {
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compatible = "spacemit,k1-pdma";
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reg = <0x0 0xd4000000 0x0 0x4000>;
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interrupts = <72>;
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clocks = <&syscon_apmu CLK_DMA>;
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resets = <&syscon_apmu RESET_DMA>;
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dma-channels = <16>;
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#dma-cells = <1>;
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};
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};
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@@ -109,26 +109,3 @@ axi_vdma_0: axivdma@40030000 {
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xlnx,datawidth = <0x40>;
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} ;
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} ;
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* DMA client
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Required properties:
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- dmas: a list of <[Video DMA device phandle] [Channel ID]> pairs,
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where Channel ID is '0' for write/tx and '1' for read/rx
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channel. For MCMDA, MM2S channel(write/tx) ID start from
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'0' and is in [0-15] range. S2MM channel(read/rx) ID start
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from '16' and is in [16-31] range. These channels ID are
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fixed irrespective of IP configuration.
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- dma-names: a list of DMA channel names, one per "dmas" entry
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Example:
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++++++++
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vdmatest_0: vdmatest@0 {
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compatible ="xlnx,axi-vdma-test-1.00.a";
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dmas = <&axi_vdma_0 0
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&axi_vdma_0 1>;
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dma-names = "vdma0", "vdma1";
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} ;
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+1
-1
@@ -450,7 +450,7 @@ config MILBEAUT_XDMAC
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config MMP_PDMA
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tristate "MMP PDMA support"
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depends on ARCH_MMP || ARCH_PXA || COMPILE_TEST
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depends on ARCH_MMP || ARCH_PXA || ARCH_SPACEMIT || COMPILE_TEST
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select DMA_ENGINE
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help
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Support the MMP PDMA engine for PXA and MMP platform.
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@@ -584,6 +584,25 @@ dw_edma_device_prep_interleaved_dma(struct dma_chan *dchan,
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return dw_edma_device_transfer(&xfer);
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}
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static void dw_hdma_set_callback_result(struct virt_dma_desc *vd,
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enum dmaengine_tx_result result)
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{
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u32 residue = 0;
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struct dw_edma_desc *desc;
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struct dmaengine_result *res;
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if (!vd->tx.callback_result)
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return;
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desc = vd2dw_edma_desc(vd);
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if (desc)
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residue = desc->alloc_sz - desc->xfer_sz;
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res = &vd->tx_result;
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res->result = result;
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res->residue = residue;
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}
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static void dw_edma_done_interrupt(struct dw_edma_chan *chan)
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{
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struct dw_edma_desc *desc;
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@@ -597,6 +616,8 @@ static void dw_edma_done_interrupt(struct dw_edma_chan *chan)
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case EDMA_REQ_NONE:
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desc = vd2dw_edma_desc(vd);
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if (!desc->chunks_alloc) {
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dw_hdma_set_callback_result(vd,
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DMA_TRANS_NOERROR);
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list_del(&vd->node);
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vchan_cookie_complete(vd);
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}
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@@ -633,6 +654,7 @@ static void dw_edma_abort_interrupt(struct dw_edma_chan *chan)
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spin_lock_irqsave(&chan->vc.lock, flags);
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vd = vchan_next_desc(&chan->vc);
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if (vd) {
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dw_hdma_set_callback_result(vd, DMA_TRANS_ABORTED);
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list_del(&vd->node);
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vchan_cookie_complete(vd);
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}
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@@ -36,12 +36,10 @@ int idxd_load_iaa_device_defaults(struct idxd_device *idxd)
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group->num_wqs++;
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/* set name to "iaa_crypto" */
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memset(wq->name, 0, WQ_NAME_SIZE + 1);
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strscpy(wq->name, "iaa_crypto", WQ_NAME_SIZE + 1);
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strscpy_pad(wq->name, "iaa_crypto");
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/* set driver_name to "crypto" */
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memset(wq->driver_name, 0, DRIVER_NAME_SIZE + 1);
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strscpy(wq->driver_name, "crypto", DRIVER_NAME_SIZE + 1);
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strscpy_pad(wq->driver_name, "crypto");
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engine = idxd->engines[0];
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@@ -80,6 +80,8 @@ static struct pci_device_id idxd_pci_tbl[] = {
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{ PCI_DEVICE_DATA(INTEL, IAA_DMR, &idxd_driver_data[IDXD_TYPE_IAX]) },
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/* IAA PTL platforms */
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{ PCI_DEVICE_DATA(INTEL, IAA_PTL, &idxd_driver_data[IDXD_TYPE_IAX]) },
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/* IAA WCL platforms */
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{ PCI_DEVICE_DATA(INTEL, IAA_WCL, &idxd_driver_data[IDXD_TYPE_IAX]) },
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{ 0, }
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};
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MODULE_DEVICE_TABLE(pci, idxd_pci_tbl);
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@@ -14,6 +14,7 @@
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#define PCI_DEVICE_ID_INTEL_DSA_DMR 0x1212
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#define PCI_DEVICE_ID_INTEL_IAA_DMR 0x1216
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#define PCI_DEVICE_ID_INTEL_IAA_PTL 0xb02d
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#define PCI_DEVICE_ID_INTEL_IAA_WCL 0xfd2d
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#define DEVICE_VERSION_1 0x100
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#define DEVICE_VERSION_2 0x200
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@@ -256,7 +256,7 @@ struct sdma_script_start_addrs {
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/* End of v3 array */
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union { s32 v3_end; s32 mcu_2_zqspi_addr; };
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/* End of v4 array */
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s32 v4_end[0];
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s32 v4_end[];
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};
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/*
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+256
-37
@@ -15,6 +15,8 @@
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#include <linux/device.h>
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#include <linux/platform_data/mmp_dma.h>
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#include <linux/dmapool.h>
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#include <linux/clk.h>
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#include <linux/reset.h>
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#include <linux/of_dma.h>
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#include <linux/of.h>
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@@ -23,9 +25,12 @@
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#define DCSR 0x0000
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#define DALGN 0x00a0
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#define DINT 0x00f0
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#define DDADR 0x0200
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#define DDADR(n) (0x0200 + ((n) << 4))
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#define DSADR(n) (0x0204 + ((n) << 4))
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#define DTADR(n) (0x0208 + ((n) << 4))
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#define DDADRH(n) (0x0300 + ((n) << 4))
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#define DSADRH(n) (0x0304 + ((n) << 4))
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#define DTADRH(n) (0x0308 + ((n) << 4))
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#define DCMD 0x020c
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#define DCSR_RUN BIT(31) /* Run Bit (read / write) */
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@@ -42,6 +47,7 @@
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#define DCSR_EORSTOPEN BIT(26) /* STOP on an EOR */
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#define DCSR_SETCMPST BIT(25) /* Set Descriptor Compare Status */
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#define DCSR_CLRCMPST BIT(24) /* Clear Descriptor Compare Status */
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#define DCSR_LPAEEN BIT(21) /* Long Physical Address Extension Enable */
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#define DCSR_CMPST BIT(10) /* The Descriptor Compare Status */
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#define DCSR_EORINTR BIT(9) /* The end of Receive */
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@@ -74,6 +80,16 @@ struct mmp_pdma_desc_hw {
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u32 dsadr; /* DSADR value for the current transfer */
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u32 dtadr; /* DTADR value for the current transfer */
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u32 dcmd; /* DCMD value for the current transfer */
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/*
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* The following 32-bit words are only used in the 64-bit, ie.
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* LPAE (Long Physical Address Extension) mode.
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* They are used to specify the high 32 bits of the descriptor's
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* addresses.
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*/
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u32 ddadrh; /* High 32-bit of DDADR */
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u32 dsadrh; /* High 32-bit of DSADR */
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u32 dtadrh; /* High 32-bit of DTADR */
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u32 rsvd; /* reserved */
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} __aligned(32);
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struct mmp_pdma_desc_sw {
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@@ -118,12 +134,55 @@ struct mmp_pdma_phy {
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struct mmp_pdma_chan *vchan;
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};
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/**
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* struct mmp_pdma_ops - Operations for the MMP PDMA controller
|
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*
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* Hardware Register Operations (read/write hardware registers):
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* @write_next_addr: Function to program address of next descriptor into
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* DDADR/DDADRH
|
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* @read_src_addr: Function to read the source address from DSADR/DSADRH
|
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* @read_dst_addr: Function to read the destination address from DTADR/DTADRH
|
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*
|
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* Descriptor Memory Operations (manipulate descriptor structs in memory):
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* @set_desc_next_addr: Function to set next descriptor address in descriptor
|
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* @set_desc_src_addr: Function to set the source address in descriptor
|
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* @set_desc_dst_addr: Function to set the destination address in descriptor
|
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* @get_desc_src_addr: Function to get the source address from descriptor
|
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* @get_desc_dst_addr: Function to get the destination address from descriptor
|
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*
|
||||
* Controller Configuration:
|
||||
* @run_bits: Control bits in DCSR register for channel start/stop
|
||||
* @dma_mask: DMA addressing capability of controller. 0 to use OF/platform
|
||||
* settings, or explicit mask like DMA_BIT_MASK(32/64)
|
||||
*/
|
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struct mmp_pdma_ops {
|
||||
/* Hardware Register Operations */
|
||||
void (*write_next_addr)(struct mmp_pdma_phy *phy, dma_addr_t addr);
|
||||
u64 (*read_src_addr)(struct mmp_pdma_phy *phy);
|
||||
u64 (*read_dst_addr)(struct mmp_pdma_phy *phy);
|
||||
|
||||
/* Descriptor Memory Operations */
|
||||
void (*set_desc_next_addr)(struct mmp_pdma_desc_hw *desc,
|
||||
dma_addr_t addr);
|
||||
void (*set_desc_src_addr)(struct mmp_pdma_desc_hw *desc,
|
||||
dma_addr_t addr);
|
||||
void (*set_desc_dst_addr)(struct mmp_pdma_desc_hw *desc,
|
||||
dma_addr_t addr);
|
||||
u64 (*get_desc_src_addr)(const struct mmp_pdma_desc_hw *desc);
|
||||
u64 (*get_desc_dst_addr)(const struct mmp_pdma_desc_hw *desc);
|
||||
|
||||
/* Controller Configuration */
|
||||
u32 run_bits;
|
||||
u64 dma_mask;
|
||||
};
|
||||
|
||||
struct mmp_pdma_device {
|
||||
int dma_channels;
|
||||
void __iomem *base;
|
||||
struct device *dev;
|
||||
struct dma_device device;
|
||||
struct mmp_pdma_phy *phy;
|
||||
const struct mmp_pdma_ops *ops;
|
||||
spinlock_t phy_lock; /* protect alloc/free phy channels */
|
||||
};
|
||||
|
||||
@@ -136,24 +195,112 @@ struct mmp_pdma_device {
|
||||
#define to_mmp_pdma_dev(dmadev) \
|
||||
container_of(dmadev, struct mmp_pdma_device, device)
|
||||
|
||||
static int mmp_pdma_config_write(struct dma_chan *dchan,
|
||||
struct dma_slave_config *cfg,
|
||||
enum dma_transfer_direction direction);
|
||||
|
||||
static void set_desc(struct mmp_pdma_phy *phy, dma_addr_t addr)
|
||||
/* For 32-bit PDMA */
|
||||
static void write_next_addr_32(struct mmp_pdma_phy *phy, dma_addr_t addr)
|
||||
{
|
||||
u32 reg = (phy->idx << 4) + DDADR;
|
||||
|
||||
writel(addr, phy->base + reg);
|
||||
writel(addr, phy->base + DDADR(phy->idx));
|
||||
}
|
||||
|
||||
static u64 read_src_addr_32(struct mmp_pdma_phy *phy)
|
||||
{
|
||||
return readl(phy->base + DSADR(phy->idx));
|
||||
}
|
||||
|
||||
static u64 read_dst_addr_32(struct mmp_pdma_phy *phy)
|
||||
{
|
||||
return readl(phy->base + DTADR(phy->idx));
|
||||
}
|
||||
|
||||
static void set_desc_next_addr_32(struct mmp_pdma_desc_hw *desc, dma_addr_t addr)
|
||||
{
|
||||
desc->ddadr = addr;
|
||||
}
|
||||
|
||||
static void set_desc_src_addr_32(struct mmp_pdma_desc_hw *desc, dma_addr_t addr)
|
||||
{
|
||||
desc->dsadr = addr;
|
||||
}
|
||||
|
||||
static void set_desc_dst_addr_32(struct mmp_pdma_desc_hw *desc, dma_addr_t addr)
|
||||
{
|
||||
desc->dtadr = addr;
|
||||
}
|
||||
|
||||
static u64 get_desc_src_addr_32(const struct mmp_pdma_desc_hw *desc)
|
||||
{
|
||||
return desc->dsadr;
|
||||
}
|
||||
|
||||
static u64 get_desc_dst_addr_32(const struct mmp_pdma_desc_hw *desc)
|
||||
{
|
||||
return desc->dtadr;
|
||||
}
|
||||
|
||||
/* For 64-bit PDMA */
|
||||
static void write_next_addr_64(struct mmp_pdma_phy *phy, dma_addr_t addr)
|
||||
{
|
||||
writel(lower_32_bits(addr), phy->base + DDADR(phy->idx));
|
||||
writel(upper_32_bits(addr), phy->base + DDADRH(phy->idx));
|
||||
}
|
||||
|
||||
static u64 read_src_addr_64(struct mmp_pdma_phy *phy)
|
||||
{
|
||||
u32 low = readl(phy->base + DSADR(phy->idx));
|
||||
u32 high = readl(phy->base + DSADRH(phy->idx));
|
||||
|
||||
return ((u64)high << 32) | low;
|
||||
}
|
||||
|
||||
static u64 read_dst_addr_64(struct mmp_pdma_phy *phy)
|
||||
{
|
||||
u32 low = readl(phy->base + DTADR(phy->idx));
|
||||
u32 high = readl(phy->base + DTADRH(phy->idx));
|
||||
|
||||
return ((u64)high << 32) | low;
|
||||
}
|
||||
|
||||
static void set_desc_next_addr_64(struct mmp_pdma_desc_hw *desc, dma_addr_t addr)
|
||||
{
|
||||
desc->ddadr = lower_32_bits(addr);
|
||||
desc->ddadrh = upper_32_bits(addr);
|
||||
}
|
||||
|
||||
static void set_desc_src_addr_64(struct mmp_pdma_desc_hw *desc, dma_addr_t addr)
|
||||
{
|
||||
desc->dsadr = lower_32_bits(addr);
|
||||
desc->dsadrh = upper_32_bits(addr);
|
||||
}
|
||||
|
||||
static void set_desc_dst_addr_64(struct mmp_pdma_desc_hw *desc, dma_addr_t addr)
|
||||
{
|
||||
desc->dtadr = lower_32_bits(addr);
|
||||
desc->dtadrh = upper_32_bits(addr);
|
||||
}
|
||||
|
||||
static u64 get_desc_src_addr_64(const struct mmp_pdma_desc_hw *desc)
|
||||
{
|
||||
return ((u64)desc->dsadrh << 32) | desc->dsadr;
|
||||
}
|
||||
|
||||
static u64 get_desc_dst_addr_64(const struct mmp_pdma_desc_hw *desc)
|
||||
{
|
||||
return ((u64)desc->dtadrh << 32) | desc->dtadr;
|
||||
}
|
||||
|
||||
static int mmp_pdma_config_write(struct dma_chan *dchan,
|
||||
struct dma_slave_config *cfg,
|
||||
enum dma_transfer_direction direction);
|
||||
|
||||
static void enable_chan(struct mmp_pdma_phy *phy)
|
||||
{
|
||||
u32 reg, dalgn;
|
||||
struct mmp_pdma_device *pdev;
|
||||
|
||||
if (!phy->vchan)
|
||||
return;
|
||||
|
||||
pdev = to_mmp_pdma_dev(phy->vchan->chan.device);
|
||||
|
||||
reg = DRCMR(phy->vchan->drcmr);
|
||||
writel(DRCMR_MAPVLD | phy->idx, phy->base + reg);
|
||||
|
||||
@@ -165,18 +312,29 @@ static void enable_chan(struct mmp_pdma_phy *phy)
|
||||
writel(dalgn, phy->base + DALGN);
|
||||
|
||||
reg = (phy->idx << 2) + DCSR;
|
||||
writel(readl(phy->base + reg) | DCSR_RUN, phy->base + reg);
|
||||
writel(readl(phy->base + reg) | pdev->ops->run_bits,
|
||||
phy->base + reg);
|
||||
}
|
||||
|
||||
static void disable_chan(struct mmp_pdma_phy *phy)
|
||||
{
|
||||
u32 reg;
|
||||
u32 reg, dcsr;
|
||||
|
||||
if (!phy)
|
||||
return;
|
||||
|
||||
reg = (phy->idx << 2) + DCSR;
|
||||
writel(readl(phy->base + reg) & ~DCSR_RUN, phy->base + reg);
|
||||
dcsr = readl(phy->base + reg);
|
||||
|
||||
if (phy->vchan) {
|
||||
struct mmp_pdma_device *pdev;
|
||||
|
||||
pdev = to_mmp_pdma_dev(phy->vchan->chan.device);
|
||||
writel(dcsr & ~pdev->ops->run_bits, phy->base + reg);
|
||||
} else {
|
||||
/* If no vchan, just clear the RUN bit */
|
||||
writel(dcsr & ~DCSR_RUN, phy->base + reg);
|
||||
}
|
||||
}
|
||||
|
||||
static int clear_chan_irq(struct mmp_pdma_phy *phy)
|
||||
@@ -295,6 +453,7 @@ static void mmp_pdma_free_phy(struct mmp_pdma_chan *pchan)
|
||||
static void start_pending_queue(struct mmp_pdma_chan *chan)
|
||||
{
|
||||
struct mmp_pdma_desc_sw *desc;
|
||||
struct mmp_pdma_device *pdev = to_mmp_pdma_dev(chan->chan.device);
|
||||
|
||||
/* still in running, irq will start the pending list */
|
||||
if (!chan->idle) {
|
||||
@@ -329,7 +488,7 @@ static void start_pending_queue(struct mmp_pdma_chan *chan)
|
||||
* Program the descriptor's address into the DMA controller,
|
||||
* then start the DMA transaction
|
||||
*/
|
||||
set_desc(chan->phy, desc->async_tx.phys);
|
||||
pdev->ops->write_next_addr(chan->phy, desc->async_tx.phys);
|
||||
enable_chan(chan->phy);
|
||||
chan->idle = false;
|
||||
}
|
||||
@@ -445,15 +604,14 @@ mmp_pdma_prep_memcpy(struct dma_chan *dchan,
|
||||
size_t len, unsigned long flags)
|
||||
{
|
||||
struct mmp_pdma_chan *chan;
|
||||
struct mmp_pdma_device *pdev;
|
||||
struct mmp_pdma_desc_sw *first = NULL, *prev = NULL, *new;
|
||||
size_t copy = 0;
|
||||
|
||||
if (!dchan)
|
||||
return NULL;
|
||||
|
||||
if (!len)
|
||||
if (!dchan || !len)
|
||||
return NULL;
|
||||
|
||||
pdev = to_mmp_pdma_dev(dchan->device);
|
||||
chan = to_mmp_pdma_chan(dchan);
|
||||
chan->byte_align = false;
|
||||
|
||||
@@ -476,13 +634,14 @@ mmp_pdma_prep_memcpy(struct dma_chan *dchan,
|
||||
chan->byte_align = true;
|
||||
|
||||
new->desc.dcmd = chan->dcmd | (DCMD_LENGTH & copy);
|
||||
new->desc.dsadr = dma_src;
|
||||
new->desc.dtadr = dma_dst;
|
||||
pdev->ops->set_desc_src_addr(&new->desc, dma_src);
|
||||
pdev->ops->set_desc_dst_addr(&new->desc, dma_dst);
|
||||
|
||||
if (!first)
|
||||
first = new;
|
||||
else
|
||||
prev->desc.ddadr = new->async_tx.phys;
|
||||
pdev->ops->set_desc_next_addr(&prev->desc,
|
||||
new->async_tx.phys);
|
||||
|
||||
new->async_tx.cookie = 0;
|
||||
async_tx_ack(&new->async_tx);
|
||||
@@ -526,6 +685,7 @@ mmp_pdma_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl,
|
||||
unsigned long flags, void *context)
|
||||
{
|
||||
struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan);
|
||||
struct mmp_pdma_device *pdev = to_mmp_pdma_dev(dchan->device);
|
||||
struct mmp_pdma_desc_sw *first = NULL, *prev = NULL, *new = NULL;
|
||||
size_t len, avail;
|
||||
struct scatterlist *sg;
|
||||
@@ -557,17 +717,18 @@ mmp_pdma_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl,
|
||||
|
||||
new->desc.dcmd = chan->dcmd | (DCMD_LENGTH & len);
|
||||
if (dir == DMA_MEM_TO_DEV) {
|
||||
new->desc.dsadr = addr;
|
||||
pdev->ops->set_desc_src_addr(&new->desc, addr);
|
||||
new->desc.dtadr = chan->dev_addr;
|
||||
} else {
|
||||
new->desc.dsadr = chan->dev_addr;
|
||||
new->desc.dtadr = addr;
|
||||
pdev->ops->set_desc_dst_addr(&new->desc, addr);
|
||||
}
|
||||
|
||||
if (!first)
|
||||
first = new;
|
||||
else
|
||||
prev->desc.ddadr = new->async_tx.phys;
|
||||
pdev->ops->set_desc_next_addr(&prev->desc,
|
||||
new->async_tx.phys);
|
||||
|
||||
new->async_tx.cookie = 0;
|
||||
async_tx_ack(&new->async_tx);
|
||||
@@ -607,12 +768,15 @@ mmp_pdma_prep_dma_cyclic(struct dma_chan *dchan,
|
||||
unsigned long flags)
|
||||
{
|
||||
struct mmp_pdma_chan *chan;
|
||||
struct mmp_pdma_device *pdev;
|
||||
struct mmp_pdma_desc_sw *first = NULL, *prev = NULL, *new;
|
||||
dma_addr_t dma_src, dma_dst;
|
||||
|
||||
if (!dchan || !len || !period_len)
|
||||
return NULL;
|
||||
|
||||
pdev = to_mmp_pdma_dev(dchan->device);
|
||||
|
||||
/* the buffer length must be a multiple of period_len */
|
||||
if (len % period_len != 0)
|
||||
return NULL;
|
||||
@@ -649,13 +813,14 @@ mmp_pdma_prep_dma_cyclic(struct dma_chan *dchan,
|
||||
|
||||
new->desc.dcmd = (chan->dcmd | DCMD_ENDIRQEN |
|
||||
(DCMD_LENGTH & period_len));
|
||||
new->desc.dsadr = dma_src;
|
||||
new->desc.dtadr = dma_dst;
|
||||
pdev->ops->set_desc_src_addr(&new->desc, dma_src);
|
||||
pdev->ops->set_desc_dst_addr(&new->desc, dma_dst);
|
||||
|
||||
if (!first)
|
||||
first = new;
|
||||
else
|
||||
prev->desc.ddadr = new->async_tx.phys;
|
||||
pdev->ops->set_desc_next_addr(&prev->desc,
|
||||
new->async_tx.phys);
|
||||
|
||||
new->async_tx.cookie = 0;
|
||||
async_tx_ack(&new->async_tx);
|
||||
@@ -676,7 +841,7 @@ mmp_pdma_prep_dma_cyclic(struct dma_chan *dchan,
|
||||
first->async_tx.cookie = -EBUSY;
|
||||
|
||||
/* make the cyclic link */
|
||||
new->desc.ddadr = first->async_tx.phys;
|
||||
pdev->ops->set_desc_next_addr(&new->desc, first->async_tx.phys);
|
||||
chan->cyclic_first = first;
|
||||
|
||||
return &first->async_tx;
|
||||
@@ -762,7 +927,9 @@ static unsigned int mmp_pdma_residue(struct mmp_pdma_chan *chan,
|
||||
dma_cookie_t cookie)
|
||||
{
|
||||
struct mmp_pdma_desc_sw *sw;
|
||||
u32 curr, residue = 0;
|
||||
struct mmp_pdma_device *pdev = to_mmp_pdma_dev(chan->chan.device);
|
||||
u64 curr;
|
||||
u32 residue = 0;
|
||||
bool passed = false;
|
||||
bool cyclic = chan->cyclic_first != NULL;
|
||||
|
||||
@@ -774,17 +941,18 @@ static unsigned int mmp_pdma_residue(struct mmp_pdma_chan *chan,
|
||||
return 0;
|
||||
|
||||
if (chan->dir == DMA_DEV_TO_MEM)
|
||||
curr = readl(chan->phy->base + DTADR(chan->phy->idx));
|
||||
curr = pdev->ops->read_dst_addr(chan->phy);
|
||||
else
|
||||
curr = readl(chan->phy->base + DSADR(chan->phy->idx));
|
||||
curr = pdev->ops->read_src_addr(chan->phy);
|
||||
|
||||
list_for_each_entry(sw, &chan->chain_running, node) {
|
||||
u32 start, end, len;
|
||||
u64 start, end;
|
||||
u32 len;
|
||||
|
||||
if (chan->dir == DMA_DEV_TO_MEM)
|
||||
start = sw->desc.dtadr;
|
||||
start = pdev->ops->get_desc_dst_addr(&sw->desc);
|
||||
else
|
||||
start = sw->desc.dsadr;
|
||||
start = pdev->ops->get_desc_src_addr(&sw->desc);
|
||||
|
||||
len = sw->desc.dcmd & DCMD_LENGTH;
|
||||
end = start + len;
|
||||
@@ -800,7 +968,7 @@ static unsigned int mmp_pdma_residue(struct mmp_pdma_chan *chan,
|
||||
if (passed) {
|
||||
residue += len;
|
||||
} else if (curr >= start && curr <= end) {
|
||||
residue += end - curr;
|
||||
residue += (u32)(end - curr);
|
||||
passed = true;
|
||||
}
|
||||
|
||||
@@ -994,9 +1162,42 @@ static int mmp_pdma_chan_init(struct mmp_pdma_device *pdev, int idx, int irq)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct mmp_pdma_ops marvell_pdma_v1_ops = {
|
||||
.write_next_addr = write_next_addr_32,
|
||||
.read_src_addr = read_src_addr_32,
|
||||
.read_dst_addr = read_dst_addr_32,
|
||||
.set_desc_next_addr = set_desc_next_addr_32,
|
||||
.set_desc_src_addr = set_desc_src_addr_32,
|
||||
.set_desc_dst_addr = set_desc_dst_addr_32,
|
||||
.get_desc_src_addr = get_desc_src_addr_32,
|
||||
.get_desc_dst_addr = get_desc_dst_addr_32,
|
||||
.run_bits = (DCSR_RUN),
|
||||
.dma_mask = 0, /* let OF/platform set DMA mask */
|
||||
};
|
||||
|
||||
static const struct mmp_pdma_ops spacemit_k1_pdma_ops = {
|
||||
.write_next_addr = write_next_addr_64,
|
||||
.read_src_addr = read_src_addr_64,
|
||||
.read_dst_addr = read_dst_addr_64,
|
||||
.set_desc_next_addr = set_desc_next_addr_64,
|
||||
.set_desc_src_addr = set_desc_src_addr_64,
|
||||
.set_desc_dst_addr = set_desc_dst_addr_64,
|
||||
.get_desc_src_addr = get_desc_src_addr_64,
|
||||
.get_desc_dst_addr = get_desc_dst_addr_64,
|
||||
.run_bits = (DCSR_RUN | DCSR_LPAEEN),
|
||||
.dma_mask = DMA_BIT_MASK(64), /* force 64-bit DMA addr capability */
|
||||
};
|
||||
|
||||
static const struct of_device_id mmp_pdma_dt_ids[] = {
|
||||
{ .compatible = "marvell,pdma-1.0", },
|
||||
{}
|
||||
{
|
||||
.compatible = "marvell,pdma-1.0",
|
||||
.data = &marvell_pdma_v1_ops
|
||||
}, {
|
||||
.compatible = "spacemit,k1-pdma",
|
||||
.data = &spacemit_k1_pdma_ops
|
||||
}, {
|
||||
/* sentinel */
|
||||
}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, mmp_pdma_dt_ids);
|
||||
|
||||
@@ -1019,6 +1220,8 @@ static int mmp_pdma_probe(struct platform_device *op)
|
||||
{
|
||||
struct mmp_pdma_device *pdev;
|
||||
struct mmp_dma_platdata *pdata = dev_get_platdata(&op->dev);
|
||||
struct clk *clk;
|
||||
struct reset_control *rst;
|
||||
int i, ret, irq = 0;
|
||||
int dma_channels = 0, irq_num = 0;
|
||||
const enum dma_slave_buswidth widths =
|
||||
@@ -1037,6 +1240,19 @@ static int mmp_pdma_probe(struct platform_device *op)
|
||||
if (IS_ERR(pdev->base))
|
||||
return PTR_ERR(pdev->base);
|
||||
|
||||
clk = devm_clk_get_optional_enabled(pdev->dev, NULL);
|
||||
if (IS_ERR(clk))
|
||||
return PTR_ERR(clk);
|
||||
|
||||
rst = devm_reset_control_get_optional_exclusive_deasserted(pdev->dev,
|
||||
NULL);
|
||||
if (IS_ERR(rst))
|
||||
return PTR_ERR(rst);
|
||||
|
||||
pdev->ops = of_device_get_match_data(&op->dev);
|
||||
if (!pdev->ops)
|
||||
return -ENODEV;
|
||||
|
||||
if (pdev->dev->of_node) {
|
||||
/* Parse new and deprecated dma-channels properties */
|
||||
if (of_property_read_u32(pdev->dev->of_node, "dma-channels",
|
||||
@@ -1098,7 +1314,10 @@ static int mmp_pdma_probe(struct platform_device *op)
|
||||
pdev->device.directions = BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM);
|
||||
pdev->device.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
|
||||
|
||||
if (pdev->dev->coherent_dma_mask)
|
||||
/* Set DMA mask based on ops->dma_mask, or OF/platform */
|
||||
if (pdev->ops->dma_mask)
|
||||
dma_set_mask(pdev->dev, pdev->ops->dma_mask);
|
||||
else if (pdev->dev->coherent_dma_mask)
|
||||
dma_set_mask(pdev->dev, pdev->dev->coherent_dma_mask);
|
||||
else
|
||||
dma_set_mask(pdev->dev, DMA_BIT_MASK(64));
|
||||
|
||||
@@ -1013,7 +1013,7 @@ static int mv_xor_channel_remove(struct mv_xor_chan *mv_chan)
|
||||
|
||||
dma_async_device_unregister(&mv_chan->dmadev);
|
||||
|
||||
dma_free_coherent(dev, MV_XOR_POOL_SIZE,
|
||||
dma_free_wc(dev, MV_XOR_POOL_SIZE,
|
||||
mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool);
|
||||
dma_unmap_single(dev, mv_chan->dummy_src_addr,
|
||||
MV_XOR_MIN_BYTE_COUNT, DMA_FROM_DEVICE);
|
||||
@@ -1163,7 +1163,7 @@ mv_xor_channel_add(struct mv_xor_device *xordev,
|
||||
err_free_irq:
|
||||
free_irq(mv_chan->irq, mv_chan);
|
||||
err_free_dma:
|
||||
dma_free_coherent(&pdev->dev, MV_XOR_POOL_SIZE,
|
||||
dma_free_wc(&pdev->dev, MV_XOR_POOL_SIZE,
|
||||
mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool);
|
||||
err_unmap_dst:
|
||||
dma_unmap_single(dma_dev->dev, mv_chan->dummy_dst_addr,
|
||||
|
||||
@@ -874,7 +874,7 @@ static int ppc440spe_dma2_pq_slot_count(dma_addr_t *srcs,
|
||||
pr_err("%s: src_cnt=%d, state=%d, addr_count=%d, order=%lld\n",
|
||||
__func__, src_cnt, state, addr_count, order);
|
||||
for (i = 0; i < src_cnt; i++)
|
||||
pr_err("\t[%d] 0x%llx \n", i, srcs[i]);
|
||||
pr_err("\t[%d] 0x%llx\n", i, srcs[i]);
|
||||
BUG();
|
||||
}
|
||||
|
||||
@@ -3636,7 +3636,7 @@ static void ppc440spe_adma_issue_pending(struct dma_chan *chan)
|
||||
|
||||
ppc440spe_chan = to_ppc440spe_adma_chan(chan);
|
||||
dev_dbg(ppc440spe_chan->device->common.dev,
|
||||
"ppc440spe adma%d: %s %d \n", ppc440spe_chan->device->id,
|
||||
"ppc440spe adma%d: %s %d\n", ppc440spe_chan->device->id,
|
||||
__func__, ppc440spe_chan->pending);
|
||||
|
||||
if (ppc440spe_chan->pending) {
|
||||
|
||||
@@ -129,12 +129,25 @@ static dma_cookie_t shdma_tx_submit(struct dma_async_tx_descriptor *tx)
|
||||
const struct shdma_ops *ops = sdev->ops;
|
||||
dev_dbg(schan->dev, "Bring up channel %d\n",
|
||||
schan->id);
|
||||
/*
|
||||
* TODO: .xfer_setup() might fail on some platforms.
|
||||
* Make it int then, on error remove chunks from the
|
||||
* queue again
|
||||
*/
|
||||
ops->setup_xfer(schan, schan->slave_id);
|
||||
|
||||
ret = ops->setup_xfer(schan, schan->slave_id);
|
||||
if (ret < 0) {
|
||||
dev_err(schan->dev, "setup_xfer failed: %d\n", ret);
|
||||
|
||||
/* Remove chunks from the queue and mark them as idle */
|
||||
list_for_each_entry_safe(chunk, c, &schan->ld_queue, node) {
|
||||
if (chunk->cookie == cookie) {
|
||||
chunk->mark = DESC_IDLE;
|
||||
list_move(&chunk->node, &schan->ld_free);
|
||||
}
|
||||
}
|
||||
|
||||
schan->pm_state = SHDMA_PM_ESTABLISHED;
|
||||
ret = pm_runtime_put(schan->dev);
|
||||
|
||||
spin_unlock_irq(&schan->chan_lock);
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (schan->pm_state == SHDMA_PM_PENDING)
|
||||
shdma_chan_xfer_ld_queue(schan);
|
||||
|
||||
+13
-4
@@ -300,21 +300,30 @@ static bool sh_dmae_channel_busy(struct shdma_chan *schan)
|
||||
return dmae_is_busy(sh_chan);
|
||||
}
|
||||
|
||||
static void sh_dmae_setup_xfer(struct shdma_chan *schan,
|
||||
int slave_id)
|
||||
static int sh_dmae_setup_xfer(struct shdma_chan *schan, int slave_id)
|
||||
{
|
||||
struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
|
||||
shdma_chan);
|
||||
|
||||
int ret = 0;
|
||||
if (slave_id >= 0) {
|
||||
const struct sh_dmae_slave_config *cfg =
|
||||
sh_chan->config;
|
||||
|
||||
dmae_set_dmars(sh_chan, cfg->mid_rid);
|
||||
dmae_set_chcr(sh_chan, cfg->chcr);
|
||||
ret = dmae_set_dmars(sh_chan, cfg->mid_rid);
|
||||
if (ret < 0)
|
||||
goto END;
|
||||
|
||||
ret = dmae_set_chcr(sh_chan, cfg->chcr);
|
||||
if (ret < 0)
|
||||
goto END;
|
||||
|
||||
} else {
|
||||
dmae_init(sh_chan);
|
||||
}
|
||||
|
||||
END:
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
|
||||
@@ -2172,6 +2172,99 @@ error:
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/**
|
||||
* xilinx_dma_prep_peripheral_dma_vec - prepare descriptors for a DMA_SLAVE
|
||||
* transaction from DMA vectors
|
||||
* @dchan: DMA channel
|
||||
* @vecs: Array of DMA vectors that should be transferred
|
||||
* @nb: number of entries in @vecs
|
||||
* @direction: DMA direction
|
||||
* @flags: transfer ack flags
|
||||
*
|
||||
* Return: Async transaction descriptor on success and NULL on failure
|
||||
*/
|
||||
static struct dma_async_tx_descriptor *xilinx_dma_prep_peripheral_dma_vec(
|
||||
struct dma_chan *dchan, const struct dma_vec *vecs, size_t nb,
|
||||
enum dma_transfer_direction direction, unsigned long flags)
|
||||
{
|
||||
struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
|
||||
struct xilinx_dma_tx_descriptor *desc;
|
||||
struct xilinx_axidma_tx_segment *segment, *head, *prev = NULL;
|
||||
size_t copy;
|
||||
size_t sg_used;
|
||||
unsigned int i;
|
||||
|
||||
if (!is_slave_direction(direction) || direction != chan->direction)
|
||||
return NULL;
|
||||
|
||||
desc = xilinx_dma_alloc_tx_descriptor(chan);
|
||||
if (!desc)
|
||||
return NULL;
|
||||
|
||||
dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
|
||||
desc->async_tx.tx_submit = xilinx_dma_tx_submit;
|
||||
|
||||
/* Build transactions using information from DMA vectors */
|
||||
for (i = 0; i < nb; i++) {
|
||||
sg_used = 0;
|
||||
|
||||
/* Loop until the entire dma_vec entry is used */
|
||||
while (sg_used < vecs[i].len) {
|
||||
struct xilinx_axidma_desc_hw *hw;
|
||||
|
||||
/* Get a free segment */
|
||||
segment = xilinx_axidma_alloc_tx_segment(chan);
|
||||
if (!segment)
|
||||
goto error;
|
||||
|
||||
/*
|
||||
* Calculate the maximum number of bytes to transfer,
|
||||
* making sure it is less than the hw limit
|
||||
*/
|
||||
copy = xilinx_dma_calc_copysize(chan, vecs[i].len,
|
||||
sg_used);
|
||||
hw = &segment->hw;
|
||||
|
||||
/* Fill in the descriptor */
|
||||
xilinx_axidma_buf(chan, hw, vecs[i].addr, sg_used, 0);
|
||||
hw->control = copy;
|
||||
|
||||
if (prev)
|
||||
prev->hw.next_desc = segment->phys;
|
||||
|
||||
prev = segment;
|
||||
sg_used += copy;
|
||||
|
||||
/*
|
||||
* Insert the segment into the descriptor segments
|
||||
* list.
|
||||
*/
|
||||
list_add_tail(&segment->node, &desc->segments);
|
||||
}
|
||||
}
|
||||
|
||||
head = list_first_entry(&desc->segments, struct xilinx_axidma_tx_segment, node);
|
||||
desc->async_tx.phys = head->phys;
|
||||
|
||||
/* For the last DMA_MEM_TO_DEV transfer, set EOP */
|
||||
if (chan->direction == DMA_MEM_TO_DEV) {
|
||||
segment->hw.control |= XILINX_DMA_BD_SOP;
|
||||
segment = list_last_entry(&desc->segments,
|
||||
struct xilinx_axidma_tx_segment,
|
||||
node);
|
||||
segment->hw.control |= XILINX_DMA_BD_EOP;
|
||||
}
|
||||
|
||||
if (chan->xdev->has_axistream_connected)
|
||||
desc->async_tx.metadata_ops = &xilinx_dma_metadata_ops;
|
||||
|
||||
return &desc->async_tx;
|
||||
|
||||
error:
|
||||
xilinx_dma_free_tx_descriptor(chan, desc);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/**
|
||||
* xilinx_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction
|
||||
* @dchan: DMA channel
|
||||
@@ -3180,6 +3273,7 @@ static int xilinx_dma_probe(struct platform_device *pdev)
|
||||
xdev->common.device_config = xilinx_dma_device_config;
|
||||
if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
|
||||
dma_cap_set(DMA_CYCLIC, xdev->common.cap_mask);
|
||||
xdev->common.device_prep_peripheral_dma_vec = xilinx_dma_prep_peripheral_dma_vec;
|
||||
xdev->common.device_prep_slave_sg = xilinx_dma_prep_slave_sg;
|
||||
xdev->common.device_prep_dma_cyclic =
|
||||
xilinx_dma_prep_dma_cyclic;
|
||||
|
||||
@@ -1173,9 +1173,9 @@ static void zynqmp_dma_remove(struct platform_device *pdev)
|
||||
dma_async_device_unregister(&zdev->common);
|
||||
|
||||
zynqmp_dma_chan_remove(zdev->chan);
|
||||
pm_runtime_disable(zdev->dev);
|
||||
if (!pm_runtime_enabled(zdev->dev))
|
||||
if (pm_runtime_active(zdev->dev))
|
||||
zynqmp_dma_runtime_suspend(zdev->dev);
|
||||
pm_runtime_disable(zdev->dev);
|
||||
}
|
||||
|
||||
static const struct of_device_id zynqmp_dma_of_match[] = {
|
||||
@@ -1193,6 +1193,7 @@ static struct platform_driver zynqmp_dma_driver = {
|
||||
},
|
||||
.probe = zynqmp_dma_probe,
|
||||
.remove = zynqmp_dma_remove,
|
||||
.shutdown = zynqmp_dma_remove,
|
||||
};
|
||||
|
||||
module_platform_driver(zynqmp_dma_driver);
|
||||
|
||||
@@ -594,9 +594,9 @@ struct dma_descriptor_metadata_ops {
|
||||
* @phys: physical address of the descriptor
|
||||
* @chan: target channel for this operation
|
||||
* @tx_submit: accept the descriptor, assign ordered cookie and mark the
|
||||
* descriptor pending. To be pushed on .issue_pending() call
|
||||
* @desc_free: driver's callback function to free a resusable descriptor
|
||||
* after completion
|
||||
* descriptor pending. To be pushed on .issue_pending() call
|
||||
* @callback: routine to call after this operation is complete
|
||||
* @callback_result: error result from a DMA transaction
|
||||
* @callback_param: general parameter to pass to the callback routine
|
||||
|
||||
@@ -96,7 +96,7 @@ struct shdma_ops {
|
||||
int (*desc_setup)(struct shdma_chan *, struct shdma_desc *,
|
||||
dma_addr_t, dma_addr_t, size_t *);
|
||||
int (*set_slave)(struct shdma_chan *, int, dma_addr_t, bool);
|
||||
void (*setup_xfer)(struct shdma_chan *, int);
|
||||
int (*setup_xfer)(struct shdma_chan *, int);
|
||||
void (*start_xfer)(struct shdma_chan *, struct shdma_desc *);
|
||||
struct shdma_desc *(*embedded_desc)(void *, int);
|
||||
bool (*chan_irq)(struct shdma_chan *, int);
|
||||
|
||||
Reference in New Issue
Block a user