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ARM: dts: meson: Add the Ethernet "timing-adjustment" clock

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Add the "timing-adjusment" clock now that we now that this is connected
to the PRG_ETHERNET registers. It is used internally to generate the
RGMII RX delay no the MAC side (if needed).

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/20200512215148.540322-2-martin.blumenstingl@googlemail.com
This commit is contained in:
Martin Blumenstingl
2020-05-19 16:18:58 -07:00
committed by Kevin Hilman
parent f5a7382d6f
commit b632506c5a
2 changed files with 6 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/boot/dts/meson8b.dtsi
+3 -2
View File
@@ -425,8 +425,9 @@
clocks = <&clkc CLKID_ETH>,
<&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL2>;
clock-names = "stmmaceth", "clkin0", "clkin1";
<&clkc CLKID_MPLL2>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
rx-fifo-depth = <4096>;
tx-fifo-depth = <2048>;
arch/arm/boot/dts/meson8m2.dtsi
+3 -2
View File
@@ -30,8 +30,9 @@
0xc1108140 0x8>;
clocks = <&clkc CLKID_ETH>,
<&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL2>;
clock-names = "stmmaceth", "clkin0", "clkin1";
<&clkc CLKID_MPLL2>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
resets = <&reset RESET_ETHERNET>;
reset-names = "stmmaceth";
};