dlan17/linux
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

arm64: dts: mediatek: mt8188: Describe SCP as a cluster with two cores

Browse Source 
The SCP is currently described in the Devicetree as a single-core
processor, but really it is a cluster with two cores. Describe the full
cluster but enable only core0 on the current mt8188 platforms since
that's the only one usable with the upstream firmware.

Co-developed-by: Tinghan Shen <tinghan.shen@mediatek.com>
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Co-developed-by: Jason Chen <jason-ch.chen@mediatek.corp-partner.google.com>
Signed-off-by: Jason Chen <jason-ch.chen@mediatek.corp-partner.google.com>
Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Link: https://lore.kernel.org/r/20250421-scp-dual-core-mt8390-v2-4-c84117a959a9@collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
This commit is contained in:
Nícolas F. R. A. Prado
2025-04-22 15:47:16 +02:00
committed by AngeloGioacchino Del Regno
parent f5d2cbe5d8
commit b1e157c61d
3 changed files with 37 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm64/boot/dts/mediatek/mt8188-evb.dts
+5 -1
View File
@@ -331,7 +331,11 @@
interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
};
&scp {
&scp_cluster {
status = "okay";
};
&scp_c0 {
memory-region = <&scp_mem_reserved>;
status = "okay";
};
arch/arm64/boot/dts/mediatek/mt8188.dtsi
+27 -9
View File
@@ -1382,12 +1382,30 @@
clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>;
};
scp: scp@10500000 {
compatible = "mediatek,mt8188-scp";
reg = <0 0x10500000 0 0x100000>,
<0 0x10720000 0 0xe0000>;
reg-names = "sram", "cfg";
interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>;
scp_cluster: scp@10720000 {
compatible = "mediatek,mt8188-scp-dual";
reg = <0 0x10720000 0 0xe0000>;
reg-names = "cfg";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x10500000 0x100000>;
status = "disabled";
scp_c0: scp@0 {
compatible = "mediatek,scp-core";
reg = <0x0 0xd0000>;
reg-names = "sram";
interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>;
status = "disabled";
};
scp_c1: scp@d0000 {
compatible = "mediatek,scp-core";
reg = <0xd0000 0x2f000>;
reg-names = "sram";
interrupts = <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH 0>;
status = "disabled";
};
};
afe: audio-controller@10b10000 {
@@ -2249,7 +2267,7 @@
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>;
mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RDMA_SOF>,
<CMDQ_EVENT_VPP0_MDP_RDMA_FRAME_DONE>;
mediatek,scp = <&scp>;
mediatek,scp = <&scp_c0>;
};
display@14002000 {
@@ -2704,7 +2722,7 @@
iommus = <&vpp_iommu M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT>;
#address-cells = <2>;
#size-cells = <2>;
mediatek,scp = <&scp>;
mediatek,scp = <&scp_c0>;
video-codec@10000 {
compatible = "mediatek,mtk-vcodec-lat";
@@ -2828,7 +2846,7 @@
<&vdo_iommu M4U_PORT_L19_VENC_SUB_W_LUMA>,
<&vdo_iommu M4U_PORT_L19_VENC_SUB_R_LUMA>;
power-domains = <&spm MT8188_POWER_DOMAIN_VENC>;
mediatek,scp = <&scp>;
mediatek,scp = <&scp_c0>;
};
jpeg_encoder: jpeg-encoder@1a030000 {
arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi
+5 -1
View File
@@ -1055,7 +1055,11 @@
};
};
&scp {
&scp_cluster {
status = "okay";
};
&scp_c0 {
memory-region = <&scp_mem>;
status = "okay";
};