Merge tag 'arm-soc/for-6.14/devicetree-arm64' of https://github.com/Broadcom/stblinux into soc/dt
This pull request contains Broadcom ARM64-based SoCs Device Tree updates for 6.14: - Dave adds the display pipeline DT nodes on BCM2712 (Raspberry Pi 5) - Rob removes some undocumented properties - Same ensures that the CFE stub area is reserved to allow secondary CPUs to be successfully brought up in Linux, also making sure that the address used in the spin table is also carved out. Finally he adds support for the Zyxel EX3510-B router using BCM4906 - Rosen converts the BCM4908 platforms to use the more flexible nvmem-layout representation * tag 'arm-soc/for-6.14/devicetree-arm64' of https://github.com/Broadcom/stblinux: arm64: dts: bcm4908: nvmem-layout conversion arm64: dts: broadcom: bcmbca: bcm4908: Add DT for Zyxel EX3510-B dt-bindings: arm64: bcmbca: Add Zyxel EX3510-B based on BCM4906 arm64: dts: broadcom: bcmbca: bcm4908: Protect cpu-release-addr arm64: dts: broadcom: bcmbca: bcm4908: Reserve CFE stub area arm64: dts: broadcom: Remove unused and undocumented properties arm64: dts: broadcom: Add DT for D-step version of BCM2712 arm64: dts: broadcom: Add display pipeline support to BCM2712 arm64: dts: broadcom: Add firmware clocks and power nodes to Pi5 DT Link: https://lore.kernel.org/r/20250109224756.3632025-2-florian.fainelli@broadcom.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
@@ -34,6 +34,7 @@ properties:
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- enum:
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- netgear,r8000p
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- tplink,archer-c2300-v1
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- zyxel,ex3510b
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- const: brcm,bcm4906
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- const: brcm,bcm4908
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- const: brcm,bcmbca
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@@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-400.dtb \
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bcm2711-rpi-4-b.dtb \
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bcm2711-rpi-cm4-io.dtb \
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bcm2712-rpi-5-b.dtb \
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bcm2712-d-rpi-5-b.dtb \
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bcm2837-rpi-3-a-plus.dtb \
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bcm2837-rpi-3-b.dtb \
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bcm2837-rpi-3-b-plus.dtb \
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@@ -0,0 +1,37 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/dts-v1/;
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#include "bcm2712-rpi-5-b.dts"
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&gio_aon {
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brcm,gpio-bank-widths = <15 6>;
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gpio-line-names =
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"RP1_SDA", // AON_GPIO_00
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"RP1_SCL", // AON_GPIO_01
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"RP1_RUN", // AON_GPIO_02
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"SD_IOVDD_SEL", // AON_GPIO_03
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"SD_PWR_ON", // AON_GPIO_04
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"SD_CDET_N", // AON_GPIO_05
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"SD_FLG_N", // AON_GPIO_06
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"", // AON_GPIO_07
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"2712_WAKE", // AON_GPIO_08
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"2712_STAT_LED", // AON_GPIO_09
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"", // AON_GPIO_10
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"", // AON_GPIO_11
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"PMIC_INT", // AON_GPIO_12
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"UART_TX_FS", // AON_GPIO_13
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"UART_RX_FS", // AON_GPIO_14
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"", // AON_GPIO_15
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"", // AON_GPIO_16
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// Pad bank0 out to 32 entries
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"", "", "", "", "", "", "", "", "", "", "", "", "", "", "",
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"HDMI0_SCL", // AON_SGPIO_00
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"HDMI0_SDA", // AON_SGPIO_01
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"HDMI1_SCL", // AON_SGPIO_02
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"HDMI1_SDA", // AON_SGPIO_03
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"PMIC_SCL", // AON_SGPIO_04
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"PMIC_SDA"; // AON_SGPIO_05
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};
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@@ -62,3 +62,45 @@
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sd-uhs-ddr50;
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sd-uhs-sdr104;
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};
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&soc {
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firmware: firmware {
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compatible = "raspberrypi,bcm2835-firmware", "simple-mfd";
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#address-cells = <1>;
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#size-cells = <1>;
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mboxes = <&mailbox>;
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dma-ranges;
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firmware_clocks: clocks {
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compatible = "raspberrypi,firmware-clocks";
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#clock-cells = <1>;
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};
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reset: reset {
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compatible = "raspberrypi,firmware-reset";
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#reset-cells = <1>;
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};
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};
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power: power {
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compatible = "raspberrypi,bcm2835-power";
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firmware = <&firmware>;
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#power-domain-cells = <1>;
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};
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};
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&hvs {
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clocks = <&firmware_clocks 4>, <&firmware_clocks 16>;
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clock-names = "core", "disp";
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};
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&hdmi0 {
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clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 0>, <&clk_27MHz>;
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clock-names = "hdmi", "bvb", "audio", "cec";
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};
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&hdmi1 {
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clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>;
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clock-names = "hdmi", "bvb", "audio", "cec";
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};
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@@ -221,11 +221,6 @@
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#mbox-cells = <0>;
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};
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local_intc: interrupt-controller@7cd00000 {
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compatible = "brcm,bcm2836-l1-intc";
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reg = <0x7cd00000 0x100>;
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};
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uart10: serial@7d001000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x7d001000 0x200>;
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@@ -265,6 +260,172 @@
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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aon_intr: interrupt-controller@7d510600 {
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compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc";
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reg = <0x7d510600 0x30>;
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interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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pixelvalve0: pixelvalve@7c410000 {
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compatible = "brcm,bcm2712-pixelvalve0";
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reg = <0x7c410000 0x100>;
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interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
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};
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pixelvalve1: pixelvalve@7c411000 {
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compatible = "brcm,bcm2712-pixelvalve1";
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reg = <0x7c411000 0x100>;
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interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
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};
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mop: mop@7c500000 {
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compatible = "brcm,bcm2712-mop";
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reg = <0x7c500000 0x28>;
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interrupt-parent = <&disp_intr>;
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interrupts = <1>;
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};
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moplet: moplet@7c501000 {
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compatible = "brcm,bcm2712-moplet";
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reg = <0x7c501000 0x20>;
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interrupt-parent = <&disp_intr>;
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interrupts = <0>;
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};
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disp_intr: interrupt-controller@7c502000 {
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compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc";
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reg = <0x7c502000 0x30>;
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interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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dvp: clock@7c700000 {
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compatible = "brcm,brcm2711-dvp";
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reg = <0x7c700000 0x10>;
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clocks = <&clk_108MHz>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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ddc0: i2c@7d508200 {
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compatible = "brcm,brcmstb-i2c";
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reg = <0x7d508200 0x58>;
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interrupt-parent = <&bsc_irq>;
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interrupts = <1>;
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clock-frequency = <97500>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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ddc1: i2c@7d508280 {
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compatible = "brcm,brcmstb-i2c";
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reg = <0x7d508280 0x58>;
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interrupt-parent = <&bsc_irq>;
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interrupts = <2>;
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clock-frequency = <97500>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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bsc_irq: interrupt-controller@7d508380 {
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compatible = "brcm,bcm7271-l2-intc";
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reg = <0x7d508380 0x10>;
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interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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main_irq: interrupt-controller@7d508400 {
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compatible = "brcm,bcm7271-l2-intc";
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reg = <0x7d508400 0x10>;
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interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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hdmi0: hdmi@7c701400 {
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compatible = "brcm,bcm2712-hdmi0";
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reg = <0x7c701400 0x300>,
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<0x7c701000 0x200>,
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<0x7c701d00 0x300>,
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<0x7c702000 0x80>,
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<0x7c703800 0x200>,
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<0x7c704000 0x800>,
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<0x7c700100 0x80>,
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<0x7d510800 0x100>,
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<0x7c720000 0x100>;
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reg-names = "hdmi",
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"dvp",
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"phy",
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"rm",
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"packet",
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"metadata",
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"csc",
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"cec",
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"hd";
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resets = <&dvp 1>;
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interrupt-parent = <&aon_intr>;
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interrupts = <1>, <2>, <3>,
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<7>, <8>;
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interrupt-names = "cec-tx", "cec-rx", "cec-low",
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"hpd-connected", "hpd-removed";
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ddc = <&ddc0>;
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};
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hdmi1: hdmi@7c706400 {
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compatible = "brcm,bcm2712-hdmi1";
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reg = <0x7c706400 0x300>,
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<0x7c706000 0x200>,
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<0x7c706d00 0x300>,
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<0x7c707000 0x80>,
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<0x7c708800 0x200>,
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<0x7c709000 0x800>,
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<0x7c700180 0x80>,
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<0x7d511000 0x100>,
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<0x7c720000 0x100>;
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reg-names = "hdmi",
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"dvp",
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"phy",
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"rm",
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"packet",
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"metadata",
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"csc",
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"cec",
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"hd";
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resets = <&dvp 2>;
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interrupt-parent = <&aon_intr>;
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interrupts = <11>, <12>, <13>,
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<14>, <15>;
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interrupt-names = "cec-tx", "cec-rx", "cec-low",
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"hpd-connected", "hpd-removed";
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ddc = <&ddc1>;
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};
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};
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axi: axi {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x00 0x00000000 0x00 0x00000000 0x10 0x00000000>,
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<0x10 0x00000000 0x10 0x00000000 0x01 0x00000000>,
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<0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>,
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<0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>,
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<0x1c 0x00000000 0x1c 0x00000000 0x04 0x00000000>;
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dma-ranges = <0x00 0x00000000 0x00 0x00000000 0x10 0x00000000>,
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<0x10 0x00000000 0x10 0x00000000 0x01 0x00000000>,
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<0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>,
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<0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>,
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<0x1c 0x00000000 0x1c 0x00000000 0x04 0x00000000>;
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vc4: gpu {
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compatible = "brcm,bcm2712-vc6";
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};
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};
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timer {
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@@ -280,4 +441,26 @@
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<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(4) |
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IRQ_TYPE_LEVEL_LOW)>;
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};
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clk_27MHz: clk-27M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <27000000>;
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clock-output-names = "27MHz-clock";
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};
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clk_108MHz: clk-108M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <108000000>;
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clock-output-names = "108MHz-clock";
|
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};
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hvs: hvs@107c580000 {
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compatible = "brcm,bcm2712-hvs";
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reg = <0x10 0x7c580000 0x0 0x1a000>;
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interrupt-parent = <&disp_intr>;
|
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interrupts = <2>, <9>, <16>;
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interrupt-names = "ch0-eof", "ch1-eof", "ch2-eof";
|
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};
|
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};
|
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|
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@@ -2,6 +2,7 @@
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dtb-$(CONFIG_ARCH_BCMBCA) += \
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bcm4906-netgear-r8000p.dtb \
|
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bcm4906-tplink-archer-c2300-v1.dtb \
|
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bcm4906-zyxel-ex3510b.dtb \
|
||||
bcm4908-asus-gt-ac5300.dtb \
|
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bcm4908-netgear-raxe500.dtb \
|
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bcm94908.dtb \
|
||||
|
||||
@@ -144,16 +144,20 @@
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
compatible = "nvmem-cells";
|
||||
label = "cferom";
|
||||
reg = <0x0 0x100000>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
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ranges = <0 0x0 0x100000>;
|
||||
|
||||
base_mac_addr: mac@106a0 {
|
||||
reg = <0x106a0 0x6>;
|
||||
nvmem-layout {
|
||||
compatible = "fixed-layout";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
base_mac_addr: mac@106a0 {
|
||||
reg = <0x106a0 0x6>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@@ -0,0 +1,196 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
|
||||
#include "bcm4906.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "zyxel,ex3510b", "brcm,bcm4906", "brcm,bcm4908", "brcm,bcmbca";
|
||||
model = "Zyxel EX3510-B";
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x20000000>;
|
||||
};
|
||||
|
||||
gpio-keys-polled {
|
||||
compatible = "gpio-keys-polled";
|
||||
poll-interval = <100>;
|
||||
|
||||
key-wps {
|
||||
label = "WPS";
|
||||
linux,code = <KEY_WPS_BUTTON>;
|
||||
gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
key-reset {
|
||||
label = "Reset";
|
||||
linux,code = <KEY_RESTART>;
|
||||
gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&leds {
|
||||
pinctrl-0 = <&pins_led_0_a>, <&pins_led_2_a>, <&pins_led_3_a>,
|
||||
<&pins_led_4_a>, <&pins_led_10_a>, <&pins_led_12_a>,
|
||||
<&pins_led_14_a>, <&pins_led_15_a>, <&pins_led_21_a>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
led@0 {
|
||||
reg = <0x0>;
|
||||
function = LED_FUNCTION_POWER;
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
};
|
||||
|
||||
led@2 {
|
||||
reg = <0x2>;
|
||||
function = LED_FUNCTION_WAN_ONLINE;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
};
|
||||
|
||||
led@3 {
|
||||
reg = <0x3>;
|
||||
function = LED_FUNCTION_WAN_ONLINE;
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
};
|
||||
|
||||
led@4 {
|
||||
reg = <0x4>;
|
||||
function = LED_FUNCTION_USB;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
trigger-sources = <&ohci_port1>, <&ohci_port2>,
|
||||
<&ehci_port1>, <&ehci_port2>,
|
||||
<&xhci_port1>, <&xhci_port2>;
|
||||
linux,default-trigger = "usbport";
|
||||
};
|
||||
|
||||
led@a {
|
||||
reg = <0xa>;
|
||||
function = LED_FUNCTION_POWER;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
linux,default-trigger = "default-on";
|
||||
};
|
||||
|
||||
led@c {
|
||||
reg = <0xc>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
active-low;
|
||||
};
|
||||
|
||||
led@e {
|
||||
reg = <0xe>;
|
||||
function = LED_FUNCTION_WPS;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
active-low;
|
||||
};
|
||||
|
||||
led@f {
|
||||
reg = <0xf>;
|
||||
function = LED_FUNCTION_WPS;
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
active-low;
|
||||
};
|
||||
|
||||
led@15 {
|
||||
reg = <0x15>;
|
||||
function = LED_FUNCTION_WAN;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
active-low;
|
||||
};
|
||||
};
|
||||
|
||||
&enet {
|
||||
nvmem-cells = <&base_mac_addr>;
|
||||
nvmem-cell-names = "mac-address";
|
||||
};
|
||||
|
||||
&usb_phy {
|
||||
brcm,ioc = <1>;
|
||||
brcm,ipp = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&xhci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ports {
|
||||
port@0 {
|
||||
label = "lan1";
|
||||
};
|
||||
|
||||
port@1 {
|
||||
label = "lan2";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
label = "lan3";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
label = "lan4";
|
||||
};
|
||||
|
||||
port@7 {
|
||||
reg = <7>;
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy12>;
|
||||
label = "wan";
|
||||
};
|
||||
};
|
||||
|
||||
&nand_controller {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&nandcs {
|
||||
brcm,nand-oob-sector-size = <27>;
|
||||
nand-ecc-strength = <8>;
|
||||
nand-ecc-step-size = <512>;
|
||||
nand-on-flash-bbt;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
partitions {
|
||||
compatible = "brcm,bcm4908-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
compatible = "nvmem-cells";
|
||||
label = "cferom";
|
||||
reg = <0x0 0x100000>;
|
||||
read-only;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
base_mac_addr: mac@106a0 {
|
||||
reg = <0x106a0 0x6>;
|
||||
};
|
||||
};
|
||||
|
||||
partition@100000 {
|
||||
compatible = "brcm,bcm4908-firmware";
|
||||
reg = <0x100000 0x5f80000>;
|
||||
};
|
||||
|
||||
partition@6080000 {
|
||||
compatible = "brcm,bcm4908-firmware";
|
||||
reg = <0x6080000 0x5f80000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -30,7 +30,7 @@
|
||||
compatible = "brcm,brahma-b53";
|
||||
reg = <0x0>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0x0 0xfff8>;
|
||||
cpu-release-addr = <0x0 0xff8>;
|
||||
next-level-cache = <&l2>;
|
||||
};
|
||||
|
||||
@@ -39,7 +39,7 @@
|
||||
compatible = "brcm,brahma-b53";
|
||||
reg = <0x1>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0x0 0xfff8>;
|
||||
cpu-release-addr = <0x0 0xff8>;
|
||||
next-level-cache = <&l2>;
|
||||
};
|
||||
|
||||
@@ -48,7 +48,7 @@
|
||||
compatible = "brcm,brahma-b53";
|
||||
reg = <0x2>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0x0 0xfff8>;
|
||||
cpu-release-addr = <0x0 0xff8>;
|
||||
next-level-cache = <&l2>;
|
||||
};
|
||||
|
||||
@@ -57,7 +57,7 @@
|
||||
compatible = "brcm,brahma-b53";
|
||||
reg = <0x3>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0x0 0xfff8>;
|
||||
cpu-release-addr = <0x0 0xff8>;
|
||||
next-level-cache = <&l2>;
|
||||
};
|
||||
|
||||
@@ -68,6 +68,16 @@
|
||||
};
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
cfe-stub@0 {
|
||||
reg = <0x0 0x0 0x0 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
axi@81000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
|
||||
@@ -137,7 +137,6 @@
|
||||
spi-cpha;
|
||||
spi-cpol;
|
||||
pl022,interface = <0>;
|
||||
pl022,slave-tx-disable = <0>;
|
||||
pl022,com-mode = <0>;
|
||||
pl022,rx-level-trig = <1>;
|
||||
pl022,tx-level-trig = <1>;
|
||||
@@ -200,7 +199,6 @@
|
||||
};
|
||||
|
||||
&qspi {
|
||||
bspi-sel = <0>;
|
||||
flash: flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
@@ -151,7 +151,6 @@
|
||||
#size-cells = <1>;
|
||||
compatible = "m25p80";
|
||||
spi-max-frequency = <62500000>;
|
||||
m25p,default-addr-width = <3>;
|
||||
reg = <0x0 0x0>;
|
||||
|
||||
partition@0 {
|
||||
|
||||
@@ -134,7 +134,6 @@
|
||||
brcm,pcie-ob;
|
||||
brcm,pcie-ob-oarr-size;
|
||||
brcm,pcie-ob-axi-offset = <0x00000000>;
|
||||
brcm,pcie-ob-window-size = <256>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
@@ -165,7 +164,6 @@
|
||||
brcm,pcie-ob;
|
||||
brcm,pcie-ob-oarr-size;
|
||||
brcm,pcie-ob-axi-offset = <0x30000000>;
|
||||
brcm,pcie-ob-window-size = <256>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
|
||||
Reference in New Issue
Block a user