arm64: dts: qcom: x1e80100: Add videocc
Add the video clock controller for X1E80100, similar to sm8550.dtsi. It provides the needed clocks/power domains for the iris video codec. Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250709-x1e-videocc-v2-6-ad1acf5674b4@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Bjorn Andersson
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@@ -5,6 +5,7 @@
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
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#include <dt-bindings/clock/qcom,sm8450-videocc.h>
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#include <dt-bindings/clock/qcom,x1e80100-dispcc.h>
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#include <dt-bindings/clock/qcom,x1e80100-gcc.h>
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#include <dt-bindings/clock/qcom,x1e80100-gpucc.h>
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@@ -5182,6 +5183,20 @@
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};
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};
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videocc: clock-controller@aaf0000 {
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compatible = "qcom,x1e80100-videocc";
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reg = <0 0x0aaf0000 0 0x10000>;
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clocks = <&bi_tcxo_div2>,
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<&gcc GCC_VIDEO_AHB_CLK>;
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power-domains = <&rpmhpd RPMHPD_MMCX>,
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<&rpmhpd RPMHPD_MXC>;
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required-opps = <&rpmhpd_opp_low_svs>,
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<&rpmhpd_opp_low_svs>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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mdss: display-subsystem@ae00000 {
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compatible = "qcom,x1e80100-mdss";
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reg = <0 0x0ae00000 0 0x1000>;
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