dts: Add nanhu-v5-1core-uartlite

Signed-off-by: Ran Wang <wangran@bosc.ac.cn>

arch/riscv/boot/dts/bosc/Makefile

@@ -21,6 +21,7 @@ dtb-$(CONFIG_SOC_XIANGSHAN) += \
 	kmh-v2-4core-uartlite.dtb \
 	kmh-v2-8core-uartlite.dtb \
 	kmh-v2-16core-uartlite.dtb \
-	nanhu-v5-1core.dtb
+	nanhu-v5-1core.dtb \
+	nanhu-v5-1core-uartlite.dtb
 
 obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))

arch/riscv/boot/dts/bosc/nanhu-v5-1core-uartlite.dts

@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2025 BOSC */
+
+/dts-v1/;
+#include "nanhu-v5.dtsi"
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	compatible = "bosc,nanhu-v5-dev";
+	model = "bosc,nanhu-v5-1core-uartlite";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		bootargs = "console=hvc0 earlycon=sbi loglevel=8";
+		opensbi-config {
+		    compatible = "opensbi,config";
+		    cold-boot-harts = <&cpu0>;
+		};
+	};
+};
+
+&cpu0 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};

arch/riscv/boot/dts/bosc/nanhu-v5.dtsi

@@ -44,6 +44,7 @@
 			reg = <0x0 0x38000000 0x0 0x10000>;
 			interrupts-extended = <&intc_cpu0 3>, <&intc_cpu0 7>;
 		};
+
 		uart0: serial@310b0000 {
 			compatible = "ns16550a";
 			reg = <0x0 0x310b0000 0x0 0x10000>;
@@ -54,6 +55,14 @@
 			status = "disable"
 		};
 
+		uart1: serial@40600000 {
+			compatible = "xlnx,xps-uartlite-1.00.a";
+			current-speed = <115200>;
+			reg = <0x0 0x40600000 0x0 0x1000>;
+			reg-names = "control";
+			status = "disable"
+		};
+
 	};
 
 	memory: memory@80000000 {