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drm/amdgpu: Add VCN v4.0.3 RRMT register offset

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Add RRMT control register offset for VCN v4.0.3

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Lijo Lazar
2025-02-12 21:02:55 -05:00
committed by Alex Deucher
parent e55565f880
commit 822b13d19f
1 changed files with 2 additions and 1 deletions
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drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_offset.h
+2 -1
View File
@@ -779,7 +779,8 @@
#define regUVD_LMI_MIF_REF_LUMA_64BIT_BAR_HIGH_BASE_IDX 1
#define regVCN_RAS_CNTL 0x02df
#define regVCN_RAS_CNTL_BASE_IDX 1
#define regVCN_RRMT_CNTL 0x0940
#define regVCN_RRMT_CNTL_BASE_IDX 1
// addressBlock: aid_uvd0_uvd_jpeg0_jpegnpdec
// base address: 0x20f00