Merge tag 'kvmarm-fixes-6.16-5' of https://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD
KVM/arm64 fixes for 6.16, take # - Remove the last leftovers from the ill-fated FPSIMD host state mapping at EL2 stage-1 - Fix unexpected advertisement to the guest of unimplemented S2 base granule sizes
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@@ -1480,7 +1480,6 @@ int kvm_vm_ioctl_get_reg_writable_masks(struct kvm *kvm,
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struct reg_mask_range *range);
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/* Guest/host FPSIMD coordination helpers */
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int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu);
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void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu);
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void kvm_arch_vcpu_ctxflush_fp(struct kvm_vcpu *vcpu);
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void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu);
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@@ -825,10 +825,6 @@ int kvm_arch_vcpu_run_pid_change(struct kvm_vcpu *vcpu)
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if (!kvm_arm_vcpu_is_finalized(vcpu))
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return -EPERM;
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ret = kvm_arch_vcpu_run_map_fp(vcpu);
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if (ret)
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return ret;
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if (likely(vcpu_has_run_once(vcpu)))
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return 0;
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@@ -14,32 +14,6 @@
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#include <asm/kvm_mmu.h>
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#include <asm/sysreg.h>
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/*
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* Called on entry to KVM_RUN unless this vcpu previously ran at least
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* once and the most recent prior KVM_RUN for this vcpu was called from
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* the same task as current (highly likely).
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*
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* This is guaranteed to execute before kvm_arch_vcpu_load_fp(vcpu),
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* such that on entering hyp the relevant parts of current are already
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* mapped.
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*/
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int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu)
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{
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struct user_fpsimd_state *fpsimd = ¤t->thread.uw.fpsimd_state;
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int ret;
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/* pKVM has its own tracking of the host fpsimd state. */
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if (is_protected_kvm_enabled())
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return 0;
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/* Make sure the host task fpsimd state is visible to hyp: */
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ret = kvm_share_hyp(fpsimd, fpsimd + 1);
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if (ret)
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return ret;
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return 0;
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}
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/*
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* Prepare vcpu for saving the host's FPSIMD state and loading the guest's.
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* The actual loading is done by the FPSIMD access trap taken to hyp.
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+23
-3
@@ -1402,6 +1402,21 @@ static void kvm_map_l1_vncr(struct kvm_vcpu *vcpu)
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}
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}
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#define has_tgran_2(__r, __sz) \
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({ \
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u64 _s1, _s2, _mmfr0 = __r; \
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\
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_s2 = SYS_FIELD_GET(ID_AA64MMFR0_EL1, \
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TGRAN##__sz##_2, _mmfr0); \
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\
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_s1 = SYS_FIELD_GET(ID_AA64MMFR0_EL1, \
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TGRAN##__sz, _mmfr0); \
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\
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((_s2 != ID_AA64MMFR0_EL1_TGRAN##__sz##_2_NI && \
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_s2 != ID_AA64MMFR0_EL1_TGRAN##__sz##_2_TGRAN##__sz) || \
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(_s2 == ID_AA64MMFR0_EL1_TGRAN##__sz##_2_TGRAN##__sz && \
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_s1 != ID_AA64MMFR0_EL1_TGRAN##__sz##_NI)); \
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})
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/*
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* Our emulated CPU doesn't support all the possible features. For the
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* sake of simplicity (and probably mental sanity), wipe out a number
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@@ -1411,6 +1426,8 @@ static void kvm_map_l1_vncr(struct kvm_vcpu *vcpu)
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*/
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u64 limit_nv_id_reg(struct kvm *kvm, u32 reg, u64 val)
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{
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u64 orig_val = val;
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switch (reg) {
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case SYS_ID_AA64ISAR0_EL1:
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/* Support everything but TME */
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@@ -1480,13 +1497,16 @@ u64 limit_nv_id_reg(struct kvm *kvm, u32 reg, u64 val)
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*/
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switch (PAGE_SIZE) {
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case SZ_4K:
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val |= SYS_FIELD_PREP_ENUM(ID_AA64MMFR0_EL1, TGRAN4_2, IMP);
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if (has_tgran_2(orig_val, 4))
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val |= SYS_FIELD_PREP_ENUM(ID_AA64MMFR0_EL1, TGRAN4_2, IMP);
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fallthrough;
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case SZ_16K:
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val |= SYS_FIELD_PREP_ENUM(ID_AA64MMFR0_EL1, TGRAN16_2, IMP);
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if (has_tgran_2(orig_val, 16))
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val |= SYS_FIELD_PREP_ENUM(ID_AA64MMFR0_EL1, TGRAN16_2, IMP);
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fallthrough;
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case SZ_64K:
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val |= SYS_FIELD_PREP_ENUM(ID_AA64MMFR0_EL1, TGRAN64_2, IMP);
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if (has_tgran_2(orig_val, 64))
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val |= SYS_FIELD_PREP_ENUM(ID_AA64MMFR0_EL1, TGRAN64_2, IMP);
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break;
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}
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