drm/etnaviv: add optional reset support
Add optional reset support which is mentioned in vivante,gc.yaml to allow the driver to work on SoCs whose reset signal is asserted by default Signed-off-by: Philippe Lecointre <philippe.lecointre@thalesgroup.com> Acked-by: Simon Lenain <simon.lenain@thalesgroup.com> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
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Lucas Stach
parent
6bef484c5e
commit
6bde14ba5f
@@ -13,6 +13,7 @@
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regulator/consumer.h>
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#include <linux/reset.h>
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#include <linux/thermal.h>
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#include "etnaviv_cmdbuf.h"
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@@ -172,6 +173,29 @@ int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value)
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return 0;
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}
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static int etnaviv_gpu_reset_deassert(struct etnaviv_gpu *gpu)
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{
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int ret;
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/*
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* 32 core clock cycles (slowest clock) required before deassertion
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* 1 microsecond might match all implementations without computation
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*/
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usleep_range(1, 2);
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ret = reset_control_deassert(gpu->rst);
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if (ret)
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return ret;
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/*
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* 128 core clock cycles (slowest clock) required before any activity on AHB
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* 1 microsecond might match all implementations without computation
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*/
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usleep_range(1, 2);
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return 0;
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}
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static inline bool etnaviv_is_model_rev(struct etnaviv_gpu *gpu, u32 model, u32 revision)
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{
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return gpu->identity.model == model &&
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@@ -799,6 +823,12 @@ int etnaviv_gpu_init(struct etnaviv_gpu *gpu)
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goto pm_put;
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}
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ret = etnaviv_gpu_reset_deassert(gpu);
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if (ret) {
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dev_err(gpu->dev, "GPU reset deassert failed\n");
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goto fail;
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}
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etnaviv_hw_identify(gpu);
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if (gpu->identity.model == 0) {
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@@ -1860,6 +1890,17 @@ static int etnaviv_gpu_platform_probe(struct platform_device *pdev)
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if (IS_ERR(gpu->mmio))
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return PTR_ERR(gpu->mmio);
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/* Get Reset: */
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gpu->rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
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if (IS_ERR(gpu->rst))
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return dev_err_probe(dev, PTR_ERR(gpu->rst),
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"failed to get reset\n");
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err = reset_control_assert(gpu->rst);
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if (err)
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return dev_err_probe(dev, err, "failed to assert reset\n");
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/* Get Interrupt: */
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gpu->irq = platform_get_irq(pdev, 0);
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if (gpu->irq < 0)
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@@ -93,6 +93,7 @@ struct etnaviv_event {
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struct etnaviv_cmdbuf_suballoc;
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struct regulator;
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struct clk;
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struct reset_control;
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#define ETNA_NR_EVENTS 30
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@@ -158,6 +159,7 @@ struct etnaviv_gpu {
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struct clk *clk_reg;
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struct clk *clk_core;
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struct clk *clk_shader;
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struct reset_control *rst;
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unsigned int freq_scale;
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unsigned int fe_waitcycles;
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