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dt-bindings: PCI: altera: Add binding for Agilex

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Add the compatible bindings for the three variants of the Agilex
PCIe Hard IP.

Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20250221170452.875419-2-matthew.gerlach@linux.intel.com
[kwilczynski: update description within devicetree bindings]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
This commit is contained in:
Matthew Gerlach
2025-03-05 22:22:08 +00:00
committed by Krzysztof Wilczyński
parent 2014c95afe
commit 6843f38e16
1 changed files with 10 additions and 0 deletions
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Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml
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@@ -12,9 +12,19 @@ maintainers:
properties:
compatible:
description: Each family of socfpga has its own implementation of the
PCI controller. The altr,pcie-root-port-1.0 is used for the Cyclone5
family of chips. The Stratix10 family of chips is supported by the
altr,pcie-root-port-2.0. The Agilex family of chips has three,
non-register compatible, variants of PCIe Hard IP referred to as the
F-Tile, P-Tile, and R-Tile, depending on the specific chip instance.
enum:
- altr,pcie-root-port-1.0
- altr,pcie-root-port-2.0
- altr,pcie-root-port-3.0-f-tile
- altr,pcie-root-port-3.0-p-tile
- altr,pcie-root-port-3.0-r-tile
reg:
items: