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Merge branch 'randconfig-fixes' into next/fixes-non-critical

Browse Source 
This is the first batch of a much longer series of bug fixes
found during randconfig testing. This part are all the simple
patches that are applicable for the arm-soc tree, while most
other fixes will likely go through other maintainers.

* randconfig-fixes: (50 commits)
  ARM: tegra: make debug_ll code build for ARMv6
  ARM: sunxi: fix build for THUMB2_KERNEL
  ARM: exynos: add missing include of linux/module.h
  ARM: exynos: fix l2x0 saved regs handling
  ARM: samsung: select CRC32 for SAMSUNG_PM_CHECK
  ARM: samsung: select ATAGS where necessary
  ARM: samsung: fix SAMSUNG_PM_DEBUG Kconfig logic
  ARM: samsung: allow serial driver to be disabled
  ARM: s5pv210: enable IDE support in MACH_TORBRECK
  ARM: s5p64x0: fix building with only one soc type
  ARM: s3c64xx: select power domains only when used
  ARM: s3c64xx: MACH_SMDK6400 needs HSMMC1
  ARM: s3c24xx: osiris dvs needs tps65010
  ARM: s3c24xx: fix gta02 build error
  ARM: s3c24xx: MINI2440 needs I2C for EEPROM_AT24
  ARM: integrator: only select pl01x if TTY is enabled
  ARM: realview: fix sparsemem build
  ARM: footbridge: make screen_info setup conditional
  ARM: footbridge: fix build with PCI disabled
  ARM: footbridge: don't build floppy code for addin mode
  ...

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2014-03-22 01:10:19 +01:00
parent b44ce3b0f9 9f3ba4567e
commit 600a1dfae2
53 changed files with 161 additions and 93 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/Kconfig
+8 -1
View File
@@ -420,6 +420,7 @@ config ARCH_EFM32
bool "Energy Micro efm32"
depends on !MMU
select ARCH_REQUIRE_GPIOLIB
select AUTO_ZRELADDR
select ARM_NVIC
# CLKSRC_MMIO is wrong here, but needed until a proper fix is merged,
# i.e. CLKSRC_EFM32 selecting CLKSRC_MMIO
@@ -697,6 +698,7 @@ config ARCH_RPC
select ARCH_MAY_HAVE_PC_FDC
select ARCH_SPARSEMEM_ENABLE
select ARCH_USES_GETTIMEOFFSET
select CPU_SA110
select FIQ
select HAVE_IDE
select HAVE_PATA_PLATFORM
@@ -731,6 +733,7 @@ config ARCH_S3C24XX
bool "Samsung S3C24XX SoCs"
select ARCH_HAS_CPUFREQ
select ARCH_REQUIRE_GPIOLIB
select ATAGS
select CLKDEV_LOOKUP
select CLKSRC_SAMSUNG_PWM
select GENERIC_CLOCKEVENTS
@@ -753,6 +756,7 @@ config ARCH_S3C64XX
select ARCH_REQUIRE_GPIOLIB
select ARM_AMBA
select ARM_VIC
select ATAGS
select CLKDEV_LOOKUP
select CLKSRC_SAMSUNG_PWM
select COMMON_CLK
@@ -764,7 +768,7 @@ config ARCH_S3C64XX
select HAVE_TCM
select NO_IOPORT
select PLAT_SAMSUNG
select PM_GENERIC_DOMAINS
select PM_GENERIC_DOMAINS if PM
select S3C_DEV_NAND
select S3C_GPIO_TRACK
select SAMSUNG_ATAGS
@@ -776,6 +780,7 @@ config ARCH_S3C64XX
config ARCH_S5P64X0
bool "Samsung S5P6440 S5P6450"
select ATAGS
select CLKDEV_LOOKUP
select CLKSRC_SAMSUNG_PWM
select CPU_V6
@@ -794,6 +799,7 @@ config ARCH_S5P64X0
config ARCH_S5PC100
bool "Samsung S5PC100"
select ARCH_REQUIRE_GPIOLIB
select ATAGS
select CLKDEV_LOOKUP
select CLKSRC_SAMSUNG_PWM
select CPU_V7
@@ -813,6 +819,7 @@ config ARCH_S5PV210
select ARCH_HAS_CPUFREQ
select ARCH_HAS_HOLES_MEMORYMODEL
select ARCH_SPARSEMEM_ENABLE
select ATAGS
select CLKDEV_LOOKUP
select CLKSRC_SAMSUNG_PWM
select CPU_V7
arch/arm/configs/davinci_all_defconfig
+2
View File
@@ -198,3 +198,5 @@ CONFIG_DEBUG_ERRORS=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set
# CONFIG_CRYPTO_HW is not set
CONFIG_CRC_T10DIF=m
CONFIG_GPIO_PCA953X=y
CONFIG_KEYBOARD_GPIO_POLLED=y
arch/arm/include/asm/smp.h
+1
View File
@@ -74,6 +74,7 @@ struct secondary_data {
};
extern struct secondary_data secondary_data;
extern volatile int pen_release;
extern void secondary_startup(void);
extern int __cpu_disable(void);
arch/arm/include/debug/tegra.S
+8 -10
View File
@@ -53,8 +53,7 @@
#define checkuart(rp, rv, lhu, bit, uart) \
/* Load address of CLK_RST register */ \
movw rp, #TEGRA_CLK_RST_DEVICES_##lhu & 0xffff ; \
movt rp, #TEGRA_CLK_RST_DEVICES_##lhu >> 16 ; \
ldr rp, =TEGRA_CLK_RST_DEVICES_##lhu ; \
/* Load value from CLK_RST register */ \
ldr rp, [rp, #0] ; \
/* Test UART's reset bit */ \
@@ -62,8 +61,7 @@
/* If set, can't use UART; jump to save no UART */ \
bne 90f ; \
/* Load address of CLK_OUT_ENB register */ \
movw rp, #TEGRA_CLK_OUT_ENB_##lhu & 0xffff ; \
movt rp, #TEGRA_CLK_OUT_ENB_##lhu >> 16 ; \
ldr rp, =TEGRA_CLK_OUT_ENB_##lhu ; \
/* Load value from CLK_OUT_ENB register */ \
ldr rp, [rp, #0] ; \
/* Test UART's clock enable bit */ \
@@ -71,8 +69,7 @@
/* If clear, can't use UART; jump to save no UART */ \
beq 90f ; \
/* Passed all tests, load address of UART registers */ \
movw rp, #TEGRA_UART##uart##_BASE & 0xffff ; \
movt rp, #TEGRA_UART##uart##_BASE >> 16 ; \
ldr rp, =TEGRA_UART##uart##_BASE ; \
/* Jump to save UART address */ \
b 91f
@@ -90,15 +87,16 @@
#ifdef CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA
/* Check ODMDATA */
10: movw \rp, #TEGRA_PMC_SCRATCH20 & 0xffff
movt \rp, #TEGRA_PMC_SCRATCH20 >> 16
10: ldr \rp, =TEGRA_PMC_SCRATCH20
ldr \rp, [\rp, #0] @ Load PMC_SCRATCH20
ubfx \rv, \rp, #18, #2 @ 19:18 are console type
lsr \rv, \rp, #18 @ 19:18 are console type
and \rv, \rv, #3
cmp \rv, #2 @ 2 and 3 mean DCC, UART
beq 11f @ some boards swap the meaning
cmp \rv, #3 @ so accept either
bne 90f
11: ubfx \rv, \rp, #15, #3 @ 17:15 are UART ID
11: lsr \rv, \rp, #15 @ 17:15 are UART ID
and \rv, #7
cmp \rv, #0 @ UART 0?
beq 20f
cmp \rv, #1 @ UART 1?
arch/arm/mach-at91/Kconfig
+21 -6
View File
@@ -57,6 +57,7 @@ config SOC_SAMA5
select GENERIC_CLOCKEVENTS
select MULTI_IRQ_HANDLER
select SPARSE_IRQ
select USE_OF
menu "Atmel AT91 System-on-Chip"
@@ -64,11 +65,22 @@ choice
prompt "Core type"
config SOC_SAM_V4_V5
bool "ARM7/ARM9"
config ARCH_AT91X40
bool "ARM7 AT91X40"
depends on !MMU
select CPU_ARM7TDMI
select ARCH_USES_GETTIMEOFFSET
select MULTI_IRQ_HANDLER
select SPARSE_IRQ
help
Select this if you are using one of Atmel's AT91SAM9, AT91RM9200
or AT91X40 SoC.
Select this if you are using one of Atmel's AT91X40 SoC.
config SOC_SAM_V4_V5
bool "ARM9 AT91SAM9/AT91RM9200"
help
Select this if you are using one of Atmel's AT91SAM9 or
AT91RM9200 SoC.
config SOC_SAM_V7
bool "Cortex A5"
@@ -179,10 +191,13 @@ config SOC_AT91SAM9N12
Select this if you are using Atmel's AT91SAM9N12 SoC.
# ----------------------------------------------------------
source arch/arm/mach-at91/Kconfig.non_dt
endif # SOC_SAM_V4_V5
if SOC_SAM_V4_V5 || ARCH_AT91X40
source arch/arm/mach-at91/Kconfig.non_dt
endif
comment "Generic Board Type"
config MACH_AT91RM9200_DT
arch/arm/mach-at91/Kconfig.non_dt
+1 -7
View File
@@ -5,6 +5,7 @@ config HAVE_AT91_DATAFLASH_CARD
choice
prompt "Atmel AT91 Processor Devices for non DT boards"
depends on !ARCH_AT91X40
config ARCH_AT91_NONE
bool "None"
@@ -39,13 +40,6 @@ config ARCH_AT91SAM9G45
select SOC_AT91SAM9G45
select AT91_USE_OLD_CLK
config ARCH_AT91X40
bool "AT91x40"
depends on !MMU
select ARCH_USES_GETTIMEOFFSET
select MULTI_IRQ_HANDLER
select SPARSE_IRQ
endchoice
config ARCH_AT91SAM9G20
arch/arm/mach-at91/at91sam9260_devices.c
+1 -5
View File
@@ -1255,12 +1255,8 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
at91_set_A_periph(AT91_PIN_PC10, 0); /* CFRNW */
at91_set_A_periph(AT91_PIN_PC15, 1); /* NWAIT */
if (data->flags & AT91_CF_TRUE_IDE)
#if defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE)
if (IS_ENABLED(CONFIG_PATA_AT91) && (data->flags & AT91_CF_TRUE_IDE)
pdev->name = "pata_at91";
#else
#warning "board requires AT91_CF_TRUE_IDE: enable pata_at91"
#endif
else
pdev->name = "at91_cf";
arch/arm/mach-at91/sam9_smc.c
+3
View File
@@ -36,6 +36,7 @@ void sam9_smc_write_mode(int id, int cs,
{
sam9_smc_cs_write_mode(AT91_SMC_CS(id, cs), config);
}
EXPORT_SYMBOL_GPL(sam9_smc_write_mode);
static void sam9_smc_cs_configure(void __iomem *base,
struct sam9_smc_config *config)
@@ -69,6 +70,7 @@ void sam9_smc_configure(int id, int cs,
{
sam9_smc_cs_configure(AT91_SMC_CS(id, cs), config);
}
EXPORT_SYMBOL_GPL(sam9_smc_configure);
static void sam9_smc_cs_read_mode(void __iomem *base,
struct sam9_smc_config *config)
@@ -84,6 +86,7 @@ void sam9_smc_read_mode(int id, int cs,
{
sam9_smc_cs_read_mode(AT91_SMC_CS(id, cs), config);
}
EXPORT_SYMBOL_GPL(sam9_smc_read_mode);
static void sam9_smc_cs_read(void __iomem *base,
struct sam9_smc_config *config)
arch/arm/mach-at91/setup.c
+1 -1
View File
@@ -351,7 +351,7 @@ void __init at91_ioremap_matrix(u32 base_addr)
panic("Impossible to ioremap at91_matrix_base\n");
}
#if defined(CONFIG_OF)
#if defined(CONFIG_OF) && !defined(CONFIG_ARCH_AT91X40)
static struct of_device_id rstc_ids[] = {
{ .compatible = "atmel,at91sam9260-rstc", .data = at91sam9_alt_restart },
{ .compatible = "atmel,at91sam9g45-rstc", .data = at91sam9g45_restart },
arch/arm/mach-davinci/Kconfig
-5
View File
@@ -214,11 +214,6 @@ config DA850_WL12XX
Say Y if you want to use a wl1271 expansion card connected to the
AM18x EVM.
config GPIO_PCA953X
default MACH_DAVINCI_DA850_EVM
config KEYBOARD_GPIO_POLLED
default MACH_DAVINCI_DA850_EVM
config MACH_TNETV107X
bool "TI TNETV107X Reference Platform"
arch/arm/mach-davinci/board-dm644x-evm.c
+6 -5
View File
@@ -799,11 +799,12 @@ static __init void davinci_evm_init(void)
/* irlml6401 switches over 1A, in under 8 msec */
davinci_setup_usb(1000, 8);
soc_info->emac_pdata->phy_id = DM644X_EVM_PHY_ID;
/* Register the fixup for PHY on DaVinci */
phy_register_fixup_for_uid(LXT971_PHY_ID, LXT971_PHY_MASK,
davinci_phy_fixup);
if (IS_BUILTIN(CONFIG_PHYLIB)) {
soc_info->emac_pdata->phy_id = DM644X_EVM_PHY_ID;
/* Register the fixup for PHY on DaVinci */
phy_register_fixup_for_uid(LXT971_PHY_ID, LXT971_PHY_MASK,
davinci_phy_fixup);
}
}
MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM")
arch/arm/mach-ep93xx/core.c
+1
View File
@@ -242,6 +242,7 @@ unsigned int ep93xx_chip_revision(void)
v >>= EP93XX_SYSCON_SYSCFG_REV_SHIFT;
return v;
}
EXPORT_SYMBOL_GPL(ep93xx_chip_revision);
/*************************************************************************
* EP93xx GPIO
arch/arm/mach-exynos/common.c
+4 -2
View File
@@ -404,8 +404,10 @@ static int __init exynos4_l2x0_cache_init(void)
if (ret)
return ret;
l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
if (IS_ENABLED(CONFIG_S5P_SLEEP)) {
l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
}
return 0;
}
early_initcall(exynos4_l2x0_cache_init);
arch/arm/mach-exynos/cpuidle.c
+1
View File
@@ -14,6 +14,7 @@
#include <linux/cpu_pm.h>
#include <linux/io.h>
#include <linux/export.h>
#include <linux/module.h>
#include <linux/time.h>
#include <linux/platform_device.h>
arch/arm/mach-footbridge/Kconfig
+1 -1
View File
@@ -52,6 +52,7 @@ config ARCH_EBSA285_HOST
select FOOTBRIDGE_HOST
select ISA
select ISA_DMA
select ARCH_MAY_HAVE_PC_FDC
select PCI
help
Say Y here if you intend to run this kernel on the EBSA285 card
@@ -94,6 +95,5 @@ config FOOTBRIDGE_ADDIN
# EBSA285 board in either host or addin mode
config ARCH_EBSA285
bool
select ARCH_MAY_HAVE_PC_FDC
endif
arch/arm/mach-footbridge/Makefile
+2 -1
View File
@@ -4,11 +4,12 @@
# Object file lists.
obj-y := common.o dc21285.o dma.o isa-irq.o
obj-y := common.o dma.o isa-irq.o
obj-m :=
obj-n :=
obj- :=
pci-y += dc21285.o
pci-$(CONFIG_ARCH_CATS) += cats-pci.o
pci-$(CONFIG_ARCH_EBSA285_HOST) += ebsa285-pci.o
pci-$(CONFIG_ARCH_NETWINDER) += netwinder-pci.o
arch/arm/mach-footbridge/cats-hw.c
+2
View File
@@ -78,9 +78,11 @@ __initcall(cats_hw_init);
static void __init
fixup_cats(struct tag *tags, char **cmdline, struct meminfo *mi)
{
#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
screen_info.orig_video_lines = 25;
screen_info.orig_video_points = 16;
screen_info.orig_y = 24;
#endif
}
MACHINE_START(CATS, "Chalice-CATS")
arch/arm/mach-hisi/Makefile
+1 -2
View File
@@ -3,5 +3,4 @@
#
obj-y += hisilicon.o
obj-$(CONFIG_SMP) += platsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
obj-$(CONFIG_SMP) += platsmp.o hotplug.o
arch/arm/mach-hisi/hotplug.c
+2
View File
@@ -178,6 +178,7 @@ static inline void cpu_enter_lowpower(void)
: "cc");
}
#ifdef CONFIG_HOTPLUG_CPU
void hi3xxx_cpu_die(unsigned int cpu)
{
cpu_enter_lowpower();
@@ -198,3 +199,4 @@ int hi3xxx_cpu_kill(unsigned int cpu)
hi3xxx_set_cpu(cpu, false);
return 1;
}
#endif
arch/arm/mach-integrator/Kconfig
+4 -4
View File
@@ -6,8 +6,8 @@ config ARCH_INTEGRATOR_AP
bool "Support Integrator/AP and Integrator/PP2 platforms"
select CLKSRC_MMIO
select MIGHT_HAVE_PCI
select SERIAL_AMBA_PL010
select SERIAL_AMBA_PL010_CONSOLE
select SERIAL_AMBA_PL010 if TTY
select SERIAL_AMBA_PL010_CONSOLE if TTY
select SOC_BUS
help
Include support for the ARM(R) Integrator/AP and
@@ -18,8 +18,8 @@ config ARCH_INTEGRATOR_CP
select ARCH_CINTEGRATOR
select ARM_TIMER_SP804
select PLAT_VERSATILE_CLCD
select SERIAL_AMBA_PL011
select SERIAL_AMBA_PL011_CONSOLE
select SERIAL_AMBA_PL011 if TTY
select SERIAL_AMBA_PL011_CONSOLE if TTY
select SOC_BUS
help
Include support for the ARM(R) Integrator CP platform.
arch/arm/mach-ixp4xx/common.c
+3 -3
View File
@@ -100,7 +100,7 @@ void __init ixp4xx_map_io(void)
#define IXP4XX_GPIO_CLK_0 14
#define IXP4XX_GPIO_CLK_1 15
static void gpio_line_config(u8 line, u32 direction)
void gpio_line_config(u8 line, u32 direction)
{
if (direction == IXP4XX_GPIO_IN)
*IXP4XX_GPIO_GPOER |= (1 << line);
@@ -108,12 +108,12 @@ static void gpio_line_config(u8 line, u32 direction)
*IXP4XX_GPIO_GPOER &= ~(1 << line);
}
static void gpio_line_get(u8 line, int *value)
void gpio_line_get(u8 line, int *value)
{
*value = (*IXP4XX_GPIO_GPINR >> line) & 0x1;
}
static void gpio_line_set(u8 line, int value)
void gpio_line_set(u8 line, int value)
{
if (value == IXP4XX_GPIO_HIGH)
*IXP4XX_GPIO_GPOUTR |= (1 << line);
arch/arm/mach-ixp4xx/goramo_mlr.c
+7
View File
@@ -17,6 +17,13 @@
#include <asm/mach/pci.h>
#include <asm/system_info.h>
#define IXP4XX_GPIO_OUT 0x1
#define IXP4XX_GPIO_IN 0x2
void gpio_line_config(u8 line, u32 direction);
void gpio_line_get(u8 line, int *value);
void gpio_line_set(u8 line, int value);
#define SLOT_ETHA 0x0B /* IDSEL = AD21 */
#define SLOT_ETHB 0x0C /* IDSEL = AD20 */
#define SLOT_MPCI 0x0D /* IDSEL = AD19 */
arch/arm/mach-ixp4xx/include/mach/io.h
+2 -1
View File
@@ -48,9 +48,10 @@ extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);
* fallback to the default.
*/
extern unsigned long pcibios_min_mem;
static inline int is_pci_memory(u32 addr)
{
return (addr >= PCIBIOS_MIN_MEM) && (addr <= 0x4FFFFFFF);
return (addr >= pcibios_min_mem) && (addr <= 0x4FFFFFFF);
}
#define writeb(v, p) __indirect_writeb(v, p)
arch/arm/mach-ixp4xx/omixp-setup.c
-2
View File
@@ -17,9 +17,7 @@
#include <linux/serial_8250.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#ifdef CONFIG_LEDS_CLASS
#include <linux/leds.h>
#endif
#include <asm/setup.h>
#include <asm/memory.h>
arch/arm/mach-ks8695/board-og.c
+2 -1
View File
@@ -44,7 +44,8 @@ static void __init og_register_pci(void)
if (machine_is_im4004())
ks8695_gpio_interrupt(KS8695_GPIO_1, IRQ_TYPE_LEVEL_LOW);
ks8695_init_pci(&og_pci);
if (IS_ENABLED(CONFIG_PCI))
ks8695_init_pci(&og_pci);
}
/*
arch/arm/mach-lpc32xx/common.c
+1
View File
@@ -99,6 +99,7 @@ u32 lpc32xx_return_iram_size(void)
return iram_size;
}
EXPORT_SYMBOL_GPL(lpc32xx_return_iram_size);
/*
* Computes PLL rate from PLL register and input clock
arch/arm/mach-msm/dma.c
+3
View File
@@ -18,6 +18,7 @@
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/completion.h>
#include <linux/module.h>
#include <mach/dma.h>
#include <mach/msm_iomap.h>
@@ -77,6 +78,7 @@ void msm_dmov_stop_cmd(unsigned id, struct msm_dmov_cmd *cmd, int graceful)
{
writel((graceful << 31), DMOV_FLUSH0(id));
}
EXPORT_SYMBOL_GPL(msm_dmov_stop_cmd);
void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd)
{
@@ -115,6 +117,7 @@ void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd)
}
spin_unlock_irqrestore(&msm_dmov_lock, irq_flags);
}
EXPORT_SYMBOL_GPL(msm_dmov_enqueue_cmd);
struct msm_dmov_exec_cmdptr_cmd {
struct msm_dmov_cmd dmov_cmd;
arch/arm/mach-msm/io.c
+2
View File
@@ -78,8 +78,10 @@ void __init msm_map_common_io(void)
asm("mcr p15, 0, %0, c15, c2, 4" : : "r" (0));
#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
defined(CONFIG_DEBUG_MSM_UART3)
#ifdef CONFIG_MMU
debug_ll_addr(&msm_io_desc[size - 1].pfn,
&msm_io_desc[size - 1].virtual);
#endif
msm_io_desc[size - 1].pfn = __phys_to_pfn(msm_io_desc[size - 1].pfn);
#endif
iotable_init(msm_io_desc, size);
arch/arm/mach-mvebu/armada-370-xp.c
+1
View File
@@ -21,6 +21,7 @@
#include <linux/clocksource.h>
#include <linux/dma-mapping.h>
#include <linux/mbus.h>
#include <linux/signal.h>
#include <linux/slab.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/arch.h>
arch/arm/mach-omap1/board-h2.c
+3
View File
@@ -318,6 +318,9 @@ static void __init h2_init_smc91x(void)
static int tps_setup(struct i2c_client *client, void *context)
{
if (!IS_BUILTIN(CONFIG_TPS65010))
return -ENOSYS;
tps65010_config_vregs1(TPS_LDO2_ENABLE | TPS_VLDO2_3_0V |
TPS_LDO1_ENABLE | TPS_VLDO1_3_0V);
arch/arm/mach-omap1/board-osk.c
+3
View File
@@ -191,6 +191,9 @@ static struct platform_device osk5912_tps_leds = {
static int osk_tps_setup(struct i2c_client *client, void *context)
{
if (!IS_BUILTIN(CONFIG_TPS65010))
return -ENOSYS;
/* Set GPIO 1 HIGH to disable VBUS power supply;
* OHCI driver powers it up/down as needed.
*/
arch/arm/mach-omap1/pm.c
+5 -1
View File
@@ -71,7 +71,11 @@ static unsigned int mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_SIZE];
static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
#ifdef CONFIG_OMAP_32K_TIMER
#ifndef CONFIG_OMAP_32K_TIMER
static unsigned short enable_dyn_sleep = 0;
#else
static unsigned short enable_dyn_sleep = 1;
arch/arm/mach-orion5x/Kconfig
-1
View File
@@ -33,7 +33,6 @@ config MACH_KUROBOX_PRO
config MACH_DNS323
bool "D-Link DNS-323"
select I2C_BOARDINFO
select PHYLIB
help
Say 'Y' here if you want your kernel to support the
D-Link DNS-323 platform.
arch/arm/mach-orion5x/dns323-setup.c
+2
View File
@@ -642,6 +642,8 @@ static void __init dns323_init(void)
platform_device_register_simple("dns323c-fan", 0, NULL, 0);
/* Register fixup for the PHY LEDs */
if (!IS_BUILTIN(CONFIG_PHYLIB))
break;
phy_register_fixup_for_uid(MARVELL_PHY_ID_88E1118,
MARVELL_PHY_ID_MASK,
dns323c_phy_fixup);
arch/arm/mach-pxa/Kconfig
+6 -3
View File
@@ -53,12 +53,16 @@ config MACH_TAVOREVB
select CPU_PXA930
select CPU_PXA935
select PXA3xx
select FB
select FB_PXA
config MACH_SAAR
bool "PXA930 Handheld Platform (aka SAAR)"
select CPU_PXA930
select CPU_PXA935
select PXA3xx
select FB
select FB_PXA
comment "Third Party Dev Platforms (sorted by vendor name)"
@@ -69,8 +73,7 @@ config ARCH_PXA_IDP
config ARCH_VIPER
bool "Arcom/Eurotech VIPER SBC"
select ARCOM_PCMCIA
select HAVE_PWM
select I2C_GPIO
select I2C_GPIO if I2C=y
select ISA
select PXA25x
select PXA_HAVE_ISA_IRQS
@@ -164,7 +167,6 @@ config MACH_XCEP
select MTD_CFI_INTELEXT
select MTD_PHYSMAP
select PXA25x
select SMC91X
help
PXA255 based Single Board Computer with SMC 91C111 ethernet chip and 64 MB of flash.
Tuned for usage in Libera instruments for particle accelerators.
@@ -181,6 +183,7 @@ config MACH_TRIZEPS4
config MACH_TRIZEPS4WL
bool "Keith und Koep Trizeps4-WL DIMM-Module"
depends on TRIZEPS_PXA
select MACH_TRIZEPS4
select PXA27x
select TRIZEPS_PCMCIA
arch/arm/mach-pxa/balloon3.c
-1
View File
@@ -331,7 +331,6 @@ static struct pxa2xx_udc_mach_info balloon3_udc_info __initdata = {
static void __init balloon3_udc_init(void)
{
pxa_set_udc_info(&balloon3_udc_info);
platform_device_register(&balloon3_gpio_vbus);
}
#else
static inline void balloon3_udc_init(void) {}
arch/arm/mach-pxa/colibri-evalboard.c
+1
View File
@@ -20,6 +20,7 @@
#include <asm/mach/arch.h>
#include <linux/i2c.h>
#include <linux/i2c/pxa-i2c.h>
#include <asm/io.h>
#include <mach/pxa27x.h>
#include <mach/colibri.h>
arch/arm/mach-realview/include/mach/memory.h
+2
View File
@@ -56,6 +56,8 @@
#define PAGE_OFFSET1 (PAGE_OFFSET + 0x10000000)
#define PAGE_OFFSET2 (PAGE_OFFSET + 0x30000000)
#define PHYS_OFFSET PLAT_PHYS_OFFSET
#define __phys_to_virt(phys) \
((phys) >= 0x80000000 ? (phys) - 0x80000000 + PAGE_OFFSET2 : \
(phys) >= 0x20000000 ? (phys) - 0x20000000 + PAGE_OFFSET1 : \
arch/arm/mach-s3c24xx/Kconfig
+2 -2
View File
@@ -537,7 +537,7 @@ config MACH_AT2440EVB
config MACH_MINI2440
bool "MINI2440 development board"
select EEPROM_AT24
select EEPROM_AT24 if I2C
select LEDS_CLASS
select LEDS_TRIGGERS
select LEDS_TRIGGER_BACKLIGHT
@@ -573,7 +573,7 @@ config MACH_OSIRIS
config MACH_OSIRIS_DVS
tristate "Simtec IM2440D20 (OSIRIS) Dynamic Voltage Scaling driver"
depends on MACH_OSIRIS
select TPS65010
depends on TPS65010
help
Say Y/M here if you want to have dynamic voltage scaling support
on the Simtec IM2440D20 (OSIRIS) module via the TPS65011.
arch/arm/mach-s3c24xx/mach-gta02.c
+1 -1
View File
@@ -196,7 +196,7 @@ static void gta02_charger_worker(struct work_struct *work)
* If the PCF50633 ADC is disabled we fallback to a
* 100mA limit for safety.
*/
pcf50633_mbc_usb_curlim_set(pcf, 100);
pcf50633_mbc_usb_curlim_set(gta02_pcf, 100);
#endif
}
arch/arm/mach-s3c64xx/Kconfig
+1 -2
View File
@@ -86,8 +86,7 @@ config MACH_SMDK6400
bool "SMDK6400"
select CPU_S3C6400
select S3C64XX_SETUP_SDHCI
select S3C_DEV_HSMMC
select S3C_DEV_NAND
select S3C_DEV_HSMMC1
help
Machine support for the Samsung SMDK6400
arch/arm/mach-s3c64xx/irq-pm.c
+9 -3
View File
@@ -55,7 +55,13 @@ static struct irq_grp_save {
u32 mask;
} eint_grp_save[5];
static u32 irq_uart_mask[CONFIG_SERIAL_SAMSUNG_UARTS];
#ifndef CONFIG_SERIAL_SAMSUNG_UARTS
#define SERIAL_SAMSUNG_UARTS 0
#else
#define SERIAL_SAMSUNG_UARTS CONFIG_SERIAL_SAMSUNG_UARTS
#endif
static u32 irq_uart_mask[SERIAL_SAMSUNG_UARTS];
static int s3c64xx_irq_pm_suspend(void)
{
@@ -66,7 +72,7 @@ static int s3c64xx_irq_pm_suspend(void)
s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++)
for (i = 0; i < SERIAL_SAMSUNG_UARTS; i++)
irq_uart_mask[i] = __raw_readl(S3C_VA_UARTx(i) + S3C64XX_UINTM);
for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
@@ -87,7 +93,7 @@ static void s3c64xx_irq_pm_resume(void)
s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++)
for (i = 0; i < SERIAL_SAMSUNG_UARTS; i++)
__raw_writel(irq_uart_mask[i], S3C_VA_UARTx(i) + S3C64XX_UINTM);
for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
arch/arm/mach-s5p64x0/common.c
+16 -2
View File
@@ -205,6 +205,7 @@ void __init s5p64x0_init_io(struct map_desc *mach_desc, int size)
samsung_pwm_set_platdata(&s5p64x0_pwm_variant);
}
#ifdef CONFIG_CPU_S5P6440
void __init s5p6440_map_io(void)
{
/* initialize any device information early */
@@ -218,7 +219,9 @@ void __init s5p6440_map_io(void)
iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc));
}
#endif
#ifdef CONFIG_CPU_S5P6450
void __init s5p6450_map_io(void)
{
/* initialize any device information early */
@@ -232,13 +235,14 @@ void __init s5p6450_map_io(void)
iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6450_iodesc));
}
#endif
/*
* s5p64x0_init_clocks
*
* register and setup the CPU clocks
*/
#ifdef CONFIG_CPU_S5P6440
void __init s5p6440_init_clocks(int xtal)
{
printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
@@ -248,7 +252,9 @@ void __init s5p6440_init_clocks(int xtal)
s5p6440_register_clocks();
s5p6440_setup_clocks();
}
#endif
#ifdef CONFIG_CPU_S5P6450
void __init s5p6450_init_clocks(int xtal)
{
printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
@@ -258,13 +264,14 @@ void __init s5p6450_init_clocks(int xtal)
s5p6450_register_clocks();
s5p6450_setup_clocks();
}
#endif
/*
* s5p64x0_init_irq
*
* register the CPU interrupts
*/
#ifdef CONFIG_CPU_S5P6440
void __init s5p6440_init_irq(void)
{
/* S5P6440 supports 2 VIC */
@@ -279,7 +286,9 @@ void __init s5p6440_init_irq(void)
s5p_init_irq(vic, ARRAY_SIZE(vic));
}
#endif
#ifdef CONFIG_CPU_S5P6450
void __init s5p6450_init_irq(void)
{
/* S5P6450 supports only 2 VIC */
@@ -294,6 +303,7 @@ void __init s5p6450_init_irq(void)
s5p_init_irq(vic, ARRAY_SIZE(vic));
}
#endif
struct bus_type s5p64x0_subsys = {
.name = "s5p64x0-core",
@@ -321,6 +331,7 @@ int __init s5p64x0_init(void)
}
/* uart registration process */
#ifdef CONFIG_CPU_S5P6440
void __init s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no)
{
int uart;
@@ -332,11 +343,14 @@ void __init s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no)
s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
}
#endif
#ifdef CONFIG_CPU_S5P6450
void __init s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no)
{
s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
}
#endif
#define eint_offset(irq) ((irq) - IRQ_EINT(0))
arch/arm/mach-s5p64x0/common.h
+1 -4
View File
@@ -25,10 +25,10 @@ void s5p6450_register_clocks(void);
void s5p6450_setup_clocks(void);
void s5p64x0_restart(enum reboot_mode mode, const char *cmd);
extern int s5p64x0_init(void);
#ifdef CONFIG_CPU_S5P6440
extern int s5p64x0_init(void);
extern void s5p6440_map_io(void);
extern void s5p6440_init_clocks(int xtal);
@@ -38,12 +38,10 @@ extern void s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no);
#define s5p6440_init_clocks NULL
#define s5p6440_init_uarts NULL
#define s5p6440_map_io NULL
#define s5p64x0_init NULL
#endif
#ifdef CONFIG_CPU_S5P6450
extern int s5p64x0_init(void);
extern void s5p6450_map_io(void);
extern void s5p6450_init_clocks(int xtal);
@@ -53,7 +51,6 @@ extern void s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no);
#define s5p6450_init_clocks NULL
#define s5p6450_init_uarts NULL
#define s5p6450_map_io NULL
#define s5p64x0_init NULL
#endif
#endif /* __ARCH_ARM_MACH_S5P64X0_COMMON_H */
arch/arm/mach-s5p64x0/irq-pm.c
+6
View File
@@ -34,7 +34,9 @@ static struct irq_grp_save {
u32 mask;
} eint_grp_save[4];
#ifdef CONFIG_SERIAL_SAMSUNG
static u32 irq_uart_mask[CONFIG_SERIAL_SAMSUNG_UARTS];
#endif
static int s5p64x0_irq_pm_suspend(void)
{
@@ -45,8 +47,10 @@ static int s5p64x0_irq_pm_suspend(void)
s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
#ifdef CONFIG_SERIAL_SAMSUNG
for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++)
irq_uart_mask[i] = __raw_readl(S3C_VA_UARTx(i) + S3C64XX_UINTM);
#endif
for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
grp->con = __raw_readl(S5P64X0_EINT12CON + (i * 4));
@@ -66,8 +70,10 @@ static void s5p64x0_irq_pm_resume(void)
s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
#ifdef CONFIG_SERIAL_SAMSUNG
for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++)
__raw_writel(irq_uart_mask[i], S3C_VA_UARTx(i) + S3C64XX_UINTM);
#endif
for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
__raw_writel(grp->con, S5P64X0_EINT12CON + (i * 4));
arch/arm/mach-s5pv210/Kconfig
+1
View File
@@ -189,6 +189,7 @@ config MACH_TORBRECK
select S5PV210_SETUP_I2C1
select S5PV210_SETUP_I2C2
select S5PV210_SETUP_SDHCI
select SAMSUNG_DEV_IDE
help
Machine support for aESOP Torbreck
arch/arm/mach-sunxi/Makefile
+1 -1
View File
@@ -1,2 +1,2 @@
obj-$(CONFIG_ARCH_SUNXI) += sunxi.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
obj-$(CONFIG_SMP) += platsmp.o
arch/arm/mach-sunxi/headsmp.S
-9
View File
@@ -1,9 +0,0 @@
#include <linux/linkage.h>
#include <linux/init.h>
.section ".text.head", "ax"
ENTRY(sun6i_secondary_startup)
msr cpsr_fsxc, #0xd3
b secondary_startup
ENDPROC(sun6i_secondary_startup)
arch/arm/mach-sunxi/platsmp.c
+1 -1
View File
@@ -82,7 +82,7 @@ static int sun6i_smp_boot_secondary(unsigned int cpu,
spin_lock(&cpu_lock);
/* Set CPU boot address */
writel(virt_to_phys(sun6i_secondary_startup),
writel(virt_to_phys(secondary_startup),
cpucfg_membase + CPUCFG_PRIVATE0_REG);
/* Assert the CPU core in reset */
arch/arm/mm/Kconfig
+1 -1
View File
@@ -264,7 +264,7 @@ config CPU_ARM1026
# SA110
config CPU_SA110
bool "Support StrongARM(R) SA-110 processor" if ARCH_RPC
bool
select CPU_32v3 if ARCH_RPC
select CPU_32v4 if !ARCH_RPC
select CPU_ABRT_EV4
arch/arm/plat-samsung/Kconfig
+3 -3
View File
@@ -427,8 +427,7 @@ comment "Power management"
config SAMSUNG_PM_DEBUG
bool "S3C2410 PM Suspend debug"
depends on PM
select DEBUG_LL
depends on PM && DEBUG_KERNEL && DEBUG_S3C_UART
help
Say Y here if you want verbose debugging from the PM Suspend and
Resume code. See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt>
@@ -445,7 +444,8 @@ config S3C_PM_DEBUG_LED_SMDK
config SAMSUNG_PM_CHECK
bool "S3C2410 PM Suspend Memory CRC"
depends on PM && CRC32
depends on PM
select CRC32
help
Enable the PM code's memory area checksum over sleep. This option
will generate CRCs of all blocks of memory, and store them before
arch/arm/plat-samsung/init.c
+4
View File
@@ -97,7 +97,9 @@ void __init s3c24xx_init_clocks(int xtal)
#if IS_ENABLED(CONFIG_SAMSUNG_ATAGS)
static int nr_uarts __initdata = 0;
#ifdef CONFIG_SERIAL_SAMSUNG_UARTS
static struct s3c2410_uartcfg uart_cfgs[CONFIG_SERIAL_SAMSUNG_UARTS];
#endif
/* s3c24xx_init_uartdevs
*
@@ -112,6 +114,7 @@ void __init s3c24xx_init_uartdevs(char *name,
struct s3c24xx_uart_resources *res,
struct s3c2410_uartcfg *cfg, int no)
{
#ifdef CONFIG_SERIAL_SAMSUNG_UARTS
struct platform_device *platdev;
struct s3c2410_uartcfg *cfgptr = uart_cfgs;
struct s3c24xx_uart_resources *resp;
@@ -134,6 +137,7 @@ void __init s3c24xx_init_uartdevs(char *name,
}
nr_uarts = no;
#endif
}
void __init s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
include/linux/pxa2xx_ssp.h
+1 -1
View File
@@ -219,7 +219,7 @@ static inline u32 pxa_ssp_read_reg(struct ssp_device *dev, u32 reg)
return __raw_readl(dev->mmio_base + reg);
}
#ifdef CONFIG_ARCH_PXA
#if IS_ENABLED(CONFIG_PXA_SSP)
struct ssp_device *pxa_ssp_request(int port, const char *label);
void pxa_ssp_free(struct ssp_device *);
struct ssp_device *pxa_ssp_request_of(const struct device_node *of_node,