clk: stm32mp13: add composite clock
Just to introduce management of stm32 composite clock. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Link: https://lore.kernel.org/r/20220516070600.7692-7-gabriel.fernandez@foss.st.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Gabriel Fernandez
committed by
Stephen Boyd
Stephen Boyd
parent
720e34ab3e
commit
5f0d47213f
@@ -389,6 +389,159 @@ const struct clk_ops clk_stm32_divider_ops = {
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.set_rate = clk_stm32_divider_set_rate,
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};
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static int clk_stm32_composite_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
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unsigned long flags = 0;
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int ret;
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if (composite->div_id == NO_STM32_DIV)
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return rate;
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spin_lock_irqsave(composite->lock, flags);
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ret = stm32_divider_set_rate(composite->base, composite->clock_data,
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composite->div_id, rate, parent_rate);
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spin_unlock_irqrestore(composite->lock, flags);
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return ret;
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}
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static unsigned long clk_stm32_composite_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
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if (composite->div_id == NO_STM32_DIV)
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return parent_rate;
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return stm32_divider_get_rate(composite->base, composite->clock_data,
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composite->div_id, parent_rate);
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}
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static long clk_stm32_composite_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
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const struct stm32_div_cfg *divider;
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if (composite->div_id == NO_STM32_DIV)
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return rate;
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divider = &composite->clock_data->dividers[composite->div_id];
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/* if read only, just return current value */
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if (divider->flags & CLK_DIVIDER_READ_ONLY) {
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u32 val;
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val = readl(composite->base + divider->offset) >> divider->shift;
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val &= clk_div_mask(divider->width);
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return divider_ro_round_rate(hw, rate, prate, divider->table,
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divider->width, divider->flags,
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val);
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}
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return divider_round_rate_parent(hw, clk_hw_get_parent(hw),
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rate, prate, divider->table,
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divider->width, divider->flags);
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}
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static u8 clk_stm32_composite_get_parent(struct clk_hw *hw)
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{
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struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
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return stm32_mux_get_parent(composite->base, composite->clock_data, composite->mux_id);
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}
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static int clk_stm32_composite_set_parent(struct clk_hw *hw, u8 index)
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{
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struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
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unsigned long flags = 0;
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spin_lock_irqsave(composite->lock, flags);
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stm32_mux_set_parent(composite->base, composite->clock_data, composite->mux_id, index);
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spin_unlock_irqrestore(composite->lock, flags);
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return 0;
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}
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static int clk_stm32_composite_is_enabled(struct clk_hw *hw)
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{
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struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
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if (composite->gate_id == NO_STM32_GATE)
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return (__clk_get_enable_count(hw->clk) > 0);
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return stm32_gate_is_enabled(composite->base, composite->clock_data, composite->gate_id);
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}
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static void clk_stm32_composite_gate_endisable(struct clk_hw *hw, int enable)
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{
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struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
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unsigned long flags = 0;
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spin_lock_irqsave(composite->lock, flags);
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stm32_gate_endisable(composite->base, composite->clock_data, composite->gate_id, enable);
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spin_unlock_irqrestore(composite->lock, flags);
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}
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static int clk_stm32_composite_gate_enable(struct clk_hw *hw)
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{
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struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
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if (composite->gate_id == NO_STM32_GATE)
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return 0;
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clk_stm32_composite_gate_endisable(hw, 1);
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return 0;
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}
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static void clk_stm32_composite_gate_disable(struct clk_hw *hw)
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{
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struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
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if (composite->gate_id == NO_STM32_GATE)
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return;
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clk_stm32_composite_gate_endisable(hw, 0);
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}
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static void clk_stm32_composite_disable_unused(struct clk_hw *hw)
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{
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struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
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unsigned long flags = 0;
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if (composite->gate_id == NO_STM32_GATE)
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return;
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spin_lock_irqsave(composite->lock, flags);
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stm32_gate_disable_unused(composite->base, composite->clock_data, composite->gate_id);
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spin_unlock_irqrestore(composite->lock, flags);
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}
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const struct clk_ops clk_stm32_composite_ops = {
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.set_rate = clk_stm32_composite_set_rate,
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.recalc_rate = clk_stm32_composite_recalc_rate,
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.round_rate = clk_stm32_composite_round_rate,
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.get_parent = clk_stm32_composite_get_parent,
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.set_parent = clk_stm32_composite_set_parent,
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.enable = clk_stm32_composite_gate_enable,
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.disable = clk_stm32_composite_gate_disable,
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.is_enabled = clk_stm32_composite_is_enabled,
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.disable_unused = clk_stm32_composite_disable_unused,
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};
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struct clk_hw *clk_stm32_mux_register(struct device *dev,
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const struct stm32_rcc_match_data *data,
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void __iomem *base,
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@@ -451,3 +604,24 @@ struct clk_hw *clk_stm32_div_register(struct device *dev,
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return hw;
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}
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struct clk_hw *clk_stm32_composite_register(struct device *dev,
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const struct stm32_rcc_match_data *data,
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void __iomem *base,
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spinlock_t *lock,
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const struct clock_config *cfg)
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{
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struct clk_stm32_composite *composite = cfg->clock_cfg;
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struct clk_hw *hw = &composite->hw;
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int err;
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composite->base = base;
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composite->lock = lock;
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composite->clock_data = data->clock_data;
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err = clk_hw_register(dev, hw);
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if (err)
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return ERR_PTR(err);
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return hw;
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}
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@@ -114,10 +114,23 @@ struct clk_stm32_div {
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#define to_clk_stm32_divider(_hw) container_of(_hw, struct clk_stm32_div, hw)
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struct clk_stm32_composite {
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u16 gate_id;
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u16 mux_id;
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u16 div_id;
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struct clk_hw hw;
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void __iomem *base;
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struct clk_stm32_clock_data *clock_data;
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spinlock_t *lock; /* spin lock */
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};
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#define to_clk_stm32_composite(_hw) container_of(_hw, struct clk_stm32_composite, hw)
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/* Clock operators */
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extern const struct clk_ops clk_stm32_mux_ops;
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extern const struct clk_ops clk_stm32_gate_ops;
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extern const struct clk_ops clk_stm32_divider_ops;
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extern const struct clk_ops clk_stm32_composite_ops;
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/* Clock registering */
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struct clk_hw *clk_stm32_mux_register(struct device *dev,
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@@ -138,6 +151,12 @@ struct clk_hw *clk_stm32_div_register(struct device *dev,
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spinlock_t *lock,
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const struct clock_config *cfg);
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struct clk_hw *clk_stm32_composite_register(struct device *dev,
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const struct stm32_rcc_match_data *data,
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void __iomem *base,
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spinlock_t *lock,
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const struct clock_config *cfg);
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#define STM32_CLOCK_CFG(_binding, _clk, _struct, _register)\
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{\
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.id = (_binding),\
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@@ -156,3 +175,7 @@ struct clk_hw *clk_stm32_div_register(struct device *dev,
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#define STM32_DIV_CFG(_binding, _clk)\
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STM32_CLOCK_CFG(_binding, &(_clk), struct clk_stm32_div *,\
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&clk_stm32_div_register)
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#define STM32_COMPOSITE_CFG(_binding, _clk)\
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STM32_CLOCK_CFG(_binding, &(_clk), struct clk_stm32_composite *,\
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&clk_stm32_composite_register)
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@@ -404,6 +404,14 @@ static const char * const eth12_src[] = {
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"pll4_p", "pll3_q"
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};
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static const char * const mco1_src[] = {
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"ck_hsi", "ck_hse", "ck_csi", "ck_lsi", "ck_lse"
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};
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static const char * const mco2_src[] = {
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"ck_mpu", "ck_axi", "ck_mlahb", "pll4_p", "ck_hse", "ck_hsi"
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};
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static struct clk_stm32_mux ck_ker_eth1 = {
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.mux_id = MUX_ETH1,
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.hw.init = CLK_HW_INIT_PARENTS("ck_ker_eth1", eth12_src, &clk_stm32_mux_ops,
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@@ -421,10 +429,30 @@ static struct clk_stm32_div eth1ptp_k = {
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CLK_SET_RATE_NO_REPARENT),
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};
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static struct clk_stm32_composite ck_mco1 = {
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.gate_id = GATE_MCO1,
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.mux_id = MUX_MCO1,
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.div_id = DIV_MCO1,
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.hw.init = CLK_HW_INIT_PARENTS("ck_mco1", mco1_src, &clk_stm32_composite_ops,
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CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT |
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CLK_IGNORE_UNUSED),
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};
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static struct clk_stm32_composite ck_mco2 = {
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.gate_id = GATE_MCO2,
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.mux_id = MUX_MCO2,
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.div_id = DIV_MCO2,
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.hw.init = CLK_HW_INIT_PARENTS("ck_mco2", mco2_src, &clk_stm32_composite_ops,
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CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT |
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CLK_IGNORE_UNUSED),
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};
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static const struct clock_config stm32mp13_clock_cfg[] = {
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STM32_MUX_CFG(NO_ID, ck_ker_eth1),
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STM32_GATE_CFG(ETH1CK_K, eth1ck_k),
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STM32_DIV_CFG(ETH1PTP_K, eth1ptp_k),
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STM32_COMPOSITE_CFG(CK_MCO1, ck_mco1),
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STM32_COMPOSITE_CFG(CK_MCO2, ck_mco2),
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};
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static u16 stm32mp13_cpt_gate[GATE_NB];
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