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drm/i915/display: Set C10_VDR_CTRL_MSGBUS_ACCESS before phy reg read

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According to C10 VDR Register programming sequence we need set
C10_VDR_CTRL_MSGBUS_ACCESS before accessing PHY internal registers from
MsgBus.

v2: set C10_VDR_CTRL_MSGBUS_ACCESS once for all owned lanes

Bspec: 68962
Fixes: 9dc619680d ("drm/i915/display: Add function to configure LFPS sending")
Suggested-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Link: https://lore.kernel.org/r/20250722125618.1842615-5-jouni.hogander@intel.com
(cherry picked from commit 8921dce70d)
Signed-off-by: Tvrtko Ursulin <tursulin@ursulin.net>
This commit is contained in:
Jouni Högander
2025-07-29 10:20:33 +01:00
committed by Tvrtko Ursulin
parent 3eb63578d8
commit 5a569ef4d4
1 changed files with 4 additions and 0 deletions
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drivers/gpu/drm/i915/display/intel_cx0_phy.c
+4
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@@ -3251,6 +3251,10 @@ void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
wakeref = intel_cx0_phy_transaction_begin(encoder);
if (intel_encoder_is_c10phy(encoder))
intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_CONTROL(1), 0,
C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED);
for (i = 0; i < 4; i++) {
int tx = i % 2 + 1;
u8 lane_mask = i < 2 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1;