Merge tag 'iommu-fixes-v5.15-rc0' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu
Pull iommu fixes from Joerg Roedel:
- Intel VT-d:
- PASID leakage in intel_svm_unbind_mm()
- Deadlock in intel_svm_drain_prq()
- AMD IOMMU: Fixes for an unhandled page-fault bug when AVIC is used
for a KVM guest.
- Make CONFIG_IOMMU_DEFAULT_DMA_LAZY architecture instead of IOMMU
driver dependent
* tag 'iommu-fixes-v5.15-rc0' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu:
iommu: Clarify default domain Kconfig
iommu/vt-d: Fix a deadlock in intel_svm_drain_prq()
iommu/vt-d: Fix PASID leak in intel_svm_unbind_mm()
iommu/amd: Remove iommu_init_ga()
iommu/amd: Relocate GAMSup check to early_enable_iommus
This commit is contained in:
@@ -82,7 +82,7 @@ config IOMMU_DEBUGFS
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choice
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prompt "IOMMU default domain type"
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depends on IOMMU_API
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default IOMMU_DEFAULT_DMA_LAZY if AMD_IOMMU || INTEL_IOMMU
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default IOMMU_DEFAULT_DMA_LAZY if X86 || IA64
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default IOMMU_DEFAULT_DMA_STRICT
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help
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Choose the type of IOMMU domain used to manage DMA API usage by
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+28
-20
@@ -297,6 +297,22 @@ int amd_iommu_get_num_iommus(void)
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return amd_iommus_present;
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}
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#ifdef CONFIG_IRQ_REMAP
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static bool check_feature_on_all_iommus(u64 mask)
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{
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bool ret = false;
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struct amd_iommu *iommu;
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for_each_iommu(iommu) {
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ret = iommu_feature(iommu, mask);
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if (!ret)
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return false;
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}
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return true;
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}
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#endif
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/*
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* For IVHD type 0x11/0x40, EFR is also available via IVHD.
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* Default to IVHD EFR since it is available sooner
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@@ -813,9 +829,9 @@ static int iommu_ga_log_enable(struct amd_iommu *iommu)
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return 0;
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}
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#ifdef CONFIG_IRQ_REMAP
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static int iommu_init_ga_log(struct amd_iommu *iommu)
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{
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#ifdef CONFIG_IRQ_REMAP
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u64 entry;
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if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
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@@ -845,25 +861,9 @@ static int iommu_init_ga_log(struct amd_iommu *iommu)
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err_out:
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free_ga_log(iommu);
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return -EINVAL;
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}
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#else
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return 0;
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#endif /* CONFIG_IRQ_REMAP */
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static int iommu_init_ga(struct amd_iommu *iommu)
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{
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int ret = 0;
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#ifdef CONFIG_IRQ_REMAP
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/* Note: We have already checked GASup from IVRS table.
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* Now, we need to make sure that GAMSup is set.
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*/
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if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
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!iommu_feature(iommu, FEATURE_GAM_VAPIC))
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amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA;
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ret = iommu_init_ga_log(iommu);
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#endif /* CONFIG_IRQ_REMAP */
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return ret;
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}
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static int __init alloc_cwwb_sem(struct amd_iommu *iommu)
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@@ -1845,7 +1845,7 @@ static int __init iommu_init_pci(struct amd_iommu *iommu)
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if (iommu_feature(iommu, FEATURE_PPR) && alloc_ppr_log(iommu))
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return -ENOMEM;
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ret = iommu_init_ga(iommu);
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ret = iommu_init_ga_log(iommu);
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if (ret)
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return ret;
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@@ -2479,6 +2479,14 @@ static void early_enable_iommus(void)
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}
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#ifdef CONFIG_IRQ_REMAP
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/*
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* Note: We have already checked GASup from IVRS table.
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* Now, we need to make sure that GAMSup is set.
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*/
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if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
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!check_feature_on_all_iommus(FEATURE_GAM_VAPIC))
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amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA;
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if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
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amd_iommu_irq_ops.capability |= (1 << IRQ_POSTING_CAP);
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#endif
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@@ -514,9 +514,6 @@ static void load_pasid(struct mm_struct *mm, u32 pasid)
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{
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mutex_lock(&mm->context.lock);
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/* Synchronize with READ_ONCE in update_pasid(). */
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smp_store_release(&mm->pasid, pasid);
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/* Update PASID MSR on all CPUs running the mm's tasks. */
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on_each_cpu_mask(mm_cpumask(mm), _load_pasid, NULL, true);
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@@ -792,7 +789,19 @@ prq_retry:
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goto prq_retry;
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}
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/*
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* A work in IO page fault workqueue may try to lock pasid_mutex now.
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* Holding pasid_mutex while waiting in iopf_queue_flush_dev() for
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* all works in the workqueue to finish may cause deadlock.
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*
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* It's unnecessary to hold pasid_mutex in iopf_queue_flush_dev().
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* Unlock it to allow the works to be handled while waiting for
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* them to finish.
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*/
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lockdep_assert_held(&pasid_mutex);
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mutex_unlock(&pasid_mutex);
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iopf_queue_flush_dev(dev);
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mutex_lock(&pasid_mutex);
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/*
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* Perform steps described in VT-d spec CH7.10 to drain page
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