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Merge tag 'riscv-dt-for-v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt

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RISC-V Devicetrees for v6.15

Starfive:
All changes for jh7110-based boards including the removal of a dac
that does not exist and the addition of usb3 support on the star64 board
and pcie on the framework mainboard.

Microchip:
Update pcie reg properties to fix a mistake originally describing them.
Here rather than in fixes, since the driver maintains support for the
old format.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

* tag 'riscv-dt-for-v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
  riscv: dts: starfive: jh7110-pine64-star64: enable USB 3.0 port
  riscv: dts: starfive: jh7110: pciephy0 USB 3.0 configuration registers
  riscv: dts: starfive: fml13v01: enable pcie1
  riscv: dts: starfive: remove non-existent dac from jh7110
  riscv: dts: starfive: Unify regulator naming scheme
  riscv: dts: microchip: update pcie reg properties to new format

Link: https://lore.kernel.org/r/20250318-favorite-presuming-bf2fcf55bf6a@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2025-03-19 22:15:12 +01:00
parent 370ce5aa40 38818f7c9c
commit 519df17cb0
7 changed files with 51 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
+3 -2
View File
@@ -32,8 +32,9 @@
#interrupt-cells = <0x1>;
#size-cells = <0x2>;
device_type = "pci";
reg = <0x30 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
reg-names = "cfg", "apb";
reg = <0x30 0x0 0x0 0x8000000>, <0x0 0x43008000 0x0 0x2000>,
<0x0 0x4300a000 0x0 0x2000>;
reg-names = "cfg", "bridge", "ctrl";
bus-range = <0x0 0x7f>;
interrupt-parent = <&plic>;
interrupts = <119>;
arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi
+3 -2
View File
@@ -20,8 +20,9 @@
#interrupt-cells = <0x1>;
#size-cells = <0x2>;
device_type = "pci";
reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
reg-names = "cfg", "apb";
reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43008000 0x0 0x2000>,
<0x0 0x4300a000 0x0 0x2000>;
reg-names = "cfg", "bridge", "ctrl";
bus-range = <0x0 0x7f>;
interrupt-parent = <&plic>;
interrupts = <119>;
arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
+3 -2
View File
@@ -20,8 +20,9 @@
#interrupt-cells = <0x1>;
#size-cells = <0x2>;
device_type = "pci";
reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
reg-names = "cfg", "apb";
reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43008000 0x0 0x2000>,
<0x0 0x4300a000 0x0 0x2000>;
reg-names = "cfg", "bridge", "ctrl";
bus-range = <0x0 0x7f>;
interrupt-parent = <&plic>;
interrupts = <119>;
arch/riscv/boot/dts/starfive/jh7110-common.dtsi
+1 -7
View File
@@ -233,7 +233,7 @@
regulator-always-on;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1540000>;
regulator-name = "vdd-cpu";
regulator-name = "vdd_cpu";
};
emmc_vdd: aldo4 {
@@ -350,12 +350,6 @@
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
spi_dev0: spi@0 {
compatible = "rohm,dh2228fv";
reg = <0>;
spi-max-frequency = <10000000>;
};
};
&syscrg {
arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
+34
View File
@@ -11,6 +11,40 @@
compatible = "deepcomputing,fml13v01", "starfive,jh7110";
};
&pcie1 {
perst-gpios = <&sysgpio 21 GPIO_ACTIVE_LOW>;
phys = <&pciephy1>;
pinctrl-names = "default";
pinctrl-0 = <&pcie1_pins>;
status = "okay";
};
&sysgpio {
pcie1_pins: pcie1-0 {
clkreq-pins {
pinmux = <GPIOMUX(29, GPOUT_LOW,
GPOEN_DISABLE,
GPI_NONE)>;
bias-pull-down;
drive-strength = <2>;
input-enable;
input-schmitt-disable;
slew-rate = <0>;
};
wake-pins {
pinmux = <GPIOMUX(28, GPOUT_HIGH,
GPOEN_DISABLE,
GPI_NONE)>;
bias-pull-up;
drive-strength = <2>;
input-enable;
input-schmitt-disable;
slew-rate = <0>;
};
};
};
&usb0 {
dr_mode = "host";
status = "okay";
arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts
+5
View File
@@ -100,3 +100,8 @@
pinctrl-0 = <&usb0_pins>;
status = "okay";
};
&usb_cdns3 {
phys = <&usbphy0>, <&pciephy0>;
phy-names = "cdns3,usb2-phy", "cdns3,usb3-phy";
};
arch/riscv/boot/dts/starfive/jh7110.dtsi
+2
View File
@@ -611,6 +611,8 @@
pciephy0: phy@10210000 {
compatible = "starfive,jh7110-pcie-phy";
reg = <0x0 0x10210000 0x0 0x10000>;
starfive,sys-syscon = <&sys_syscon 0x18>;
starfive,stg-syscon = <&stg_syscon 0x148 0x1f4>;
#phy-cells = <0>;
};