Merge tag 'mtk-clk-for-6.2' of https://git.kernel.org/pub/scm/linux/kernel/git/wens/linux into clk-mediatek
Pull MediaTek clk driver changes from Chen-Yu Tsai:
Some more cleanup work, and a new driver for frequency hopping
controller hardware.
- Remove flags from univ/main/syspll child fixed factor clocks across
MediaTek platforms
- The idea is to not have the clk core try to reconfigure the system
PLLs, i.e. have them be stable
- Fix clock dependency for ADC on MT7986
- New driver for frequency hopping controller hardware on MT8186
- This does frequency hopping and spread spectrum clocks in hardware
* tag 'mtk-clk-for-6.2' of https://git.kernel.org/pub/scm/linux/kernel/git/wens/linux:
clk: mediatek: fix dependency of MT7986 ADC clocks
clk: mediatek: Change PLL register API for MT8186
clk: mediatek: Add new clock driver to handle FHCTL hardware
dt-bindings: clock: mediatek: Add new bindings of MediaTek frequency hopping
clk: mediatek: Export PLL operations symbols
clk: mediatek: mt8186-topckgen: Add GPU clock mux notifier
clk: mediatek: mt8186-mfg: Propagate rate changes to parent
clk: mediatek: mt8195-topckgen: Drop flags for main/univpll fixed factors
clk: mediatek: mt8192: Drop flags for main/univpll fixed factors
clk: mediatek: mt6795-topckgen: Drop flags for main/sys/univpll fixed factors
clk: mediatek: mt8173: Drop flags for main/sys/univpll fixed factors
clk: mediatek: mt8183: Drop flags for sys/univpll fixed factors
clk: mediatek: mt8183: Compress top_divs array entries
clk: mediatek: mt8186-topckgen: Drop flags for main/univpll fixed factors
clk: mediatek: clk-mtk: Allow specifying flags on mtk_fixed_factor clocks
This commit is contained in:
Stephen Boyd
@@ -0,0 +1,53 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/mediatek,mt8186-fhctl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek frequency hopping and spread spectrum clocking control
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maintainers:
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- Edward-JW Yang <edward-jw.yang@mediatek.com>
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description: |
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Frequency hopping control (FHCTL) is a piece of hardware that control
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some PLLs to adopt "hopping" mechanism to adjust their frequency.
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Spread spectrum clocking (SSC) is another function provided by this hardware.
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properties:
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compatible:
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const: mediatek,mt8186-fhctl
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reg:
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maxItems: 1
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clocks:
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description: Phandles of the PLL with FHCTL hardware capability.
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minItems: 1
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maxItems: 30
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mediatek,hopping-ssc-percent:
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description: The percentage of spread spectrum clocking for one PLL.
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minItems: 1
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maxItems: 30
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items:
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default: 0
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minimum: 0
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maximum: 8
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required:
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- compatible
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- reg
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- clocks
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/mt8186-clk.h>
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fhctl: fhctl@1000ce00 {
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compatible = "mediatek,mt8186-fhctl";
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reg = <0x1000ce00 0x200>;
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clocks = <&apmixedsys CLK_APMIXED_MSDCPLL>;
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mediatek,hopping-ssc-percent = <3>;
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};
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@@ -11,6 +11,13 @@ config COMMON_CLK_MEDIATEK
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help
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MediaTek SoCs' clock support.
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config COMMON_CLK_MEDIATEK_FHCTL
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bool "clock driver for MediaTek FHCTL hardware control"
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select COMMON_CLK_MEDIATEK
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help
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This driver supports MediaTek frequency hopping and
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spread spectrum clocking features.
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config COMMON_CLK_MT2701
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bool "Clock driver for MediaTek MT2701"
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depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST
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@@ -553,6 +560,7 @@ config COMMON_CLK_MT8186
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bool "Clock driver for MediaTek MT8186"
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depends on ARM64 || COMPILE_TEST
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select COMMON_CLK_MEDIATEK
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select COMMON_CLK_MEDIATEK_FHCTL
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default ARCH_MEDIATEK
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help
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This driver supports MediaTek MT8186 clocks.
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@@ -1,5 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o reset.o clk-mux.o
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obj-$(CONFIG_COMMON_CLK_MEDIATEK_FHCTL) += clk-fhctl.o clk-pllfh.o
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obj-$(CONFIG_COMMON_CLK_MT6765) += clk-mt6765.o
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obj-$(CONFIG_COMMON_CLK_MT6765_AUDIOSYS) += clk-mt6765-audio.o
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@@ -0,0 +1,244 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Edward-JW Yang <edward-jw.yang@mediatek.com>
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*/
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include "clk-mtk.h"
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#include "clk-pllfh.h"
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#include "clk-fhctl.h"
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#define PERCENT_TO_DDSLMT(dds, percent_m10) \
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((((dds) * (percent_m10)) >> 5) / 100)
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static const struct fhctl_offset fhctl_offset = {
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.offset_hp_en = 0x0,
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.offset_clk_con = 0x8,
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.offset_rst_con = 0xc,
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.offset_slope0 = 0x10,
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.offset_slope1 = 0x14,
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.offset_cfg = 0x0,
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.offset_updnlmt = 0x4,
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.offset_dds = 0x8,
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.offset_dvfs = 0xc,
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.offset_mon = 0x10,
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};
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const struct fhctl_offset *fhctl_get_offset_table(void)
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{
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return &fhctl_offset;
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}
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static void dump_hw(struct mtk_clk_pll *pll, struct fh_pll_regs *regs,
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const struct fh_pll_data *data)
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{
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pr_info("hp_en<%x>,clk_con<%x>,slope0<%x>,slope1<%x>\n",
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readl(regs->reg_hp_en), readl(regs->reg_clk_con),
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readl(regs->reg_slope0), readl(regs->reg_slope1));
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pr_info("cfg<%x>,lmt<%x>,dds<%x>,dvfs<%x>,mon<%x>\n",
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readl(regs->reg_cfg), readl(regs->reg_updnlmt),
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readl(regs->reg_dds), readl(regs->reg_dvfs),
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readl(regs->reg_mon));
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pr_info("pcw<%x>\n", readl(pll->pcw_addr));
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}
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static int fhctl_set_ssc_regs(struct mtk_clk_pll *pll, struct fh_pll_regs *regs,
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const struct fh_pll_data *data, u32 rate)
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{
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u32 updnlmt_val, r;
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writel((readl(regs->reg_cfg) & ~(data->frddsx_en)), regs->reg_cfg);
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writel((readl(regs->reg_cfg) & ~(data->sfstrx_en)), regs->reg_cfg);
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writel((readl(regs->reg_cfg) & ~(data->fhctlx_en)), regs->reg_cfg);
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if (rate > 0) {
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/* Set the relative parameter registers (dt/df/upbnd/downbnd) */
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r = readl(regs->reg_cfg);
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r &= ~(data->msk_frddsx_dys);
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r |= (data->df_val << (ffs(data->msk_frddsx_dys) - 1));
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writel(r, regs->reg_cfg);
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r = readl(regs->reg_cfg);
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r &= ~(data->msk_frddsx_dts);
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r |= (data->dt_val << (ffs(data->msk_frddsx_dts) - 1));
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writel(r, regs->reg_cfg);
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writel((readl(pll->pcw_addr) & data->dds_mask) | data->tgl_org,
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regs->reg_dds);
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/* Calculate UPDNLMT */
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updnlmt_val = PERCENT_TO_DDSLMT((readl(regs->reg_dds) &
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data->dds_mask), rate) <<
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data->updnlmt_shft;
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writel(updnlmt_val, regs->reg_updnlmt);
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writel(readl(regs->reg_hp_en) | BIT(data->fh_id),
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regs->reg_hp_en);
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/* Enable SSC */
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writel(readl(regs->reg_cfg) | data->frddsx_en, regs->reg_cfg);
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/* Enable Hopping control */
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writel(readl(regs->reg_cfg) | data->fhctlx_en, regs->reg_cfg);
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} else {
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/* Switch to APMIXEDSYS control */
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writel(readl(regs->reg_hp_en) & ~BIT(data->fh_id),
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regs->reg_hp_en);
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/* Wait for DDS to be stable */
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udelay(30);
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}
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return 0;
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}
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static int hopping_hw_flow(struct mtk_clk_pll *pll, struct fh_pll_regs *regs,
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const struct fh_pll_data *data,
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struct fh_pll_state *state, unsigned int new_dds)
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{
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u32 dds_mask = data->dds_mask;
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u32 mon_dds = 0;
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u32 con_pcw_tmp;
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int ret;
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if (state->ssc_rate)
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fhctl_set_ssc_regs(pll, regs, data, 0);
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writel((readl(pll->pcw_addr) & dds_mask) | data->tgl_org,
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regs->reg_dds);
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writel(readl(regs->reg_cfg) | data->sfstrx_en, regs->reg_cfg);
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writel(readl(regs->reg_cfg) | data->fhctlx_en, regs->reg_cfg);
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writel(data->slope0_value, regs->reg_slope0);
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writel(data->slope1_value, regs->reg_slope1);
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writel(readl(regs->reg_hp_en) | BIT(data->fh_id), regs->reg_hp_en);
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writel((new_dds) | (data->dvfs_tri), regs->reg_dvfs);
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/* Wait 1000 us until DDS stable */
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ret = readl_poll_timeout_atomic(regs->reg_mon, mon_dds,
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(mon_dds & dds_mask) == new_dds,
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10, 1000);
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if (ret) {
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pr_warn("%s: FHCTL hopping timeout\n", pll->data->name);
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dump_hw(pll, regs, data);
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}
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con_pcw_tmp = readl(pll->pcw_addr) & (~dds_mask);
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con_pcw_tmp = (con_pcw_tmp | (readl(regs->reg_mon) & dds_mask) |
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data->pcwchg);
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writel(con_pcw_tmp, pll->pcw_addr);
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writel(readl(regs->reg_hp_en) & ~BIT(data->fh_id), regs->reg_hp_en);
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if (state->ssc_rate)
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fhctl_set_ssc_regs(pll, regs, data, state->ssc_rate);
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return ret;
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}
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static unsigned int __get_postdiv(struct mtk_clk_pll *pll)
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{
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unsigned int regval;
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regval = readl(pll->pd_addr) >> pll->data->pd_shift;
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regval &= POSTDIV_MASK;
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return BIT(regval);
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}
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static void __set_postdiv(struct mtk_clk_pll *pll, unsigned int postdiv)
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{
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unsigned int regval;
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regval = readl(pll->pd_addr);
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regval &= ~(POSTDIV_MASK << pll->data->pd_shift);
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regval |= (ffs(postdiv) - 1) << pll->data->pd_shift;
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writel(regval, pll->pd_addr);
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}
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static int fhctl_hopping(struct mtk_fh *fh, unsigned int new_dds,
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unsigned int postdiv)
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{
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const struct fh_pll_data *data = &fh->pllfh_data->data;
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struct fh_pll_state *state = &fh->pllfh_data->state;
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struct fh_pll_regs *regs = &fh->regs;
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struct mtk_clk_pll *pll = &fh->clk_pll;
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spinlock_t *lock = fh->lock;
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unsigned int pll_postdiv;
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unsigned long flags = 0;
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int ret;
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if (postdiv) {
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pll_postdiv = __get_postdiv(pll);
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if (postdiv > pll_postdiv)
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__set_postdiv(pll, postdiv);
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}
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spin_lock_irqsave(lock, flags);
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ret = hopping_hw_flow(pll, regs, data, state, new_dds);
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spin_unlock_irqrestore(lock, flags);
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if (postdiv && postdiv < pll_postdiv)
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__set_postdiv(pll, postdiv);
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return ret;
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}
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static int fhctl_ssc_enable(struct mtk_fh *fh, u32 rate)
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{
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const struct fh_pll_data *data = &fh->pllfh_data->data;
|
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struct fh_pll_state *state = &fh->pllfh_data->state;
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struct fh_pll_regs *regs = &fh->regs;
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struct mtk_clk_pll *pll = &fh->clk_pll;
|
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spinlock_t *lock = fh->lock;
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unsigned long flags = 0;
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spin_lock_irqsave(lock, flags);
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fhctl_set_ssc_regs(pll, regs, data, rate);
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state->ssc_rate = rate;
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|
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spin_unlock_irqrestore(lock, flags);
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return 0;
|
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}
|
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|
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static const struct fh_operation fhctl_ops = {
|
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.hopping = fhctl_hopping,
|
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.ssc_enable = fhctl_ssc_enable,
|
||||
};
|
||||
|
||||
const struct fh_operation *fhctl_get_ops(void)
|
||||
{
|
||||
return &fhctl_ops;
|
||||
}
|
||||
|
||||
void fhctl_hw_init(struct mtk_fh *fh)
|
||||
{
|
||||
const struct fh_pll_data data = fh->pllfh_data->data;
|
||||
struct fh_pll_state state = fh->pllfh_data->state;
|
||||
struct fh_pll_regs regs = fh->regs;
|
||||
u32 val;
|
||||
|
||||
/* initial hw register */
|
||||
val = readl(regs.reg_clk_con) | BIT(data.fh_id);
|
||||
writel(val, regs.reg_clk_con);
|
||||
|
||||
val = readl(regs.reg_rst_con) & ~BIT(data.fh_id);
|
||||
writel(val, regs.reg_rst_con);
|
||||
val = readl(regs.reg_rst_con) | BIT(data.fh_id);
|
||||
writel(val, regs.reg_rst_con);
|
||||
|
||||
writel(0x0, regs.reg_cfg);
|
||||
writel(0x0, regs.reg_updnlmt);
|
||||
writel(0x0, regs.reg_dds);
|
||||
|
||||
/* enable ssc if needed */
|
||||
if (state.ssc_rate)
|
||||
fh->ops->ssc_enable(fh, state.ssc_rate);
|
||||
}
|
||||
@@ -0,0 +1,26 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (c) 2022 MediaTek Inc.
|
||||
* Author: Edward-JW Yang <edward-jw.yang@mediatek.com>
|
||||
*/
|
||||
|
||||
#ifndef __CLK_FHCTL_H
|
||||
#define __CLK_FHCTL_H
|
||||
|
||||
struct fhctl_offset {
|
||||
u32 offset_hp_en;
|
||||
u32 offset_clk_con;
|
||||
u32 offset_rst_con;
|
||||
u32 offset_slope0;
|
||||
u32 offset_slope1;
|
||||
u32 offset_cfg;
|
||||
u32 offset_updnlmt;
|
||||
u32 offset_dds;
|
||||
u32 offset_dvfs;
|
||||
u32 offset_mon;
|
||||
};
|
||||
const struct fhctl_offset *fhctl_get_offset_table(void);
|
||||
const struct fh_operation *fhctl_get_ops(void);
|
||||
void fhctl_hw_init(struct mtk_fh *fh);
|
||||
|
||||
#endif
|
||||
@@ -359,19 +359,19 @@ static const struct mtk_fixed_factor top_divs[] = {
|
||||
FACTOR(CLK_TOP_ARMCA53PLL_754M, "armca53pll_754m", "clk26m", 1, 2),
|
||||
FACTOR(CLK_TOP_ARMCA53PLL_502M, "armca53pll_502m", "clk26m", 1, 3),
|
||||
|
||||
FACTOR(CLK_TOP_MAIN_H546M, "main_h546m", "mainpll", 1, 2),
|
||||
FACTOR(CLK_TOP_MAIN_H364M, "main_h364m", "mainpll", 1, 3),
|
||||
FACTOR(CLK_TOP_MAIN_H218P4M, "main_h218p4m", "mainpll", 1, 5),
|
||||
FACTOR(CLK_TOP_MAIN_H156M, "main_h156m", "mainpll", 1, 7),
|
||||
FACTOR_FLAGS(CLK_TOP_MAIN_H546M, "main_h546m", "mainpll", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_MAIN_H364M, "main_h364m", "mainpll", 1, 3, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_MAIN_H218P4M, "main_h218p4m", "mainpll", 1, 5, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_MAIN_H156M, "main_h156m", "mainpll", 1, 7, 0),
|
||||
|
||||
FACTOR(CLK_TOP_TVDPLL_445P5M, "tvdpll_445p5m", "tvdpll", 1, 4),
|
||||
FACTOR(CLK_TOP_TVDPLL_594M, "tvdpll_594m", "tvdpll", 1, 3),
|
||||
|
||||
FACTOR(CLK_TOP_UNIV_624M, "univ_624m", "univpll", 1, 2),
|
||||
FACTOR(CLK_TOP_UNIV_416M, "univ_416m", "univpll", 1, 3),
|
||||
FACTOR(CLK_TOP_UNIV_249P6M, "univ_249p6m", "univpll", 1, 5),
|
||||
FACTOR(CLK_TOP_UNIV_178P3M, "univ_178p3m", "univpll", 1, 7),
|
||||
FACTOR(CLK_TOP_UNIV_48M, "univ_48m", "univpll", 1, 26),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIV_624M, "univ_624m", "univpll", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIV_416M, "univ_416m", "univpll", 1, 3, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIV_249P6M, "univ_249p6m", "univpll", 1, 5, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIV_178P3M, "univ_178p3m", "univpll", 1, 7, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIV_48M, "univ_48m", "univpll", 1, 26, 0),
|
||||
|
||||
FACTOR(CLK_TOP_CLKRTC_EXT, "clkrtc_ext", "clk32k", 1, 1),
|
||||
FACTOR(CLK_TOP_CLKRTC_INT, "clkrtc_int", "clk26m", 1, 793),
|
||||
@@ -402,20 +402,20 @@ static const struct mtk_fixed_factor top_divs[] = {
|
||||
FACTOR(CLK_TOP_MSDCPLL2_D2, "msdcpll2_d2", "msdcpll2", 1, 2),
|
||||
FACTOR(CLK_TOP_MSDCPLL2_D4, "msdcpll2_d4", "msdcpll2", 1, 4),
|
||||
|
||||
FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "main_h546m", 1, 1),
|
||||
FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "main_h546m", 1, 2),
|
||||
FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "main_h546m", 1, 4),
|
||||
FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "main_h546m", 1, 8),
|
||||
FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "main_h546m", 1, 16),
|
||||
FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "main_h364m", 1, 1),
|
||||
FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "main_h364m", 1, 2),
|
||||
FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "main_h364m", 1, 4),
|
||||
FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "main_h218p4m", 1, 1),
|
||||
FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "main_h218p4m", 1, 2),
|
||||
FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "main_h218p4m", 1, 4),
|
||||
FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "main_h156m", 1, 1),
|
||||
FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "main_h156m", 1, 2),
|
||||
FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "main_h156m", 1, 4),
|
||||
FACTOR_FLAGS(CLK_TOP_SYSPLL_D2, "syspll_d2", "main_h546m", 1, 1, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "main_h546m", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "main_h546m", 1, 4, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "main_h546m", 1, 8, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "main_h546m", 1, 16, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_SYSPLL_D3, "syspll_d3", "main_h364m", 1, 1, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "main_h364m", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "main_h364m", 1, 4, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_SYSPLL_D5, "syspll_d5", "main_h218p4m", 1, 1, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "main_h218p4m", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "main_h218p4m", 1, 4, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_SYSPLL_D7, "syspll_d7", "main_h156m", 1, 1, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "main_h156m", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "main_h156m", 1, 4, 0),
|
||||
|
||||
FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll_594m", 1, 1),
|
||||
FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_594m", 1, 2),
|
||||
@@ -423,21 +423,21 @@ static const struct mtk_fixed_factor top_divs[] = {
|
||||
FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_594m", 1, 8),
|
||||
FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll_594m", 1, 16),
|
||||
|
||||
FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univ_624m", 1, 1),
|
||||
FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univ_624m", 1, 2),
|
||||
FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univ_624m", 1, 4),
|
||||
FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univ_624m", 1, 8),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univ_416m", 1, 1),
|
||||
FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univ_416m", 1, 2),
|
||||
FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univ_416m", 1, 4),
|
||||
FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univ_416m", 1, 8),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univ_249p6m", 1, 1),
|
||||
FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univ_249p6m", 1, 2),
|
||||
FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univ_249p6m", 1, 4),
|
||||
FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univ_249p6m", 1, 8),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univ_178p3m", 1, 1),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univ_48m", 1, 1),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univ_48m", 1, 2),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univ_624m", 1, 1, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univ_624m", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univ_624m", 1, 4, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univ_624m", 1, 8, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univ_416m", 1, 1, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univ_416m", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univ_416m", 1, 4, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univ_416m", 1, 8, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univ_249p6m", 1, 1, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univ_249p6m", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univ_249p6m", 1, 4, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univ_249p6m", 1, 8, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univ_178p3m", 1, 1, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univ_48m", 1, 1, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univ_48m", 1, 2, 0),
|
||||
|
||||
FACTOR(CLK_TOP_VCODECPLL, "vcodecpll_ck", "vcodecpll", 1, 3),
|
||||
FACTOR(CLK_TOP_VCODECPLL_370P5, "vcodecpll_370p5", "vcodecpll", 1, 4),
|
||||
|
||||
@@ -153,7 +153,7 @@ static const struct mtk_gate infra_clks[] = {
|
||||
18),
|
||||
GATE_INFRA1(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", "infra_sysaxi_d2",
|
||||
19),
|
||||
GATE_INFRA1(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", "csw_f26m_sel", 20),
|
||||
GATE_INFRA1(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", "infra_adc_frc", 20),
|
||||
GATE_INFRA1(CLK_INFRA_ADC_FRC_CK, "infra_adc_frc", "csw_f26m_sel", 21),
|
||||
GATE_INFRA1(CLK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", "nfi1x_sel", 23),
|
||||
/* INFRA2 */
|
||||
|
||||
@@ -37,19 +37,19 @@ static const struct mtk_fixed_factor top_divs[] __initconst = {
|
||||
FACTOR(CLK_TOP_ARMCA7PLL_754M, "armca7pll_754m", "armca7pll", 1, 2),
|
||||
FACTOR(CLK_TOP_ARMCA7PLL_502M, "armca7pll_502m", "armca7pll", 1, 3),
|
||||
|
||||
FACTOR(CLK_TOP_MAIN_H546M, "main_h546m", "mainpll", 1, 2),
|
||||
FACTOR(CLK_TOP_MAIN_H364M, "main_h364m", "mainpll", 1, 3),
|
||||
FACTOR(CLK_TOP_MAIN_H218P4M, "main_h218p4m", "mainpll", 1, 5),
|
||||
FACTOR(CLK_TOP_MAIN_H156M, "main_h156m", "mainpll", 1, 7),
|
||||
FACTOR_FLAGS(CLK_TOP_MAIN_H546M, "main_h546m", "mainpll", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_MAIN_H364M, "main_h364m", "mainpll", 1, 3, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_MAIN_H218P4M, "main_h218p4m", "mainpll", 1, 5, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_MAIN_H156M, "main_h156m", "mainpll", 1, 7, 0),
|
||||
|
||||
FACTOR(CLK_TOP_TVDPLL_445P5M, "tvdpll_445p5m", "tvdpll", 1, 4),
|
||||
FACTOR(CLK_TOP_TVDPLL_594M, "tvdpll_594m", "tvdpll", 1, 3),
|
||||
|
||||
FACTOR(CLK_TOP_UNIV_624M, "univ_624m", "univpll", 1, 2),
|
||||
FACTOR(CLK_TOP_UNIV_416M, "univ_416m", "univpll", 1, 3),
|
||||
FACTOR(CLK_TOP_UNIV_249P6M, "univ_249p6m", "univpll", 1, 5),
|
||||
FACTOR(CLK_TOP_UNIV_178P3M, "univ_178p3m", "univpll", 1, 7),
|
||||
FACTOR(CLK_TOP_UNIV_48M, "univ_48m", "univpll", 1, 26),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIV_624M, "univ_624m", "univpll", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIV_416M, "univ_416m", "univpll", 1, 3, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIV_249P6M, "univ_249p6m", "univpll", 1, 5, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIV_178P3M, "univ_178p3m", "univpll", 1, 7, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIV_48M, "univ_48m", "univpll", 1, 26, 0),
|
||||
|
||||
FACTOR(CLK_TOP_CLKRTC_EXT, "clkrtc_ext", "clk32k", 1, 1),
|
||||
FACTOR(CLK_TOP_CLKRTC_INT, "clkrtc_int", "clk26m", 1, 793),
|
||||
@@ -84,20 +84,20 @@ static const struct mtk_fixed_factor top_divs[] __initconst = {
|
||||
FACTOR(CLK_TOP_MSDCPLL2_D2, "msdcpll2_d2", "msdcpll2", 1, 2),
|
||||
FACTOR(CLK_TOP_MSDCPLL2_D4, "msdcpll2_d4", "msdcpll2", 1, 4),
|
||||
|
||||
FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "main_h546m", 1, 1),
|
||||
FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "main_h546m", 1, 2),
|
||||
FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "main_h546m", 1, 4),
|
||||
FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "main_h546m", 1, 8),
|
||||
FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "main_h546m", 1, 16),
|
||||
FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "main_h364m", 1, 1),
|
||||
FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "main_h364m", 1, 2),
|
||||
FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "main_h364m", 1, 4),
|
||||
FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "main_h218p4m", 1, 1),
|
||||
FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "main_h218p4m", 1, 2),
|
||||
FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "main_h218p4m", 1, 4),
|
||||
FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "main_h156m", 1, 1),
|
||||
FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "main_h156m", 1, 2),
|
||||
FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "main_h156m", 1, 4),
|
||||
FACTOR_FLAGS(CLK_TOP_SYSPLL_D2, "syspll_d2", "main_h546m", 1, 1, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "main_h546m", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "main_h546m", 1, 4, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "main_h546m", 1, 8, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "main_h546m", 1, 16, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_SYSPLL_D3, "syspll_d3", "main_h364m", 1, 1, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "main_h364m", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "main_h364m", 1, 4, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_SYSPLL_D5, "syspll_d5", "main_h218p4m", 1, 1, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "main_h218p4m", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "main_h218p4m", 1, 4, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_SYSPLL_D7, "syspll_d7", "main_h156m", 1, 1, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "main_h156m", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "main_h156m", 1, 4, 0),
|
||||
|
||||
FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll_594m", 1, 1),
|
||||
FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_594m", 1, 2),
|
||||
@@ -105,21 +105,21 @@ static const struct mtk_fixed_factor top_divs[] __initconst = {
|
||||
FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_594m", 1, 8),
|
||||
FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll_594m", 1, 16),
|
||||
|
||||
FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univ_624m", 1, 1),
|
||||
FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univ_624m", 1, 2),
|
||||
FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univ_624m", 1, 4),
|
||||
FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univ_624m", 1, 8),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univ_416m", 1, 1),
|
||||
FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univ_416m", 1, 2),
|
||||
FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univ_416m", 1, 4),
|
||||
FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univ_416m", 1, 8),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univ_249p6m", 1, 1),
|
||||
FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univ_249p6m", 1, 2),
|
||||
FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univ_249p6m", 1, 4),
|
||||
FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univ_249p6m", 1, 8),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univ_178p3m", 1, 1),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univ_48m", 1, 1),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univ_48m", 1, 2),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univ_624m", 1, 1, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univ_624m", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univ_624m", 1, 4, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univ_624m", 1, 8, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univ_416m", 1, 1, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univ_416m", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univ_416m", 1, 4, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univ_416m", 1, 8, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univ_249p6m", 1, 1, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univ_249p6m", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univ_249p6m", 1, 4, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univ_249p6m", 1, 8, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univ_178p3m", 1, 1, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univ_48m", 1, 1, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univ_48m", 1, 2, 0),
|
||||
|
||||
FACTOR(CLK_TOP_VCODECPLL, "vcodecpll_ck", "vcodecpll", 1, 3),
|
||||
FACTOR(CLK_TOP_VCODECPLL_370P5, "vcodecpll_370p5", "vcodecpll", 1, 4),
|
||||
|
||||
@@ -31,150 +31,78 @@ static const struct mtk_fixed_factor top_early_divs[] = {
|
||||
};
|
||||
|
||||
static const struct mtk_fixed_factor top_divs[] = {
|
||||
FACTOR(CLK_TOP_F26M_CK_D2, "csw_f26m_ck_d2", "clk26m", 1,
|
||||
2),
|
||||
FACTOR(CLK_TOP_SYSPLL_CK, "syspll_ck", "mainpll", 1,
|
||||
1),
|
||||
FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1,
|
||||
2),
|
||||
FACTOR(CLK_TOP_SYSPLL_D2_D2, "syspll_d2_d2", "syspll_d2", 1,
|
||||
2),
|
||||
FACTOR(CLK_TOP_SYSPLL_D2_D4, "syspll_d2_d4", "syspll_d2", 1,
|
||||
4),
|
||||
FACTOR(CLK_TOP_SYSPLL_D2_D8, "syspll_d2_d8", "syspll_d2", 1,
|
||||
8),
|
||||
FACTOR(CLK_TOP_SYSPLL_D2_D16, "syspll_d2_d16", "syspll_d2", 1,
|
||||
16),
|
||||
FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1,
|
||||
3),
|
||||
FACTOR(CLK_TOP_SYSPLL_D3_D2, "syspll_d3_d2", "syspll_d3", 1,
|
||||
2),
|
||||
FACTOR(CLK_TOP_SYSPLL_D3_D4, "syspll_d3_d4", "syspll_d3", 1,
|
||||
4),
|
||||
FACTOR(CLK_TOP_SYSPLL_D3_D8, "syspll_d3_d8", "syspll_d3", 1,
|
||||
8),
|
||||
FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1,
|
||||
5),
|
||||
FACTOR(CLK_TOP_SYSPLL_D5_D2, "syspll_d5_d2", "syspll_d5", 1,
|
||||
2),
|
||||
FACTOR(CLK_TOP_SYSPLL_D5_D4, "syspll_d5_d4", "syspll_d5", 1,
|
||||
4),
|
||||
FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1,
|
||||
7),
|
||||
FACTOR(CLK_TOP_SYSPLL_D7_D2, "syspll_d7_d2", "syspll_d7", 1,
|
||||
2),
|
||||
FACTOR(CLK_TOP_SYSPLL_D7_D4, "syspll_d7_d4", "syspll_d7", 1,
|
||||
4),
|
||||
FACTOR(CLK_TOP_UNIVPLL_CK, "univpll_ck", "univpll", 1,
|
||||
1),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1,
|
||||
2),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D2_D2, "univpll_d2_d2", "univpll_d2", 1,
|
||||
2),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D2_D4, "univpll_d2_d4", "univpll_d2", 1,
|
||||
4),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D2_D8, "univpll_d2_d8", "univpll_d2", 1,
|
||||
8),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1,
|
||||
3),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D3_D2, "univpll_d3_d2", "univpll_d3", 1,
|
||||
2),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D3_D4, "univpll_d3_d4", "univpll_d3", 1,
|
||||
4),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D3_D8, "univpll_d3_d8", "univpll_d3", 1,
|
||||
8),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1,
|
||||
5),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1,
|
||||
2),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1,
|
||||
4),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1,
|
||||
8),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1,
|
||||
7),
|
||||
FACTOR(CLK_TOP_UNIVP_192M_CK, "univ_192m_ck", "univpll_192m", 1,
|
||||
1),
|
||||
FACTOR(CLK_TOP_UNIVP_192M_D2, "univ_192m_d2", "univ_192m_ck", 1,
|
||||
2),
|
||||
FACTOR(CLK_TOP_UNIVP_192M_D4, "univ_192m_d4", "univ_192m_ck", 1,
|
||||
4),
|
||||
FACTOR(CLK_TOP_UNIVP_192M_D8, "univ_192m_d8", "univ_192m_ck", 1,
|
||||
8),
|
||||
FACTOR(CLK_TOP_UNIVP_192M_D16, "univ_192m_d16", "univ_192m_ck", 1,
|
||||
16),
|
||||
FACTOR(CLK_TOP_UNIVP_192M_D32, "univ_192m_d32", "univ_192m_ck", 1,
|
||||
32),
|
||||
FACTOR(CLK_TOP_APLL1_CK, "apll1_ck", "apll1", 1,
|
||||
1),
|
||||
FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1,
|
||||
2),
|
||||
FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1,
|
||||
4),
|
||||
FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1,
|
||||
8),
|
||||
FACTOR(CLK_TOP_APLL2_CK, "apll2_ck", "apll2", 1,
|
||||
1),
|
||||
FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1,
|
||||
2),
|
||||
FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1,
|
||||
4),
|
||||
FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1,
|
||||
8),
|
||||
FACTOR(CLK_TOP_TVDPLL_CK, "tvdpll_ck", "tvdpll", 1,
|
||||
1),
|
||||
FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1,
|
||||
2),
|
||||
FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1,
|
||||
4),
|
||||
FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll", 1,
|
||||
8),
|
||||
FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll", 1,
|
||||
16),
|
||||
FACTOR(CLK_TOP_MMPLL_CK, "mmpll_ck", "mmpll", 1,
|
||||
1),
|
||||
FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1,
|
||||
4),
|
||||
FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1,
|
||||
2),
|
||||
FACTOR(CLK_TOP_MMPLL_D4_D4, "mmpll_d4_d4", "mmpll_d4", 1,
|
||||
4),
|
||||
FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1,
|
||||
5),
|
||||
FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1,
|
||||
2),
|
||||
FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll_d5", 1,
|
||||
4),
|
||||
FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1,
|
||||
6),
|
||||
FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1,
|
||||
7),
|
||||
FACTOR(CLK_TOP_MFGPLL_CK, "mfgpll_ck", "mfgpll", 1,
|
||||
1),
|
||||
FACTOR(CLK_TOP_MSDCPLL_CK, "msdcpll_ck", "msdcpll", 1,
|
||||
1),
|
||||
FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1,
|
||||
2),
|
||||
FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1,
|
||||
4),
|
||||
FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1,
|
||||
8),
|
||||
FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16", "msdcpll", 1,
|
||||
16),
|
||||
FACTOR(CLK_TOP_AD_OSC_CK, "ad_osc_ck", "osc", 1,
|
||||
1),
|
||||
FACTOR(CLK_TOP_OSC_D2, "osc_d2", "osc", 1,
|
||||
2),
|
||||
FACTOR(CLK_TOP_OSC_D4, "osc_d4", "osc", 1,
|
||||
4),
|
||||
FACTOR(CLK_TOP_OSC_D8, "osc_d8", "osc", 1,
|
||||
8),
|
||||
FACTOR(CLK_TOP_OSC_D16, "osc_d16", "osc", 1,
|
||||
16),
|
||||
FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1,
|
||||
2),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D3_D16, "univpll_d3_d16", "univpll_d3", 1,
|
||||
16),
|
||||
FACTOR(CLK_TOP_F26M_CK_D2, "csw_f26m_ck_d2", "clk26m", 1, 2),
|
||||
FACTOR_FLAGS(CLK_TOP_SYSPLL_CK, "syspll_ck", "mainpll", 1, 1, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D2, "syspll_d2_d2", "syspll_d2", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D4, "syspll_d2_d4", "syspll_d2", 1, 4, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D8, "syspll_d2_d8", "syspll_d2", 1, 8, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D16, "syspll_d2_d16", "syspll_d2", 1, 16, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_SYSPLL_D3_D2, "syspll_d3_d2", "syspll_d3", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_SYSPLL_D3_D4, "syspll_d3_d4", "syspll_d3", 1, 4, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_SYSPLL_D3_D8, "syspll_d3_d8", "syspll_d3", 1, 8, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_SYSPLL_D5_D2, "syspll_d5_d2", "syspll_d5", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_SYSPLL_D5_D4, "syspll_d5_d4", "syspll_d5", 1, 4, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_SYSPLL_D7_D2, "syspll_d7_d2", "syspll_d7", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_SYSPLL_D7_D4, "syspll_d7_d4", "syspll_d7", 1, 4, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_CK, "univpll_ck", "univpll", 1, 1, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2_D2, "univpll_d2_d2", "univpll_d2", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2_D4, "univpll_d2_d4", "univpll_d2", 1, 4, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2_D8, "univpll_d2_d8", "univpll_d2", 1, 8, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3_D2, "univpll_d3_d2", "univpll_d3", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3_D4, "univpll_d3_d4", "univpll_d3", 1, 4, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3_D8, "univpll_d3_d8", "univpll_d3", 1, 8, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVP_192M_CK, "univ_192m_ck", "univpll_192m", 1, 1, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVP_192M_D2, "univ_192m_d2", "univ_192m_ck", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVP_192M_D4, "univ_192m_d4", "univ_192m_ck", 1, 4, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVP_192M_D8, "univ_192m_d8", "univ_192m_ck", 1, 8, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVP_192M_D16, "univ_192m_d16", "univ_192m_ck", 1, 16, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVP_192M_D32, "univ_192m_d32", "univ_192m_ck", 1, 32, 0),
|
||||
FACTOR(CLK_TOP_APLL1_CK, "apll1_ck", "apll1", 1, 1),
|
||||
FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1, 2),
|
||||
FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4),
|
||||
FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1, 8),
|
||||
FACTOR(CLK_TOP_APLL2_CK, "apll2_ck", "apll2", 1, 1),
|
||||
FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2),
|
||||
FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
|
||||
FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1, 8),
|
||||
FACTOR(CLK_TOP_TVDPLL_CK, "tvdpll_ck", "tvdpll", 1, 1),
|
||||
FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 2),
|
||||
FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4),
|
||||
FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll", 1, 8),
|
||||
FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll", 1, 16),
|
||||
FACTOR(CLK_TOP_MMPLL_CK, "mmpll_ck", "mmpll", 1, 1),
|
||||
FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4),
|
||||
FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1, 2),
|
||||
FACTOR(CLK_TOP_MMPLL_D4_D4, "mmpll_d4_d4", "mmpll_d4", 1, 4),
|
||||
FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5),
|
||||
FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1, 2),
|
||||
FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll_d5", 1, 4),
|
||||
FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1, 6),
|
||||
FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7),
|
||||
FACTOR(CLK_TOP_MFGPLL_CK, "mfgpll_ck", "mfgpll", 1, 1),
|
||||
FACTOR(CLK_TOP_MSDCPLL_CK, "msdcpll_ck", "msdcpll", 1, 1),
|
||||
FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
|
||||
FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
|
||||
FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1, 8),
|
||||
FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16", "msdcpll", 1, 16),
|
||||
FACTOR(CLK_TOP_AD_OSC_CK, "ad_osc_ck", "osc", 1, 1),
|
||||
FACTOR(CLK_TOP_OSC_D2, "osc_d2", "osc", 1, 2),
|
||||
FACTOR(CLK_TOP_OSC_D4, "osc_d4", "osc", 1, 4),
|
||||
FACTOR(CLK_TOP_OSC_D8, "osc_d8", "osc", 1, 8),
|
||||
FACTOR(CLK_TOP_OSC_D16, "osc_d16", "osc", 1, 16),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3_D16, "univpll_d3_d16", "univpll_d3", 1, 16, 0),
|
||||
};
|
||||
|
||||
static const char * const axi_parents[] = {
|
||||
|
||||
@@ -9,6 +9,7 @@
|
||||
|
||||
#include "clk-mtk.h"
|
||||
#include "clk-pll.h"
|
||||
#include "clk-pllfh.h"
|
||||
|
||||
#define MT8186_PLL_FMAX (3800UL * MHZ)
|
||||
#define MT8186_PLL_FMIN (1500UL * MHZ)
|
||||
@@ -76,6 +77,59 @@ static const struct mtk_pll_data plls[] = {
|
||||
0, 0, 32, 0x034C, 24, 0x0044, 0x000C, 5, 0x0350),
|
||||
};
|
||||
|
||||
enum fh_pll_id {
|
||||
FH_ARMPLL_LL,
|
||||
FH_ARMPLL_BL,
|
||||
FH_CCIPLL,
|
||||
FH_MAINPLL,
|
||||
FH_MMPLL,
|
||||
FH_TVDPLL,
|
||||
FH_RESERVE6,
|
||||
FH_ADSPPLL,
|
||||
FH_MFGPLL,
|
||||
FH_NNAPLL,
|
||||
FH_NNA2PLL,
|
||||
FH_MSDCPLL,
|
||||
FH_RESERVE12,
|
||||
FH_NR_FH,
|
||||
};
|
||||
|
||||
#define FH(_pllid, _fhid, _offset) { \
|
||||
.data = { \
|
||||
.pll_id = _pllid, \
|
||||
.fh_id = _fhid, \
|
||||
.fhx_offset = _offset, \
|
||||
.dds_mask = GENMASK(21, 0), \
|
||||
.slope0_value = 0x6003c97, \
|
||||
.slope1_value = 0x6003c97, \
|
||||
.sfstrx_en = BIT(2), \
|
||||
.frddsx_en = BIT(1), \
|
||||
.fhctlx_en = BIT(0), \
|
||||
.tgl_org = BIT(31), \
|
||||
.dvfs_tri = BIT(31), \
|
||||
.pcwchg = BIT(31), \
|
||||
.dt_val = 0x0, \
|
||||
.df_val = 0x9, \
|
||||
.updnlmt_shft = 16, \
|
||||
.msk_frddsx_dys = GENMASK(23, 20), \
|
||||
.msk_frddsx_dts = GENMASK(19, 16), \
|
||||
}, \
|
||||
}
|
||||
|
||||
static struct mtk_pllfh_data pllfhs[] = {
|
||||
FH(CLK_APMIXED_ARMPLL_LL, FH_ARMPLL_LL, 0x003C),
|
||||
FH(CLK_APMIXED_ARMPLL_BL, FH_ARMPLL_BL, 0x0050),
|
||||
FH(CLK_APMIXED_CCIPLL, FH_CCIPLL, 0x0064),
|
||||
FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x0078),
|
||||
FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0x008C),
|
||||
FH(CLK_APMIXED_TVDPLL, FH_TVDPLL, 0x00A0),
|
||||
FH(CLK_APMIXED_ADSPPLL, FH_ADSPPLL, 0x00C8),
|
||||
FH(CLK_APMIXED_MFGPLL, FH_MFGPLL, 0x00DC),
|
||||
FH(CLK_APMIXED_NNAPLL, FH_NNAPLL, 0x00F0),
|
||||
FH(CLK_APMIXED_NNA2PLL, FH_NNA2PLL, 0x0104),
|
||||
FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x0118),
|
||||
};
|
||||
|
||||
static const struct of_device_id of_match_clk_mt8186_apmixed[] = {
|
||||
{ .compatible = "mediatek,mt8186-apmixedsys", },
|
||||
{}
|
||||
@@ -85,13 +139,17 @@ static int clk_mt8186_apmixed_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
const u8 *fhctl_node = "mediatek,mt8186-fhctl";
|
||||
int r;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
|
||||
if (!clk_data)
|
||||
return -ENOMEM;
|
||||
|
||||
r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
|
||||
fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
|
||||
|
||||
r = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls),
|
||||
pllfhs, ARRAY_SIZE(pllfhs), clk_data);
|
||||
if (r)
|
||||
goto free_apmixed_data;
|
||||
|
||||
@@ -104,7 +162,8 @@ static int clk_mt8186_apmixed_probe(struct platform_device *pdev)
|
||||
return r;
|
||||
|
||||
unregister_plls:
|
||||
mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
|
||||
mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
|
||||
ARRAY_SIZE(pllfhs), clk_data);
|
||||
free_apmixed_data:
|
||||
mtk_free_clk_data(clk_data);
|
||||
return r;
|
||||
@@ -116,7 +175,8 @@ static int clk_mt8186_apmixed_remove(struct platform_device *pdev)
|
||||
struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
|
||||
|
||||
of_clk_del_provider(node);
|
||||
mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
|
||||
mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
|
||||
ARRAY_SIZE(pllfhs), clk_data);
|
||||
mtk_free_clk_data(clk_data);
|
||||
|
||||
return 0;
|
||||
|
||||
@@ -16,8 +16,9 @@ static const struct mtk_gate_regs mfg_cg_regs = {
|
||||
.sta_ofs = 0x0,
|
||||
};
|
||||
|
||||
#define GATE_MFG(_id, _name, _parent, _shift) \
|
||||
GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
|
||||
#define GATE_MFG(_id, _name, _parent, _shift) \
|
||||
GATE_MTK_FLAGS(_id, _name, _parent, &mfg_cg_regs, _shift, \
|
||||
&mtk_clk_gate_ops_setclr, CLK_SET_RATE_PARENT)
|
||||
|
||||
static const struct mtk_gate mfg_clks[] = {
|
||||
GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "top_mfg", 0),
|
||||
|
||||
@@ -19,37 +19,37 @@ static const struct mtk_fixed_clk top_fixed_clks[] = {
|
||||
};
|
||||
|
||||
static const struct mtk_fixed_factor top_divs[] = {
|
||||
FACTOR(CLK_TOP_MAINPLL_D2, "mainpll_d2", "mainpll", 1, 2),
|
||||
FACTOR(CLK_TOP_MAINPLL_D2_D2, "mainpll_d2_d2", "mainpll_d2", 1, 2),
|
||||
FACTOR(CLK_TOP_MAINPLL_D2_D4, "mainpll_d2_d4", "mainpll_d2", 1, 4),
|
||||
FACTOR(CLK_TOP_MAINPLL_D2_D16, "mainpll_d2_d16", "mainpll_d2", 1, 16),
|
||||
FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3),
|
||||
FACTOR(CLK_TOP_MAINPLL_D3_D2, "mainpll_d3_d2", "mainpll_d3", 1, 2),
|
||||
FACTOR(CLK_TOP_MAINPLL_D3_D4, "mainpll_d3_d4", "mainpll_d3", 1, 4),
|
||||
FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5),
|
||||
FACTOR(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2),
|
||||
FACTOR(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4),
|
||||
FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7),
|
||||
FACTOR(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2),
|
||||
FACTOR(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4),
|
||||
FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D2_D2, "univpll_d2_d2", "univpll_d2", 1, 2),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D2_D4, "univpll_d2_d4", "univpll_d2", 1, 4),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D3_D2, "univpll_d3_d2", "univpll_d3", 1, 2),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D3_D4, "univpll_d3_d4", "univpll_d3", 1, 4),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D3_D8, "univpll_d3_d8", "univpll_d3", 1, 8),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D3_D32, "univpll_d3_d32", "univpll_d3", 1, 32),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
|
||||
FACTOR(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univ2pll", 1, 13),
|
||||
FACTOR(CLK_TOP_UNIVPLL_192M_D4, "univpll_192m_d4", "univpll_192m", 1, 4),
|
||||
FACTOR(CLK_TOP_UNIVPLL_192M_D8, "univpll_192m_d8", "univpll_192m", 1, 8),
|
||||
FACTOR(CLK_TOP_UNIVPLL_192M_D16, "univpll_192m_d16", "univpll_192m", 1, 16),
|
||||
FACTOR(CLK_TOP_UNIVPLL_192M_D32, "univpll_192m_d32", "univpll_192m", 1, 32),
|
||||
FACTOR_FLAGS(CLK_TOP_MAINPLL_D2, "mainpll_d2", "mainpll", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_MAINPLL_D2_D2, "mainpll_d2_d2", "mainpll_d2", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_MAINPLL_D2_D4, "mainpll_d2_d4", "mainpll_d2", 1, 4, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_MAINPLL_D2_D16, "mainpll_d2_d16", "mainpll_d2", 1, 16, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_MAINPLL_D3_D2, "mainpll_d3_d2", "mainpll_d3", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_MAINPLL_D3_D4, "mainpll_d3_d4", "mainpll_d3", 1, 4, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2_D2, "univpll_d2_d2", "univpll_d2", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2_D4, "univpll_d2_d4", "univpll_d2", 1, 4, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3_D2, "univpll_d3_d2", "univpll_d3", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3_D4, "univpll_d3_d4", "univpll_d3", 1, 4, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3_D8, "univpll_d3_d8", "univpll_d3", 1, 8, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3_D32, "univpll_d3_d32", "univpll_d3", 1, 32, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univ2pll", 1, 13, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D4, "univpll_192m_d4", "univpll_192m", 1, 4, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D8, "univpll_192m_d8", "univpll_192m", 1, 8, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D16, "univpll_192m_d16", "univpll_192m", 1, 16, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D32, "univpll_192m_d32", "univpll_192m", 1, 32, 0),
|
||||
FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1, 2),
|
||||
FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4),
|
||||
FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1, 8),
|
||||
@@ -689,6 +689,28 @@ static const struct of_device_id of_match_clk_mt8186_topck[] = {
|
||||
{}
|
||||
};
|
||||
|
||||
/* Register mux notifier for MFG mux */
|
||||
static int clk_mt8186_reg_mfg_mux_notifier(struct device *dev, struct clk *clk)
|
||||
{
|
||||
struct mtk_mux_nb *mfg_mux_nb;
|
||||
int i;
|
||||
|
||||
mfg_mux_nb = devm_kzalloc(dev, sizeof(*mfg_mux_nb), GFP_KERNEL);
|
||||
if (!mfg_mux_nb)
|
||||
return -ENOMEM;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(top_mtk_muxes); i++)
|
||||
if (top_mtk_muxes[i].id == CLK_TOP_MFG)
|
||||
break;
|
||||
if (i == ARRAY_SIZE(top_mtk_muxes))
|
||||
return -EINVAL;
|
||||
|
||||
mfg_mux_nb->ops = top_mtk_muxes[i].ops;
|
||||
mfg_mux_nb->bypass_index = 0; /* Bypass to 26M crystal */
|
||||
|
||||
return devm_mtk_clk_mux_notifier_register(dev, clk, mfg_mux_nb);
|
||||
}
|
||||
|
||||
static int clk_mt8186_topck_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
@@ -730,6 +752,11 @@ static int clk_mt8186_topck_probe(struct platform_device *pdev)
|
||||
if (r)
|
||||
goto unregister_composite_muxes;
|
||||
|
||||
r = clk_mt8186_reg_mfg_mux_notifier(&pdev->dev,
|
||||
clk_data->hws[CLK_TOP_MFG]->clk);
|
||||
if (r)
|
||||
goto unregister_composite_divs;
|
||||
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (r)
|
||||
goto unregister_composite_divs;
|
||||
|
||||
@@ -31,38 +31,38 @@ static const struct mtk_fixed_factor top_early_divs[] = {
|
||||
};
|
||||
|
||||
static const struct mtk_fixed_factor top_divs[] = {
|
||||
FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3),
|
||||
FACTOR(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4),
|
||||
FACTOR(CLK_TOP_MAINPLL_D4_D2, "mainpll_d4_d2", "mainpll_d4", 1, 2),
|
||||
FACTOR(CLK_TOP_MAINPLL_D4_D4, "mainpll_d4_d4", "mainpll_d4", 1, 4),
|
||||
FACTOR(CLK_TOP_MAINPLL_D4_D8, "mainpll_d4_d8", "mainpll_d4", 1, 8),
|
||||
FACTOR(CLK_TOP_MAINPLL_D4_D16, "mainpll_d4_d16", "mainpll_d4", 1, 16),
|
||||
FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5),
|
||||
FACTOR(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2),
|
||||
FACTOR(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4),
|
||||
FACTOR(CLK_TOP_MAINPLL_D5_D8, "mainpll_d5_d8", "mainpll_d5", 1, 8),
|
||||
FACTOR(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6),
|
||||
FACTOR(CLK_TOP_MAINPLL_D6_D2, "mainpll_d6_d2", "mainpll_d6", 1, 2),
|
||||
FACTOR(CLK_TOP_MAINPLL_D6_D4, "mainpll_d6_d4", "mainpll_d6", 1, 4),
|
||||
FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7),
|
||||
FACTOR(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2),
|
||||
FACTOR(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4),
|
||||
FACTOR(CLK_TOP_MAINPLL_D7_D8, "mainpll_d7_d8", "mainpll_d7", 1, 8),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D4_D2, "univpll_d4_d2", "univpll_d4", 1, 2),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D4_D4, "univpll_d4_d4", "univpll_d4", 1, 4),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D4_D8, "univpll_d4_d8", "univpll_d4", 1, 8),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D6_D2, "univpll_d6_d2", "univpll_d6", 1, 2),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D6_D4, "univpll_d6_d4", "univpll_d6", 1, 4),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D6_D8, "univpll_d6_d8", "univpll_d6", 1, 8),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D6_D16, "univpll_d6_d16", "univpll_d6", 1, 16),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
|
||||
FACTOR_FLAGS(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D2, "mainpll_d4_d2", "mainpll_d4", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D4, "mainpll_d4_d4", "mainpll_d4", 1, 4, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D8, "mainpll_d4_d8", "mainpll_d4", 1, 8, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D16, "mainpll_d4_d16", "mainpll_d4", 1, 16, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D8, "mainpll_d5_d8", "mainpll_d5", 1, 8, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_MAINPLL_D6_D2, "mainpll_d6_d2", "mainpll_d6", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_MAINPLL_D6_D4, "mainpll_d6_d4", "mainpll_d6", 1, 4, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_MAINPLL_D7_D8, "mainpll_d7_d8", "mainpll_d7", 1, 8, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4_D2, "univpll_d4_d2", "univpll_d4", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4_D4, "univpll_d4_d4", "univpll_d4", 1, 4, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4_D8, "univpll_d4_d8", "univpll_d4", 1, 8, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6_D2, "univpll_d6_d2", "univpll_d6", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6_D4, "univpll_d6_d4", "univpll_d6", 1, 4, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6_D8, "univpll_d6_d8", "univpll_d6", 1, 8, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6_D16, "univpll_d6_d16", "univpll_d6", 1, 16, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7, 0),
|
||||
FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
|
||||
FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1, 2),
|
||||
FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4),
|
||||
@@ -96,12 +96,12 @@ static const struct mtk_fixed_factor top_divs[] = {
|
||||
FACTOR(CLK_TOP_OSC_D16, "osc_d16", "ulposc", 1, 16),
|
||||
FACTOR(CLK_TOP_OSC_D20, "osc_d20", "ulposc", 1, 20),
|
||||
FACTOR(CLK_TOP_ADSPPLL, "adsppll_ck", "adsppll", 1, 1),
|
||||
FACTOR(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univpll", 1, 13),
|
||||
FACTOR(CLK_TOP_UNIVPLL_192M_D2, "univpll_192m_d2", "univpll_192m", 1, 2),
|
||||
FACTOR(CLK_TOP_UNIVPLL_192M_D4, "univpll_192m_d4", "univpll_192m", 1, 4),
|
||||
FACTOR(CLK_TOP_UNIVPLL_192M_D8, "univpll_192m_d8", "univpll_192m", 1, 8),
|
||||
FACTOR(CLK_TOP_UNIVPLL_192M_D16, "univpll_192m_d16", "univpll_192m", 1, 16),
|
||||
FACTOR(CLK_TOP_UNIVPLL_192M_D32, "univpll_192m_d32", "univpll_192m", 1, 32),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univpll", 1, 13, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D2, "univpll_192m_d2", "univpll_192m", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D4, "univpll_192m_d4", "univpll_192m", 1, 4, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D8, "univpll_192m_d8", "univpll_192m", 1, 8, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D16, "univpll_192m_d16", "univpll_192m", 1, 16, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D32, "univpll_192m_d32", "univpll_192m", 1, 32, 0),
|
||||
};
|
||||
|
||||
static const char * const axi_parents[] = {
|
||||
|
||||
@@ -35,45 +35,45 @@ static const struct mtk_fixed_factor top_divs[] = {
|
||||
FACTOR(CLK_TOP_IN_DGI_D4, "in_dgi_d4", "in_dgi", 1, 4),
|
||||
FACTOR(CLK_TOP_IN_DGI_D6, "in_dgi_d6", "in_dgi", 1, 6),
|
||||
FACTOR(CLK_TOP_IN_DGI_D8, "in_dgi_d8", "in_dgi", 1, 8),
|
||||
FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3),
|
||||
FACTOR(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4),
|
||||
FACTOR(CLK_TOP_MAINPLL_D4_D2, "mainpll_d4_d2", "mainpll_d4", 1, 2),
|
||||
FACTOR(CLK_TOP_MAINPLL_D4_D4, "mainpll_d4_d4", "mainpll_d4", 1, 4),
|
||||
FACTOR(CLK_TOP_MAINPLL_D4_D8, "mainpll_d4_d8", "mainpll_d4", 1, 8),
|
||||
FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5),
|
||||
FACTOR(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2),
|
||||
FACTOR(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4),
|
||||
FACTOR(CLK_TOP_MAINPLL_D5_D8, "mainpll_d5_d8", "mainpll_d5", 1, 8),
|
||||
FACTOR(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6),
|
||||
FACTOR(CLK_TOP_MAINPLL_D6_D2, "mainpll_d6_d2", "mainpll_d6", 1, 2),
|
||||
FACTOR(CLK_TOP_MAINPLL_D6_D4, "mainpll_d6_d4", "mainpll_d6", 1, 4),
|
||||
FACTOR(CLK_TOP_MAINPLL_D6_D8, "mainpll_d6_d8", "mainpll_d6", 1, 8),
|
||||
FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7),
|
||||
FACTOR(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2),
|
||||
FACTOR(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4),
|
||||
FACTOR(CLK_TOP_MAINPLL_D7_D8, "mainpll_d7_d8", "mainpll_d7", 1, 8),
|
||||
FACTOR(CLK_TOP_MAINPLL_D9, "mainpll_d9", "mainpll", 1, 9),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D4_D2, "univpll_d4_d2", "univpll_d4", 1, 2),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D4_D4, "univpll_d4_d4", "univpll_d4", 1, 4),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D4_D8, "univpll_d4_d8", "univpll_d4", 1, 8),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D6_D2, "univpll_d6_d2", "univpll_d6", 1, 2),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D6_D4, "univpll_d6_d4", "univpll_d6", 1, 4),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D6_D8, "univpll_d6_d8", "univpll_d6", 1, 8),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D6_D16, "univpll_d6_d16", "univpll_d6", 1, 16),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
|
||||
FACTOR(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univpll", 1, 13),
|
||||
FACTOR(CLK_TOP_UNIVPLL_192M_D4, "univpll_192m_d4", "univpll_192m", 1, 4),
|
||||
FACTOR(CLK_TOP_UNIVPLL_192M_D8, "univpll_192m_d8", "univpll_192m", 1, 8),
|
||||
FACTOR(CLK_TOP_UNIVPLL_192M_D16, "univpll_192m_d16", "univpll_192m", 1, 16),
|
||||
FACTOR(CLK_TOP_UNIVPLL_192M_D32, "univpll_192m_d32", "univpll_192m", 1, 32),
|
||||
FACTOR_FLAGS(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D2, "mainpll_d4_d2", "mainpll_d4", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D4, "mainpll_d4_d4", "mainpll_d4", 1, 4, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D8, "mainpll_d4_d8", "mainpll_d4", 1, 8, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D8, "mainpll_d5_d8", "mainpll_d5", 1, 8, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_MAINPLL_D6_D2, "mainpll_d6_d2", "mainpll_d6", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_MAINPLL_D6_D4, "mainpll_d6_d4", "mainpll_d6", 1, 4, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_MAINPLL_D6_D8, "mainpll_d6_d8", "mainpll_d6", 1, 8, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_MAINPLL_D7_D8, "mainpll_d7_d8", "mainpll_d7", 1, 8, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_MAINPLL_D9, "mainpll_d9", "mainpll", 1, 9, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4_D2, "univpll_d4_d2", "univpll_d4", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4_D4, "univpll_d4_d4", "univpll_d4", 1, 4, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4_D8, "univpll_d4_d8", "univpll_d4", 1, 8, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6_D2, "univpll_d6_d2", "univpll_d6", 1, 2, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6_D4, "univpll_d6_d4", "univpll_d6", 1, 4, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6_D8, "univpll_d6_d8", "univpll_d6", 1, 8, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6_D16, "univpll_d6_d16", "univpll_d6", 1, 16, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univpll", 1, 13, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D4, "univpll_192m_d4", "univpll_192m", 1, 4, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D8, "univpll_192m_d8", "univpll_192m", 1, 8, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D16, "univpll_192m_d16", "univpll_192m", 1, 16, 0),
|
||||
FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D32, "univpll_192m_d32", "univpll_192m", 1, 32, 0),
|
||||
FACTOR(CLK_TOP_APLL1_D3, "apll1_d3", "apll1", 1, 3),
|
||||
FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4),
|
||||
FACTOR(CLK_TOP_APLL2_D3, "apll2_d3", "apll2", 1, 3),
|
||||
|
||||
@@ -149,7 +149,7 @@ int mtk_clk_register_factors(const struct mtk_fixed_factor *clks, int num,
|
||||
}
|
||||
|
||||
hw = clk_hw_register_fixed_factor(NULL, ff->name, ff->parent_name,
|
||||
CLK_SET_RATE_PARENT, ff->mult, ff->div);
|
||||
ff->flags, ff->mult, ff->div);
|
||||
|
||||
if (IS_ERR(hw)) {
|
||||
pr_err("Failed to register clk %s: %pe\n", ff->name,
|
||||
|
||||
@@ -47,16 +47,21 @@ struct mtk_fixed_factor {
|
||||
const char *parent_name;
|
||||
int mult;
|
||||
int div;
|
||||
unsigned long flags;
|
||||
};
|
||||
|
||||
#define FACTOR(_id, _name, _parent, _mult, _div) { \
|
||||
#define FACTOR_FLAGS(_id, _name, _parent, _mult, _div, _fl) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.mult = _mult, \
|
||||
.div = _div, \
|
||||
.flags = _fl, \
|
||||
}
|
||||
|
||||
#define FACTOR(_id, _name, _parent, _mult, _div) \
|
||||
FACTOR_FLAGS(_id, _name, _parent, _mult, _div, CLK_SET_RATE_PARENT)
|
||||
|
||||
int mtk_clk_register_factors(const struct mtk_fixed_factor *clks, int num,
|
||||
struct clk_hw_onecell_data *clk_data);
|
||||
void mtk_clk_unregister_factors(const struct mtk_fixed_factor *clks, int num,
|
||||
|
||||
@@ -27,37 +27,10 @@
|
||||
|
||||
#define AUDPLL_TUNER_EN BIT(31)
|
||||
|
||||
#define POSTDIV_MASK 0x7
|
||||
|
||||
/* default 7 bits integer, can be overridden with pcwibits. */
|
||||
#define INTEGER_BITS 7
|
||||
|
||||
/*
|
||||
* MediaTek PLLs are configured through their pcw value. The pcw value describes
|
||||
* a divider in the PLL feedback loop which consists of 7 bits for the integer
|
||||
* part and the remaining bits (if present) for the fractional part. Also they
|
||||
* have a 3 bit power-of-two post divider.
|
||||
*/
|
||||
|
||||
struct mtk_clk_pll {
|
||||
struct clk_hw hw;
|
||||
void __iomem *base_addr;
|
||||
void __iomem *pd_addr;
|
||||
void __iomem *pwr_addr;
|
||||
void __iomem *tuner_addr;
|
||||
void __iomem *tuner_en_addr;
|
||||
void __iomem *pcw_addr;
|
||||
void __iomem *pcw_chg_addr;
|
||||
void __iomem *en_addr;
|
||||
const struct mtk_pll_data *data;
|
||||
};
|
||||
|
||||
static inline struct mtk_clk_pll *to_mtk_clk_pll(struct clk_hw *hw)
|
||||
{
|
||||
return container_of(hw, struct mtk_clk_pll, hw);
|
||||
}
|
||||
|
||||
static int mtk_pll_is_prepared(struct clk_hw *hw)
|
||||
int mtk_pll_is_prepared(struct clk_hw *hw)
|
||||
{
|
||||
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
|
||||
|
||||
@@ -161,8 +134,8 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
|
||||
* @fin: The input frequency
|
||||
*
|
||||
*/
|
||||
static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
|
||||
u32 freq, u32 fin)
|
||||
void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
|
||||
u32 freq, u32 fin)
|
||||
{
|
||||
unsigned long fmin = pll->data->fmin ? pll->data->fmin : (1000 * MHZ);
|
||||
const struct mtk_pll_div_table *div_table = pll->data->div_table;
|
||||
@@ -198,8 +171,8 @@ static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
|
||||
*pcw = (u32)_pcw;
|
||||
}
|
||||
|
||||
static int mtk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
int mtk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
|
||||
u32 pcw = 0;
|
||||
@@ -211,8 +184,7 @@ static int mtk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static unsigned long mtk_pll_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
unsigned long mtk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
|
||||
{
|
||||
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
|
||||
u32 postdiv;
|
||||
@@ -227,8 +199,8 @@ static unsigned long mtk_pll_recalc_rate(struct clk_hw *hw,
|
||||
return __mtk_pll_recalc_rate(pll, parent_rate, pcw, postdiv);
|
||||
}
|
||||
|
||||
static long mtk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *prate)
|
||||
long mtk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *prate)
|
||||
{
|
||||
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
|
||||
u32 pcw = 0;
|
||||
@@ -239,7 +211,7 @@ static long mtk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
return __mtk_pll_recalc_rate(pll, *prate, pcw, postdiv);
|
||||
}
|
||||
|
||||
static int mtk_pll_prepare(struct clk_hw *hw)
|
||||
int mtk_pll_prepare(struct clk_hw *hw)
|
||||
{
|
||||
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
|
||||
u32 r;
|
||||
@@ -273,7 +245,7 @@ static int mtk_pll_prepare(struct clk_hw *hw)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void mtk_pll_unprepare(struct clk_hw *hw)
|
||||
void mtk_pll_unprepare(struct clk_hw *hw)
|
||||
{
|
||||
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
|
||||
u32 r;
|
||||
@@ -301,7 +273,7 @@ static void mtk_pll_unprepare(struct clk_hw *hw)
|
||||
writel(r, pll->pwr_addr);
|
||||
}
|
||||
|
||||
static const struct clk_ops mtk_pll_ops = {
|
||||
const struct clk_ops mtk_pll_ops = {
|
||||
.is_prepared = mtk_pll_is_prepared,
|
||||
.prepare = mtk_pll_prepare,
|
||||
.unprepare = mtk_pll_unprepare,
|
||||
@@ -310,18 +282,15 @@ static const struct clk_ops mtk_pll_ops = {
|
||||
.set_rate = mtk_pll_set_rate,
|
||||
};
|
||||
|
||||
static struct clk_hw *mtk_clk_register_pll(const struct mtk_pll_data *data,
|
||||
void __iomem *base)
|
||||
struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_pll *pll,
|
||||
const struct mtk_pll_data *data,
|
||||
void __iomem *base,
|
||||
const struct clk_ops *pll_ops)
|
||||
{
|
||||
struct mtk_clk_pll *pll;
|
||||
struct clk_init_data init = {};
|
||||
int ret;
|
||||
const char *parent_name = "clk26m";
|
||||
|
||||
pll = kzalloc(sizeof(*pll), GFP_KERNEL);
|
||||
if (!pll)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
pll->base_addr = base + data->reg;
|
||||
pll->pwr_addr = base + data->pwr_reg;
|
||||
pll->pd_addr = base + data->pd_reg;
|
||||
@@ -343,7 +312,7 @@ static struct clk_hw *mtk_clk_register_pll(const struct mtk_pll_data *data,
|
||||
|
||||
init.name = data->name;
|
||||
init.flags = (data->flags & PLL_AO) ? CLK_IS_CRITICAL : 0;
|
||||
init.ops = &mtk_pll_ops;
|
||||
init.ops = pll_ops;
|
||||
if (data->parent_name)
|
||||
init.parent_names = &data->parent_name;
|
||||
else
|
||||
@@ -360,7 +329,22 @@ static struct clk_hw *mtk_clk_register_pll(const struct mtk_pll_data *data,
|
||||
return &pll->hw;
|
||||
}
|
||||
|
||||
static void mtk_clk_unregister_pll(struct clk_hw *hw)
|
||||
struct clk_hw *mtk_clk_register_pll(const struct mtk_pll_data *data,
|
||||
void __iomem *base)
|
||||
{
|
||||
struct mtk_clk_pll *pll;
|
||||
struct clk_hw *hw;
|
||||
|
||||
pll = kzalloc(sizeof(*pll), GFP_KERNEL);
|
||||
if (!pll)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
hw = mtk_clk_register_pll_ops(pll, data, base, &mtk_pll_ops);
|
||||
|
||||
return hw;
|
||||
}
|
||||
|
||||
void mtk_clk_unregister_pll(struct clk_hw *hw)
|
||||
{
|
||||
struct mtk_clk_pll *pll;
|
||||
|
||||
@@ -423,8 +407,8 @@ err:
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(mtk_clk_register_plls);
|
||||
|
||||
static __iomem void *mtk_clk_pll_get_base(struct clk_hw *hw,
|
||||
const struct mtk_pll_data *data)
|
||||
__iomem void *mtk_clk_pll_get_base(struct clk_hw *hw,
|
||||
const struct mtk_pll_data *data)
|
||||
{
|
||||
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
|
||||
|
||||
|
||||
@@ -7,6 +7,7 @@
|
||||
#ifndef __DRV_CLK_MTK_PLL_H
|
||||
#define __DRV_CLK_MTK_PLL_H
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
struct clk_ops;
|
||||
@@ -20,6 +21,7 @@ struct mtk_pll_div_table {
|
||||
|
||||
#define HAVE_RST_BAR BIT(0)
|
||||
#define PLL_AO BIT(1)
|
||||
#define POSTDIV_MASK GENMASK(2, 0)
|
||||
|
||||
struct mtk_pll_data {
|
||||
int id;
|
||||
@@ -48,10 +50,63 @@ struct mtk_pll_data {
|
||||
u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */
|
||||
};
|
||||
|
||||
/*
|
||||
* MediaTek PLLs are configured through their pcw value. The pcw value describes
|
||||
* a divider in the PLL feedback loop which consists of 7 bits for the integer
|
||||
* part and the remaining bits (if present) for the fractional part. Also they
|
||||
* have a 3 bit power-of-two post divider.
|
||||
*/
|
||||
|
||||
struct mtk_clk_pll {
|
||||
struct clk_hw hw;
|
||||
void __iomem *base_addr;
|
||||
void __iomem *pd_addr;
|
||||
void __iomem *pwr_addr;
|
||||
void __iomem *tuner_addr;
|
||||
void __iomem *tuner_en_addr;
|
||||
void __iomem *pcw_addr;
|
||||
void __iomem *pcw_chg_addr;
|
||||
void __iomem *en_addr;
|
||||
const struct mtk_pll_data *data;
|
||||
};
|
||||
|
||||
int mtk_clk_register_plls(struct device_node *node,
|
||||
const struct mtk_pll_data *plls, int num_plls,
|
||||
struct clk_hw_onecell_data *clk_data);
|
||||
void mtk_clk_unregister_plls(const struct mtk_pll_data *plls, int num_plls,
|
||||
struct clk_hw_onecell_data *clk_data);
|
||||
|
||||
extern const struct clk_ops mtk_pll_ops;
|
||||
|
||||
static inline struct mtk_clk_pll *to_mtk_clk_pll(struct clk_hw *hw)
|
||||
{
|
||||
return container_of(hw, struct mtk_clk_pll, hw);
|
||||
}
|
||||
|
||||
int mtk_pll_is_prepared(struct clk_hw *hw);
|
||||
|
||||
int mtk_pll_prepare(struct clk_hw *hw);
|
||||
|
||||
void mtk_pll_unprepare(struct clk_hw *hw);
|
||||
|
||||
unsigned long mtk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate);
|
||||
|
||||
void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
|
||||
u32 freq, u32 fin);
|
||||
int mtk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate);
|
||||
long mtk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *prate);
|
||||
|
||||
struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_pll *pll,
|
||||
const struct mtk_pll_data *data,
|
||||
void __iomem *base,
|
||||
const struct clk_ops *pll_ops);
|
||||
struct clk_hw *mtk_clk_register_pll(const struct mtk_pll_data *data,
|
||||
void __iomem *base);
|
||||
void mtk_clk_unregister_pll(struct clk_hw *hw);
|
||||
|
||||
__iomem void *mtk_clk_pll_get_base(struct clk_hw *hw,
|
||||
const struct mtk_pll_data *data);
|
||||
|
||||
#endif /* __DRV_CLK_MTK_PLL_H */
|
||||
|
||||
@@ -0,0 +1,275 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (c) 2022 MediaTek Inc.
|
||||
* Author: Edward-JW Yang <edward-jw.yang@mediatek.com>
|
||||
*/
|
||||
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/delay.h>
|
||||
|
||||
#include "clk-mtk.h"
|
||||
#include "clk-pllfh.h"
|
||||
#include "clk-fhctl.h"
|
||||
|
||||
static DEFINE_SPINLOCK(pllfh_lock);
|
||||
|
||||
inline struct mtk_fh *to_mtk_fh(struct clk_hw *hw)
|
||||
{
|
||||
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
|
||||
|
||||
return container_of(pll, struct mtk_fh, clk_pll);
|
||||
}
|
||||
|
||||
static int mtk_fhctl_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
|
||||
struct mtk_fh *fh = to_mtk_fh(hw);
|
||||
u32 pcw = 0;
|
||||
u32 postdiv;
|
||||
|
||||
mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate);
|
||||
|
||||
return fh->ops->hopping(fh, pcw, postdiv);
|
||||
}
|
||||
|
||||
static const struct clk_ops mtk_pllfh_ops = {
|
||||
.is_prepared = mtk_pll_is_prepared,
|
||||
.prepare = mtk_pll_prepare,
|
||||
.unprepare = mtk_pll_unprepare,
|
||||
.recalc_rate = mtk_pll_recalc_rate,
|
||||
.round_rate = mtk_pll_round_rate,
|
||||
.set_rate = mtk_fhctl_set_rate,
|
||||
};
|
||||
|
||||
static struct mtk_pllfh_data *get_pllfh_by_id(struct mtk_pllfh_data *pllfhs,
|
||||
int num_fhs, int pll_id)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < num_fhs; i++)
|
||||
if (pllfhs[i].data.pll_id == pll_id)
|
||||
return &pllfhs[i];
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
void fhctl_parse_dt(const u8 *compatible_node, struct mtk_pllfh_data *pllfhs,
|
||||
int num_fhs)
|
||||
{
|
||||
void __iomem *base;
|
||||
struct device_node *node;
|
||||
u32 num_clocks, pll_id, ssc_rate;
|
||||
int offset, i;
|
||||
|
||||
node = of_find_compatible_node(NULL, NULL, compatible_node);
|
||||
if (!node) {
|
||||
pr_err("cannot find \"%s\"\n", compatible_node);
|
||||
return;
|
||||
}
|
||||
|
||||
base = of_iomap(node, 0);
|
||||
if (!base) {
|
||||
pr_err("%s(): ioremap failed\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
num_clocks = of_clk_get_parent_count(node);
|
||||
if (!num_clocks) {
|
||||
pr_err("%s(): failed to get clocks property\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
for (i = 0; i < num_clocks; i++) {
|
||||
struct mtk_pllfh_data *pllfh;
|
||||
|
||||
offset = i * 2;
|
||||
|
||||
of_property_read_u32_index(node, "clocks", offset + 1, &pll_id);
|
||||
of_property_read_u32_index(node,
|
||||
"mediatek,hopping-ssc-percent",
|
||||
i, &ssc_rate);
|
||||
|
||||
pllfh = get_pllfh_by_id(pllfhs, num_fhs, pll_id);
|
||||
if (!pllfh)
|
||||
continue;
|
||||
|
||||
pllfh->state.fh_enable = 1;
|
||||
pllfh->state.ssc_rate = ssc_rate;
|
||||
pllfh->state.base = base;
|
||||
}
|
||||
}
|
||||
|
||||
static void pllfh_init(struct mtk_fh *fh, struct mtk_pllfh_data *pllfh_data)
|
||||
{
|
||||
struct fh_pll_regs *regs = &fh->regs;
|
||||
const struct fhctl_offset *offset;
|
||||
void __iomem *base = pllfh_data->state.base;
|
||||
void __iomem *fhx_base = base + pllfh_data->data.fhx_offset;
|
||||
|
||||
offset = fhctl_get_offset_table();
|
||||
|
||||
regs->reg_hp_en = base + offset->offset_hp_en;
|
||||
regs->reg_clk_con = base + offset->offset_clk_con;
|
||||
regs->reg_rst_con = base + offset->offset_rst_con;
|
||||
regs->reg_slope0 = base + offset->offset_slope0;
|
||||
regs->reg_slope1 = base + offset->offset_slope1;
|
||||
|
||||
regs->reg_cfg = fhx_base + offset->offset_cfg;
|
||||
regs->reg_updnlmt = fhx_base + offset->offset_updnlmt;
|
||||
regs->reg_dds = fhx_base + offset->offset_dds;
|
||||
regs->reg_dvfs = fhx_base + offset->offset_dvfs;
|
||||
regs->reg_mon = fhx_base + offset->offset_mon;
|
||||
|
||||
fh->pllfh_data = pllfh_data;
|
||||
fh->lock = &pllfh_lock;
|
||||
|
||||
fh->ops = fhctl_get_ops();
|
||||
}
|
||||
|
||||
static bool fhctl_is_supported_and_enabled(const struct mtk_pllfh_data *pllfh)
|
||||
{
|
||||
return pllfh && (pllfh->state.fh_enable == 1);
|
||||
}
|
||||
|
||||
static struct clk_hw *
|
||||
mtk_clk_register_pllfh(const struct mtk_pll_data *pll_data,
|
||||
struct mtk_pllfh_data *pllfh_data, void __iomem *base)
|
||||
{
|
||||
struct clk_hw *hw;
|
||||
struct mtk_fh *fh;
|
||||
|
||||
fh = kzalloc(sizeof(*fh), GFP_KERNEL);
|
||||
if (!fh)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
pllfh_init(fh, pllfh_data);
|
||||
|
||||
hw = mtk_clk_register_pll_ops(&fh->clk_pll, pll_data, base,
|
||||
&mtk_pllfh_ops);
|
||||
|
||||
if (IS_ERR(hw))
|
||||
kfree(fh);
|
||||
else
|
||||
fhctl_hw_init(fh);
|
||||
|
||||
return hw;
|
||||
}
|
||||
|
||||
static void mtk_clk_unregister_pllfh(struct clk_hw *hw)
|
||||
{
|
||||
struct mtk_fh *fh;
|
||||
|
||||
if (!hw)
|
||||
return;
|
||||
|
||||
fh = to_mtk_fh(hw);
|
||||
|
||||
clk_hw_unregister(hw);
|
||||
kfree(fh);
|
||||
}
|
||||
|
||||
int mtk_clk_register_pllfhs(struct device_node *node,
|
||||
const struct mtk_pll_data *plls, int num_plls,
|
||||
struct mtk_pllfh_data *pllfhs, int num_fhs,
|
||||
struct clk_hw_onecell_data *clk_data)
|
||||
{
|
||||
void __iomem *base;
|
||||
int i;
|
||||
struct clk_hw *hw;
|
||||
|
||||
base = of_iomap(node, 0);
|
||||
if (!base) {
|
||||
pr_err("%s(): ioremap failed\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
for (i = 0; i < num_plls; i++) {
|
||||
const struct mtk_pll_data *pll = &plls[i];
|
||||
struct mtk_pllfh_data *pllfh;
|
||||
bool use_fhctl;
|
||||
|
||||
pllfh = get_pllfh_by_id(pllfhs, num_fhs, pll->id);
|
||||
use_fhctl = fhctl_is_supported_and_enabled(pllfh);
|
||||
|
||||
if (use_fhctl)
|
||||
hw = mtk_clk_register_pllfh(pll, pllfh, base);
|
||||
else
|
||||
hw = mtk_clk_register_pll(pll, base);
|
||||
|
||||
if (IS_ERR(hw)) {
|
||||
pr_err("Failed to register %s clk %s: %ld\n",
|
||||
use_fhctl ? "fhpll" : "pll", pll->name,
|
||||
PTR_ERR(hw));
|
||||
goto err;
|
||||
}
|
||||
|
||||
clk_data->hws[pll->id] = hw;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err:
|
||||
while (--i >= 0) {
|
||||
const struct mtk_pll_data *pll = &plls[i];
|
||||
struct mtk_pllfh_data *pllfh;
|
||||
bool use_fhctl;
|
||||
|
||||
pllfh = get_pllfh_by_id(pllfhs, num_fhs, pll->id);
|
||||
use_fhctl = fhctl_is_supported_and_enabled(pllfh);
|
||||
|
||||
if (use_fhctl)
|
||||
mtk_clk_unregister_pllfh(clk_data->hws[pll->id]);
|
||||
else
|
||||
mtk_clk_unregister_pll(clk_data->hws[pll->id]);
|
||||
|
||||
clk_data->hws[pll->id] = ERR_PTR(-ENOENT);
|
||||
}
|
||||
|
||||
iounmap(base);
|
||||
|
||||
return PTR_ERR(hw);
|
||||
}
|
||||
|
||||
void mtk_clk_unregister_pllfhs(const struct mtk_pll_data *plls, int num_plls,
|
||||
struct mtk_pllfh_data *pllfhs, int num_fhs,
|
||||
struct clk_hw_onecell_data *clk_data)
|
||||
{
|
||||
void __iomem *base = NULL, *fhctl_base = NULL;
|
||||
int i;
|
||||
|
||||
if (!clk_data)
|
||||
return;
|
||||
|
||||
for (i = num_plls; i > 0; i--) {
|
||||
const struct mtk_pll_data *pll = &plls[i - 1];
|
||||
struct mtk_pllfh_data *pllfh;
|
||||
bool use_fhctl;
|
||||
|
||||
if (IS_ERR_OR_NULL(clk_data->hws[pll->id]))
|
||||
continue;
|
||||
|
||||
pllfh = get_pllfh_by_id(pllfhs, num_fhs, pll->id);
|
||||
use_fhctl = fhctl_is_supported_and_enabled(pllfh);
|
||||
|
||||
if (use_fhctl) {
|
||||
fhctl_base = pllfh->state.base;
|
||||
mtk_clk_unregister_pllfh(clk_data->hws[pll->id]);
|
||||
} else {
|
||||
base = mtk_clk_pll_get_base(clk_data->hws[pll->id],
|
||||
pll);
|
||||
mtk_clk_unregister_pll(clk_data->hws[pll->id]);
|
||||
}
|
||||
|
||||
clk_data->hws[pll->id] = ERR_PTR(-ENOENT);
|
||||
}
|
||||
|
||||
if (fhctl_base)
|
||||
iounmap(fhctl_base);
|
||||
|
||||
iounmap(base);
|
||||
}
|
||||
@@ -0,0 +1,82 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (c) 2022 MediaTek Inc.
|
||||
* Author: Edward-JW Yang <edward-jw.yang@mediatek.com>
|
||||
*/
|
||||
|
||||
#ifndef __CLK_PLLFH_H
|
||||
#define __CLK_PLLFH_H
|
||||
|
||||
#include "clk-pll.h"
|
||||
|
||||
struct fh_pll_state {
|
||||
void __iomem *base;
|
||||
u32 fh_enable;
|
||||
u32 ssc_rate;
|
||||
};
|
||||
|
||||
struct fh_pll_data {
|
||||
int pll_id;
|
||||
int fh_id;
|
||||
u32 fhx_offset;
|
||||
u32 dds_mask;
|
||||
u32 slope0_value;
|
||||
u32 slope1_value;
|
||||
u32 sfstrx_en;
|
||||
u32 frddsx_en;
|
||||
u32 fhctlx_en;
|
||||
u32 tgl_org;
|
||||
u32 dvfs_tri;
|
||||
u32 pcwchg;
|
||||
u32 dt_val;
|
||||
u32 df_val;
|
||||
u32 updnlmt_shft;
|
||||
u32 msk_frddsx_dys;
|
||||
u32 msk_frddsx_dts;
|
||||
};
|
||||
|
||||
struct mtk_pllfh_data {
|
||||
struct fh_pll_state state;
|
||||
const struct fh_pll_data data;
|
||||
};
|
||||
|
||||
struct fh_pll_regs {
|
||||
void __iomem *reg_hp_en;
|
||||
void __iomem *reg_clk_con;
|
||||
void __iomem *reg_rst_con;
|
||||
void __iomem *reg_slope0;
|
||||
void __iomem *reg_slope1;
|
||||
void __iomem *reg_cfg;
|
||||
void __iomem *reg_updnlmt;
|
||||
void __iomem *reg_dds;
|
||||
void __iomem *reg_dvfs;
|
||||
void __iomem *reg_mon;
|
||||
};
|
||||
|
||||
struct mtk_fh {
|
||||
struct mtk_clk_pll clk_pll;
|
||||
struct fh_pll_regs regs;
|
||||
struct mtk_pllfh_data *pllfh_data;
|
||||
const struct fh_operation *ops;
|
||||
spinlock_t *lock;
|
||||
};
|
||||
|
||||
struct fh_operation {
|
||||
int (*hopping)(struct mtk_fh *fh, unsigned int new_dds,
|
||||
unsigned int postdiv);
|
||||
int (*ssc_enable)(struct mtk_fh *fh, u32 rate);
|
||||
};
|
||||
|
||||
int mtk_clk_register_pllfhs(struct device_node *node,
|
||||
const struct mtk_pll_data *plls, int num_plls,
|
||||
struct mtk_pllfh_data *pllfhs, int num_pllfhs,
|
||||
struct clk_hw_onecell_data *clk_data);
|
||||
|
||||
void mtk_clk_unregister_pllfhs(const struct mtk_pll_data *plls, int num_plls,
|
||||
struct mtk_pllfh_data *pllfhs, int num_fhs,
|
||||
struct clk_hw_onecell_data *clk_data);
|
||||
|
||||
void fhctl_parse_dt(const u8 *compatible_node, struct mtk_pllfh_data *pllfhs,
|
||||
int num_pllfhs);
|
||||
|
||||
#endif /* __CLK_PLLFH_H */
|
||||
Reference in New Issue
Block a user