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arm64: dts: ti: k3-am64: Add PCIe ctrl node to main_conf region

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This region is used for controlling the function of the PCIe IP. It is
compatible with "ti,j784s4-pcie-ctrl", add this here and use it with
the PCIe node.

Signed-off-by: Andrew Davis <afd@ti.com>
[j-choudhary@ti.com: Add changes to k3-am642-evm-pcie0-ep.dtso]
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Link: https://lore.kernel.org/r/20250402113201.151195-6-j-choudhary@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
This commit is contained in:
Andrew Davis
2025-04-18 13:28:12 -05:00
committed by Nishanth Menon
parent 755e47a71f
commit 4e7ad3b446
2 changed files with 7 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+6 -1
View File
@@ -51,6 +51,11 @@
reg = <0x00000014 0x4>;
};
pcie0_ctrl: pcie-ctrl@4070 {
compatible = "ti,j784s4-pcie-ctrl", "syscon";
reg = <0x4070 0x4>;
};
serdes_ln_ctrl: mux-controller@4080 {
compatible = "reg-mux";
reg = <0x4080 0x4>;
@@ -1036,7 +1041,7 @@
interrupt-names = "link_state";
interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
device_type = "pci";
ti,syscon-pcie-ctrl = <&main_conf 0x4070>;
ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
max-link-speed = <2>;
num-lanes = <1>;
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso
+1 -1
View File
@@ -46,6 +46,6 @@
max-functions = /bits/ 8 <1>;
phys = <&serdes0_pcie_link>;
phy-names = "pcie-phy";
ti,syscon-pcie-ctrl = <&main_conf 0x4070>;
ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
};
};