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Merge tag 'qcom-dts-for-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt

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Qualcomm dts updates for v5.15

This introduces the MSM8226 platform and an initial dts for the Samsung
Galaxy S III Neo phone.

MSM8974 gains another UART and this is used to enable Bluetooth on the
Sony Xperia Z2 Tablet. Samsung Galaxy S5 gains regulator definitions for
audio and modem remoteprocs, effectively enabling these.

DSI clocks on APQ8064 are updates as the old legacy clock names are no
longer supported by the driver. And IPQ806x GMAC nodes gains AHB resets
wired up.

Lastly APQ8060 is converted to a SPDX header and the ethernet node is
updates in accordance with the binding.

* tag 'qcom-dts-for-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
  ARM: dts: qcom: add ahb reset to ipq806x-gmac
  ARM: dts: qcom: Fix up APQ8060 DragonBoard license
  ARM: dts: qcom: msm8974: castor: Add Bluetooth-related nodes
  ARM: dts: qcom: msm8974: Add blsp2_uart7 for bluetooth on sirius
  ARM: dts: qcom: Add initial DTS file for Samsung Galaxy S III Neo phone
  dt-bindings: arm: qcom: Document MSM8226 SoC binding
  ARM: dts: qcom: Add support for MSM8226 SoC
  ARM: dts: qcom: apq8060: Correct Ethernet node name and drop bogus irq property
  ARM: dts: qcom: apq8064: correct clock names
  ARM: dts: qcom: msm8974-klte: Enable remote processors

Link: https://lore.kernel.org/r/20210816211957.579365-1-bjorn.andersson@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2021-08-17 11:30:41 +02:00
parent 9b35ab1e31 f95c4c56d6
commit 4d314179d6
10 changed files with 296 additions and 33 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Documentation/devicetree/bindings/arm/qcom.yaml
+6
View File
@@ -31,6 +31,7 @@ description: |
ipq6018
ipq8074
mdm9615
msm8226
msm8916
msm8974
msm8992
@@ -114,6 +115,11 @@ properties:
- qcom,apq8084-sbc
- const: qcom,apq8084
- items:
- enum:
- samsung,s3ve3g
- const: qcom,msm8226
- items:
- enum:
- qcom,msm8960-cdp
arch/arm/boot/dts/Makefile
+1
View File
@@ -957,6 +957,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-ipq4019-ap.dk07.1-c2.dtb \
qcom-ipq8064-ap148.dtb \
qcom-ipq8064-rb3011.dtb \
qcom-msm8226-samsung-s3ve3g.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
qcom-msm8974-fairphone-fp2.dtb \
arch/arm/boot/dts/qcom-apq8060-dragonboard.dts
+1 -22
View File
@@ -1,25 +1,4 @@
/*
* Copyright 2016 Linaro Ltd
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
// SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
arch/arm/boot/dts/qcom-apq8064.dtsi
+3 -3
View File
@@ -1262,9 +1262,9 @@
<&mmcc DSI1_BYTE_CLK>,
<&mmcc DSI_PIXEL_CLK>,
<&mmcc DSI1_ESC_CLK>;
clock-names = "iface_clk", "bus_clk", "core_mmss_clk",
"src_clk", "byte_clk", "pixel_clk",
"core_clk";
clock-names = "iface", "bus", "core_mmss",
"src", "byte", "pixel",
"core";
assigned-clocks = <&mmcc DSI1_BYTE_SRC>,
<&mmcc DSI1_ESC_SRC>,
arch/arm/boot/dts/qcom-ipq8064.dtsi
+12 -8
View File
@@ -980,8 +980,9 @@
clocks = <&gcc GMAC_CORE1_CLK>;
clock-names = "stmmaceth";
resets = <&gcc GMAC_CORE1_RESET>;
reset-names = "stmmaceth";
resets = <&gcc GMAC_CORE1_RESET>,
<&gcc GMAC_AHB_RESET>;
reset-names = "stmmaceth", "ahb";
status = "disabled";
};
@@ -1003,8 +1004,9 @@
clocks = <&gcc GMAC_CORE2_CLK>;
clock-names = "stmmaceth";
resets = <&gcc GMAC_CORE2_RESET>;
reset-names = "stmmaceth";
resets = <&gcc GMAC_CORE2_RESET>,
<&gcc GMAC_AHB_RESET>;
reset-names = "stmmaceth", "ahb";
status = "disabled";
};
@@ -1026,8 +1028,9 @@
clocks = <&gcc GMAC_CORE3_CLK>;
clock-names = "stmmaceth";
resets = <&gcc GMAC_CORE3_RESET>;
reset-names = "stmmaceth";
resets = <&gcc GMAC_CORE3_RESET>,
<&gcc GMAC_AHB_RESET>;
reset-names = "stmmaceth", "ahb";
status = "disabled";
};
@@ -1049,8 +1052,9 @@
clocks = <&gcc GMAC_CORE4_CLK>;
clock-names = "stmmaceth";
resets = <&gcc GMAC_CORE4_RESET>;
reset-names = "stmmaceth";
resets = <&gcc GMAC_CORE4_RESET>,
<&gcc GMAC_AHB_RESET>;
reset-names = "stmmaceth", "ahb";
status = "disabled";
};
arch/arm/boot/dts/qcom-msm8226-samsung-s3ve3g.dts
+25
View File
@@ -0,0 +1,25 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/
#include "qcom-msm8226.dtsi"
/ {
model = "Samsung Galaxy S III Neo";
compatible = "samsung,s3ve3g", "qcom,msm8226";
aliases {
serial0 = &blsp1_uart3;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&soc {
serial@f991f000 {
status = "ok"
};
};
arch/arm/boot/dts/qcom-msm8226.dtsi
+147
View File
@@ -0,0 +1,147 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/
/dts-v1/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8974.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&intc>;
chosen { };
memory@0 {
device_type = "memory";
reg = <0x0 0x0>;
};
soc: soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
intc: interrupt-controller@f9000000 {
compatible = "qcom,msm-qgic2";
reg = <0xf9000000 0x1000>,
<0xf9002000 0x1000>;
interrupt-controller;
#interrupt-cells = <3>;
};
gcc: clock-controller@fc400000 {
compatible = "qcom,gcc-msm8226";
reg = <0xfc400000 0x4000>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
tlmm: pinctrl@fd510000 {
compatible = "qcom,msm8226-pinctrl";
reg = <0xfd510000 0x4000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 117>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
};
blsp1_uart3: serial@f991f000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0xf991f000 0x1000>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
status = "disabled";
};
restart@fc4ab000 {
compatible = "qcom,pshold";
reg = <0xfc4ab000 0x4>;
};
rng@f9bff000 {
compatible = "qcom,prng";
reg = <0xf9bff000 0x200>;
clocks = <&gcc GCC_PRNG_AHB_CLK>;
clock-names = "core";
};
timer@f9020000 {
compatible = "arm,armv7-timer-mem";
reg = <0xf9020000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
frame@f9021000 {
frame-number = <0>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9021000 0x1000>,
<0xf9022000 0x1000>;
};
frame@f9023000 {
frame-number = <1>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9023000 0x1000>;
status = "disabled";
};
frame@f9024000 {
frame-number = <2>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9024000 0x1000>;
status = "disabled";
};
frame@f9025000 {
frame-number = <3>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9025000 0x1000>;
status = "disabled";
};
frame@f9026000 {
frame-number = <4>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9026000 0x1000>;
status = "disabled";
};
frame@f9027000 {
frame-number = <5>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9027000 0x1000>;
status = "disabled";
};
frame@f9028000 {
frame-number = <6>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9028000 0x1000>;
status = "disabled";
};
};
};
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 2
(GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 3
(GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 4
(GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 1
(GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>;
};
};
arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts
+11
View File
@@ -315,6 +315,10 @@
};
/delete-node/ vreg-boost;
adsp-pil {
cx-supply = <&pma8084_s2>;
};
};
&soc {
@@ -831,6 +835,13 @@
vddio-supply = <&pma8084_l12>;
};
};
remoteproc@fc880000 {
cx-supply = <&pma8084_s2>;
mss-supply = <&pma8084_s6>;
mx-supply = <&pma8084_s1>;
pll-supply = <&pma8084_l12>;
};
};
&spmi_bus {
arch/arm/boot/dts/qcom-msm8974-sony-xperia-castor.dts
+81
View File
@@ -11,6 +11,7 @@
aliases {
serial0 = &blsp1_uart2;
serial1 = &blsp2_uart7;
};
chosen {
@@ -336,6 +337,27 @@
pinctrl-0 = <&blsp1_uart2_pin_a>;
};
serial@f995d000 {
status = "ok"
pinctrl-names = "default";
pinctrl-0 = <&blsp2_uart7_pin_a>;
bluetooth {
compatible = "brcm,bcm43438-bt";
max-speed = <3000000>;
pinctrl-names = "default";
pinctrl-0 = <&bt_host_wake_pin>,
<&bt_dev_wake_pin>,
<&bt_reg_on_pin>;
host-wakeup-gpios = <&msmgpio 95 GPIO_ACTIVE_HIGH>;
device-wakeup-gpios = <&msmgpio 96 GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&pm8941_gpios 16 GPIO_ACTIVE_HIGH>;
};
};
usb@f9a55000 {
status = "okay";
@@ -380,6 +402,40 @@
};
};
blsp2_uart7_pin_a: blsp2-uart7-pin-active {
tx {
pins = "gpio41";
function = "blsp_uart7";
drive-strength = <2>;
bias-disable;
};
rx {
pins = "gpio42";
function = "blsp_uart7";
drive-strength = <2>;
bias-pull-up;
};
cts {
pins = "gpio43";
function = "blsp_uart7";
drive-strength = <2>;
bias-pull-up;
};
rts {
pins = "gpio44";
function = "blsp_uart7";
drive-strength = <2>;
bias-disable;
};
};
i2c8_pins: i2c8 {
mux {
pins = "gpio47", "gpio48";
@@ -479,6 +535,23 @@
input-enable;
};
};
bt_host_wake_pin: bt-host-wake {
pins = "gpio95";
function = "gpio";
drive-strength = <2>;
bias-disable;
output-low;
};
bt_dev_wake_pin: bt-dev-wake {
pins = "gpio96";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
};
i2c@f9964000 {
@@ -606,6 +679,14 @@
power-source = <PM8941_GPIO_S3>;
};
bt_reg_on_pin: bt-reg-on {
pins = "gpio16";
function = "normal";
output-low;
power-source = <PM8941_GPIO_S3>;
};
wlan_sleep_clk_pin: wl-sleep-clk {
pins = "gpio17";
function = "func2";
arch/arm/boot/dts/qcom-msm8974.dtsi
+9
View File
@@ -715,6 +715,15 @@
status = "disabled";
};
blsp2_uart7: serial@f995d000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0xf995d000 0x1000>;
interrupts = <GIC_SPI 113 IRQ_TYPE_NONE>;
clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
status = "disabled";
};
blsp2_uart8: serial@f995e000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0xf995e000 0x1000>;