arm64: dts: qcom: lemans: Add CCI definitions
Qualcomm SA8775P SoC contains 4 Camera Control Interface controllers. Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Wenmeng Liu <quic_wenmliu@qualcomm.com> Link: https://lore.kernel.org/r/20250912-camss_rb8-v6-2-c9a6c3d67392@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Wenmeng Liu
committed by
Bjorn Andersson
Bjorn Andersson
parent
a19c879b69
commit
3964a91e55
@@ -4411,6 +4411,162 @@
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#power-domain-cells = <1>;
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};
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cci0: cci@ac13000 {
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compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci";
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reg = <0x0 0x0ac13000 0x0 0x1000>;
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interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
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power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
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clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
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<&camcc CAM_CC_CPAS_AHB_CLK>,
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<&camcc CAM_CC_CCI_0_CLK>;
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clock-names = "camnoc_axi",
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"cpas_ahb",
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"cci";
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pinctrl-0 = <&cci0_0_default &cci0_1_default>;
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pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>;
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pinctrl-names = "default", "sleep";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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cci0_i2c0: i2c-bus@0 {
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reg = <0>;
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clock-frequency = <1000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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cci0_i2c1: i2c-bus@1 {
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reg = <1>;
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clock-frequency = <1000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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cci1: cci@ac14000 {
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compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci";
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reg = <0x0 0x0ac14000 0x0 0x1000>;
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interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
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power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
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clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
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<&camcc CAM_CC_CPAS_AHB_CLK>,
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<&camcc CAM_CC_CCI_1_CLK>;
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clock-names = "camnoc_axi",
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"cpas_ahb",
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"cci";
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pinctrl-0 = <&cci1_0_default &cci1_1_default>;
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pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>;
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pinctrl-names = "default", "sleep";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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cci1_i2c0: i2c-bus@0 {
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reg = <0>;
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clock-frequency = <1000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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cci1_i2c1: i2c-bus@1 {
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reg = <1>;
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clock-frequency = <1000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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cci2: cci@ac15000 {
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compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci";
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reg = <0x0 0x0ac15000 0x0 0x1000>;
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interrupts = <GIC_SPI 651 IRQ_TYPE_EDGE_RISING>;
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power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
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clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
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<&camcc CAM_CC_CPAS_AHB_CLK>,
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<&camcc CAM_CC_CCI_2_CLK>;
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clock-names = "camnoc_axi",
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"cpas_ahb",
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"cci";
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pinctrl-0 = <&cci2_0_default &cci2_1_default>;
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pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>;
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pinctrl-names = "default", "sleep";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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cci2_i2c0: i2c-bus@0 {
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reg = <0>;
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clock-frequency = <1000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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cci2_i2c1: i2c-bus@1 {
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reg = <1>;
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clock-frequency = <1000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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cci3: cci@ac16000 {
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compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci";
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reg = <0x0 0x0ac16000 0x0 0x1000>;
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interrupts = <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>;
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power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
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clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
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<&camcc CAM_CC_CPAS_AHB_CLK>,
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<&camcc CAM_CC_CCI_3_CLK>;
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clock-names = "camnoc_axi",
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"cpas_ahb",
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"cci";
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pinctrl-0 = <&cci3_0_default &cci3_1_default>;
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pinctrl-1 = <&cci3_0_sleep &cci3_1_sleep>;
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pinctrl-names = "default", "sleep";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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cci3_i2c0: i2c-bus@0 {
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reg = <0>;
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clock-frequency = <1000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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cci3_i2c1: i2c-bus@1 {
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reg = <1>;
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clock-frequency = <1000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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camss: isp@ac78000 {
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compatible = "qcom,sa8775p-camss";
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@@ -5268,6 +5424,118 @@
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bias-disable;
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};
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cci0_0_default: cci0-0-default-state {
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pins = "gpio60", "gpio61";
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function = "cci_i2c";
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drive-strength = <2>;
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bias-pull-up = <2200>;
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};
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cci0_0_sleep: cci0-0-sleep-state {
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pins = "gpio60", "gpio61";
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function = "cci_i2c";
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drive-strength = <2>;
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bias-pull-down;
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};
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cci0_1_default: cci0-1-default-state {
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pins = "gpio52", "gpio53";
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function = "cci_i2c";
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drive-strength = <2>;
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bias-pull-up = <2200>;
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};
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cci0_1_sleep: cci0-1-sleep-state {
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pins = "gpio52", "gpio53";
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function = "cci_i2c";
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drive-strength = <2>;
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bias-pull-down;
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};
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cci1_0_default: cci1-0-default-state {
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pins = "gpio62", "gpio63";
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function = "cci_i2c";
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drive-strength = <2>;
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bias-pull-up = <2200>;
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};
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cci1_0_sleep: cci1-0-sleep-state {
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pins = "gpio62", "gpio63";
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function = "cci_i2c";
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drive-strength = <2>;
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bias-pull-down;
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};
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cci1_1_default: cci1-1-default-state {
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pins = "gpio54", "gpio55";
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function = "cci_i2c";
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drive-strength = <2>;
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bias-pull-up = <2200>;
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};
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cci1_1_sleep: cci1-1-sleep-state {
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pins = "gpio54", "gpio55";
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function = "cci_i2c";
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drive-strength = <2>;
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bias-pull-down;
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};
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cci2_0_default: cci2-0-default-state {
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pins = "gpio64", "gpio65";
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function = "cci_i2c";
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drive-strength = <2>;
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bias-pull-up = <2200>;
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};
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cci2_0_sleep: cci2-0-sleep-state {
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pins = "gpio64", "gpio65";
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function = "cci_i2c";
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drive-strength = <2>;
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bias-pull-down;
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};
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cci2_1_default: cci2-1-default-state {
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pins = "gpio56", "gpio57";
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function = "cci_i2c";
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drive-strength = <2>;
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bias-pull-up = <2200>;
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};
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cci2_1_sleep: cci2-1-sleep-state {
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pins = "gpio56", "gpio57";
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function = "cci_i2c";
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drive-strength = <2>;
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bias-pull-down;
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};
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cci3_0_default: cci3-0-default-state {
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pins = "gpio66", "gpio67";
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function = "cci_i2c";
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drive-strength = <2>;
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bias-pull-up = <2200>;
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};
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cci3_0_sleep: cci3-0-sleep-state {
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pins = "gpio66", "gpio67";
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function = "cci_i2c";
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drive-strength = <2>;
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bias-pull-down;
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};
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cci3_1_default: cci3-1-default-state {
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pins = "gpio58", "gpio59";
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function = "cci_i2c";
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drive-strength = <2>;
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bias-pull-up = <2200>;
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};
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cci3_1_sleep: cci3-1-sleep-state {
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pins = "gpio58", "gpio59";
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function = "cci_i2c";
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drive-strength = <2>;
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bias-pull-down;
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};
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qup_i2c0_default: qup-i2c0-state {
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pins = "gpio20", "gpio21";
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function = "qup0_se0";
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