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Merge tag 'arm-soc/for-6.17/devicetree-arm64' of https://github.com/Broadcom/stblinux into soc/dt

Browse Source 
This pull request contains Broadcom ARM64-based SoCs Device Tree updates
for 6.17, please pull the following:

- Linus updates the 64-bit BCMBCA SoCs Device Tree with the common
  peripherals that exit as well as correct IRQ assignments

- Andrea adds support for the RP1 companion chip on the Raspberry Pi 5
  systems with clocks, gpios, pinctrl, all of that using an overlay to
  describe those peripherals

- Rob drops the interrupt-parent property from the GICv2M node on
  Northstar2 SoCs

* tag 'arm-soc/for-6.17/devicetree-arm64' of https://github.com/Broadcom/stblinux:
  arm64: dts: broadcom: northstar2: Drop GIC V2M "interrupt-parent"
  arm64: dts: broadcom: Add overlay for RP1 device
  arm64: dts: broadcom: Add board DTS for Rpi5 which includes RP1 node
  arm64: dts: bcm2712: Add external clock for RP1 chipset on Rpi5
  arm64: dts: rp1: Add support for RaspberryPi's RP1 device
  dt-bindings: misc: Add device specific bindings for RaspberryPi RP1
  dt-bindings: pinctrl: Add RaspberryPi RP1 gpio/pinctrl/pinmux bindings
  dt-bindings: clock: Add RaspberryPi RP1 clock bindings
  ARM64: dts: bcm63158: Add BCMBCA peripherals
  ARM64: dts: bcm6858: Add BCMBCA peripherals
  ARM64: dts: bcm6856: Add BCMBCA peripherals
  ARM64: dts: bcm4908: Add BCMBCA peripherals

Link: https://lore.kernel.org/r/20250630190216.1518354-3-florian.fainelli@broadcom.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2025-07-03 17:12:48 +02:00
parent df5e674c7a 657e413c27
commit 2ee49a6143
15 changed files with 1148 additions and 117 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Documentation/devicetree/bindings/clock/raspberrypi,rp1-clocks.yaml
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@@ -0,0 +1,58 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/raspberrypi,rp1-clocks.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: RaspberryPi RP1 clock generator
maintainers:
- A. della Porta <andrea.porta@suse.com>
description: |
The RP1 contains a clock generator designed as three PLLs (CORE, AUDIO,
VIDEO), and each PLL output can be programmed through dividers to generate
the clocks to drive the sub-peripherals embedded inside the chipset.
Link to datasheet:
https://datasheets.raspberrypi.com/rp1/rp1-peripherals.pdf
properties:
compatible:
const: raspberrypi,rp1-clocks
reg:
maxItems: 1
'#clock-cells':
const: 1
description:
The available clocks are defined in
include/dt-bindings/clock/raspberrypi,rp1-clocks.h.
clocks:
maxItems: 1
required:
- compatible
- reg
- '#clock-cells'
- clocks
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/raspberrypi,rp1-clocks.h>
rp1 {
#address-cells = <2>;
#size-cells = <2>;
clocks@c040018000 {
compatible = "raspberrypi,rp1-clocks";
reg = <0xc0 0x40018000 0x0 0x10038>;
#clock-cells = <1>;
clocks = <&clk_rp1_xosc>;
};
};
Documentation/devicetree/bindings/misc/pci1de4,1.yaml
+137
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@@ -0,0 +1,137 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/misc/pci1de4,1.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: RaspberryPi RP1 MFD PCI device
maintainers:
- A. della Porta <andrea.porta@suse.com>
description:
The RaspberryPi RP1 is a PCI multi function device containing
peripherals ranging from Ethernet to USB controller, I2C, SPI
and others.
The peripherals are accessed by addressing the PCI BAR1 region.
allOf:
- $ref: /schemas/pci/pci-ep-bus.yaml
properties:
compatible:
additionalItems: true
maxItems: 3
items:
- const: pci1de4,1
'#interrupt-cells':
const: 2
description: |
Specifies respectively the interrupt number and flags as defined
in include/dt-bindings/interrupt-controller/irq.h.
Since all interrupts are active high, only IRQ_TYPE_LEVEL_HIGH
and IRQ_TYPE_EDGE_RISING can be specified as type flags.
The supported values for the interrupt number are:
- IO BANK0: 0
- IO BANK1: 1
- IO BANK2: 2
- AUDIO IN: 3
- AUDIO OUT: 4
- PWM0: 5
- ETH: 6
- I2C0: 7
- I2C1: 8
- I2C2: 9
- I2C3: 10
- I2C4: 11
- I2C5: 12
- I2C6: 13
- I2S0: 14
- I2S1: 15
- I2S2: 16
- SDIO0: 17
- SDIO1: 18
- SPI0: 19
- SPI1: 20
- SPI2: 21
- SPI3: 22
- SPI4: 23
- SPI5: 24
- UART0: 25
- TIMER0: 26
- TIMER1: 27
- TIMER2: 28
- TIMER3: 29
- USB HOST0: 30
- USB HOST0-0: 31
- USB HOST0-1: 32
- USB HOST0-2: 33
- USB HOST0-3: 34
- USB HOST1: 35
- USB HOST1-0: 36
- USB HOST1-1: 37
- USB HOST1-2: 38
- USB HOST1-3: 39
- DMA: 40
- PWM1: 41
- UART1: 42
- UART2: 43
- UART3: 44
- UART4: 45
- UART5: 46
- MIPI0: 47
- MIPI1: 48
- VIDEO OUT: 49
- PIO0: 50
- PIO1: 51
- ADC FIFO: 52
- PCIE OUT: 53
- SPI6: 54
- SPI7: 55
- SPI8: 56
- PROC MISC: 57
- SYSCFG: 58
- CLOCKS DEFAULT: 59
- VBUSCTRL: 60
interrupt-controller: true
unevaluatedProperties: false
required:
- compatible
- '#interrupt-cells'
- interrupt-controller
- pci-ep-bus@1
examples:
- |
pci {
#address-cells = <3>;
#size-cells = <2>;
rp1@0,0 {
compatible = "pci1de4,1";
ranges = <0x01 0x00 0x00000000 0x82010000 0x00 0x00 0x00 0x400000>;
#address-cells = <3>;
#size-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
pci_ep_bus: pci-ep-bus@1 {
compatible = "simple-bus";
ranges = <0x00 0x40000000 0x01 0x00 0x00000000 0x00 0x00400000>;
dma-ranges = <0x10 0x00000000 0x43000000 0x10 0x00000000 0x10 0x00000000>;
#address-cells = <2>;
#size-cells = <2>;
rp1_clocks: clocks@40018000 {
compatible = "raspberrypi,rp1-clocks";
reg = <0x00 0x40018000 0x0 0x10038>;
#clock-cells = <1>;
clocks = <&clk_rp1_xosc>;
};
};
};
};
Documentation/devicetree/bindings/pinctrl/raspberrypi,rp1-gpio.yaml
+198
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@@ -0,0 +1,198 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/raspberrypi,rp1-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: RaspberryPi RP1 GPIO/Pinconf/Pinmux Controller submodule
maintainers:
- A. della Porta <andrea.porta@suse.com>
description:
The RP1 chipset is a Multi Function Device containing, among other
sub-peripherals, a gpio/pinconf/mux controller whose 54 pins are grouped
into 3 banks.
It works also as an interrupt controller for those gpios.
properties:
compatible:
const: raspberrypi,rp1-gpio
reg:
maxItems: 3
description: One reg specifier for each one of the 3 pin banks.
'#gpio-cells':
description: The first cell is the pin number and the second cell is used
to specify the flags (see include/dt-bindings/gpio/gpio.h).
const: 2
gpio-controller: true
gpio-ranges:
maxItems: 1
gpio-line-names:
maxItems: 54
interrupts:
maxItems: 3
description: One interrupt specifier for each one of the 3 pin banks.
'#interrupt-cells':
description:
Specifies the Bank number [0, 1, 2] and Flags as defined in
include/dt-bindings/interrupt-controller/irq.h.
const: 2
interrupt-controller: true
patternProperties:
'-state$':
oneOf:
- $ref: '#/$defs/raspberrypi-rp1-state'
- patternProperties:
'-pins$':
$ref: '#/$defs/raspberrypi-rp1-state'
additionalProperties: false
$defs:
raspberrypi-rp1-state:
allOf:
- $ref: pincfg-node.yaml#
- $ref: pinmux-node.yaml#
description:
Pin controller client devices use pin configuration subnodes (children
and grandchildren) for desired pin configuration.
Client device subnodes use below standard properties.
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
pattern: '^gpio([0-9]|[1-4][0-9]|5[0-3])$'
function:
enum: [ alt0, alt1, alt2, alt3, alt4, gpio, alt6, alt7, alt8, none,
aaud, dcd0, dpi, dsi0_te_ext, dsi1_te_ext, dsr0, dtr0, gpclk0,
gpclk1, gpclk2, gpclk3, gpclk4, gpclk5, i2c0, i2c1, i2c2, i2c3,
i2c4, i2c5, i2c6, i2s0, i2s1, i2s2, ir, mic, pcie_clkreq_n,
pio, proc_rio, pwm0, pwm1, ri0, sd0, sd1, spi0, spi1, spi2,
spi3, spi4, spi5, spi6, spi7, spi8, uart0, uart1, uart2, uart3,
uart4, uart5, vbus0, vbus1, vbus2, vbus3 ]
description:
Specify the alternative function to be configured for the specified
pins.
bias-disable: true
bias-pull-down: true
bias-pull-up: true
input-enable: true
input-schmitt-enable: true
output-enable: true
output-high: true
output-low: true
slew-rate:
description: 0 is slow slew rate, 1 is fast slew rate
enum: [ 0, 1 ]
drive-strength:
enum: [ 2, 4, 8, 12 ]
additionalProperties: false
allOf:
- $ref: pinctrl.yaml#
required:
- reg
- compatible
- '#gpio-cells'
- gpio-controller
- interrupts
- '#interrupt-cells'
- interrupt-controller
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
rp1 {
#address-cells = <2>;
#size-cells = <2>;
rp1_gpio: pinctrl@c0400d0000 {
reg = <0xc0 0x400d0000 0x0 0xc000>,
<0xc0 0x400e0000 0x0 0xc000>,
<0xc0 0x400f0000 0x0 0xc000>;
compatible = "raspberrypi,rp1-gpio";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
<1 IRQ_TYPE_LEVEL_HIGH>,
<2 IRQ_TYPE_LEVEL_HIGH>;
gpio-line-names =
"ID_SDA", // GPIO0
"ID_SCL", // GPIO1
"GPIO2", "GPIO3", "GPIO4", "GPIO5", "GPIO6",
"GPIO7", "GPIO8", "GPIO9", "GPIO10", "GPIO11",
"GPIO12", "GPIO13", "GPIO14", "GPIO15", "GPIO16",
"GPIO17", "GPIO18", "GPIO19", "GPIO20", "GPIO21",
"GPIO22", "GPIO23", "GPIO24", "GPIO25", "GPIO26",
"GPIO27",
"PCIE_RP1_WAKE", // GPIO28
"FAN_TACH", // GPIO29
"HOST_SDA", // GPIO30
"HOST_SCL", // GPIO31
"ETH_RST_N", // GPIO32
"", // GPIO33
"CD0_IO0_MICCLK", // GPIO34
"CD0_IO0_MICDAT0", // GPIO35
"RP1_PCIE_CLKREQ_N", // GPIO36
"", // GPIO37
"CD0_SDA", // GPIO38
"CD0_SCL", // GPIO39
"CD1_SDA", // GPIO40
"CD1_SCL", // GPIO41
"USB_VBUS_EN", // GPIO42
"USB_OC_N", // GPIO43
"RP1_STAT_LED", // GPIO44
"FAN_PWM", // GPIO45
"CD1_IO0_MICCLK", // GPIO46
"2712_WAKE", // GPIO47
"CD1_IO1_MICDAT1", // GPIO48
"EN_MAX_USB_CUR", // GPIO49
"", // GPIO50
"", // GPIO51
"", // GPIO52
""; // GPIO53
rp1-i2s0-default-state {
function = "i2s0";
pins = "gpio18", "gpio19", "gpio20", "gpio21";
bias-disable;
};
rp1-uart0-default-state {
txd-pins {
function = "uart0";
pins = "gpio14";
bias-disable;
};
rxd-pins {
function = "uart0";
pins = "gpio15";
bias-pull-up;
};
};
};
};
arch/arm64/boot/dts/broadcom/Makefile
+3 -1
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@@ -7,13 +7,15 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-400.dtb \
bcm2711-rpi-4-b.dtb \
bcm2711-rpi-cm4-io.dtb \
bcm2712-rpi-5-b.dtb \
bcm2712-rpi-5-b-ovl-rp1.dtb \
bcm2712-d-rpi-5-b.dtb \
bcm2837-rpi-2-b.dtb \
bcm2837-rpi-3-a-plus.dtb \
bcm2837-rpi-3-b.dtb \
bcm2837-rpi-3-b-plus.dtb \
bcm2837-rpi-cm3-io3.dtb \
bcm2837-rpi-zero-2-w.dtb
bcm2837-rpi-zero-2-w.dtb \
rp1.dtbo
subdir-y += bcmbca
subdir-y += northstar2
arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-ovl-rp1.dts
+121
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@@ -0,0 +1,121 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "bcm2712.dtsi"
/ {
compatible = "raspberrypi,5-model-b", "brcm,bcm2712";
model = "Raspberry Pi 5";
aliases {
serial10 = &uart10;
};
chosen: chosen {
stdout-path = "serial10:115200n8";
};
clk_rp1_xosc: clock-50000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-output-names = "rp1-xosc";
clock-frequency = <50000000>;
};
/* Will be filled by the bootloader */
memory@0 {
device_type = "memory";
reg = <0 0 0 0x28000000>;
};
sd_io_1v8_reg: sd-io-1v8-reg {
compatible = "regulator-gpio";
regulator-name = "vdd-sd-io";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
regulator-settling-time-us = <5000>;
gpios = <&gio_aon 3 GPIO_ACTIVE_HIGH>;
states = <1800000 1>,
<3300000 0>;
};
sd_vcc_reg: sd-vcc-reg {
compatible = "regulator-fixed";
regulator-name = "vcc-sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
enable-active-high;
gpios = <&gio_aon 4 GPIO_ACTIVE_HIGH>;
};
};
/* The Debug UART, on Rpi5 it's on JST-SH 1.0mm 3-pin connector
* labeled "UART", i.e. the interface with the system console.
*/
&uart10 {
status = "okay";
};
/* SDIO1 is used to drive the SD card */
&sdio1 {
vqmmc-supply = <&sd_io_1v8_reg>;
vmmc-supply = <&sd_vcc_reg>;
bus-width = <4>;
sd-uhs-sdr50;
sd-uhs-ddr50;
sd-uhs-sdr104;
};
&soc {
firmware: firmware {
compatible = "raspberrypi,bcm2835-firmware", "simple-mfd";
#address-cells = <1>;
#size-cells = <1>;
mboxes = <&mailbox>;
dma-ranges;
firmware_clocks: clocks {
compatible = "raspberrypi,firmware-clocks";
#clock-cells = <1>;
};
reset: reset {
compatible = "raspberrypi,firmware-reset";
#reset-cells = <1>;
};
};
power: power {
compatible = "raspberrypi,bcm2835-power";
firmware = <&firmware>;
#power-domain-cells = <1>;
};
};
&hvs {
clocks = <&firmware_clocks 4>, <&firmware_clocks 16>;
clock-names = "core", "disp";
};
&hdmi0 {
clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 0>, <&clk_27MHz>;
clock-names = "hdmi", "bvb", "audio", "cec";
};
&hdmi1 {
clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>;
clock-names = "hdmi", "bvb", "audio", "cec";
};
&pcie1 {
status = "okay";
};
&pcie2 {
status = "okay";
};
arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
+12 -101
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@@ -1,108 +1,19 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* bcm2712-rpi-5-b-ovl-rp1.dts is the overlay-ready DT which will make
* the RP1 driver to load the RP1 dtb overlay at runtime, while
* bcm2712-rpi-5-b.dts (this file) is the fully defined one (i.e. it
* already contains RP1 node, so no overlay is loaded nor needed).
* This file is not intended to be modified, nodes should be added
* to the included bcm2712-rpi-5-b-ovl-rp1.dts.
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "bcm2712.dtsi"
#include "bcm2712-rpi-5-b-ovl-rp1.dts"
/ {
compatible = "raspberrypi,5-model-b", "brcm,bcm2712";
model = "Raspberry Pi 5";
aliases {
serial10 = &uart10;
};
chosen: chosen {
stdout-path = "serial10:115200n8";
};
/* Will be filled by the bootloader */
memory@0 {
device_type = "memory";
reg = <0 0 0 0x28000000>;
};
sd_io_1v8_reg: sd-io-1v8-reg {
compatible = "regulator-gpio";
regulator-name = "vdd-sd-io";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
regulator-settling-time-us = <5000>;
gpios = <&gio_aon 3 GPIO_ACTIVE_HIGH>;
states = <1800000 1>,
<3300000 0>;
};
sd_vcc_reg: sd-vcc-reg {
compatible = "regulator-fixed";
regulator-name = "vcc-sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
enable-active-high;
gpios = <&gio_aon 4 GPIO_ACTIVE_HIGH>;
};
};
/* The Debug UART, on Rpi5 it's on JST-SH 1.0mm 3-pin connector
* labeled "UART", i.e. the interface with the system console.
*/
&uart10 {
status = "okay";
};
/* SDIO1 is used to drive the SD card */
&sdio1 {
vqmmc-supply = <&sd_io_1v8_reg>;
vmmc-supply = <&sd_vcc_reg>;
bus-width = <4>;
sd-uhs-sdr50;
sd-uhs-ddr50;
sd-uhs-sdr104;
};
&soc {
firmware: firmware {
compatible = "raspberrypi,bcm2835-firmware", "simple-mfd";
#address-cells = <1>;
#size-cells = <1>;
mboxes = <&mailbox>;
dma-ranges;
firmware_clocks: clocks {
compatible = "raspberrypi,firmware-clocks";
#clock-cells = <1>;
};
reset: reset {
compatible = "raspberrypi,firmware-reset";
#reset-cells = <1>;
};
};
power: power {
compatible = "raspberrypi,bcm2835-power";
firmware = <&firmware>;
#power-domain-cells = <1>;
};
};
&hvs {
clocks = <&firmware_clocks 4>, <&firmware_clocks 16>;
clock-names = "core", "disp";
};
&hdmi0 {
clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 0>, <&clk_27MHz>;
clock-names = "hdmi", "bvb", "audio", "cec";
};
&hdmi1 {
clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>;
clock-names = "hdmi", "bvb", "audio", "cec";
&pcie2 {
#include "rp1-nexus.dtsi"
};
&pcie1 {
arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
+115 -5
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@@ -323,11 +323,12 @@
};
};
/* PERF Peripherals */
bus@ff800000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00 0x00 0xff800000 0x3000>;
ranges = <0x00 0x00 0xff800000 0x400000>;
twd: timer-mfd@400 {
compatible = "brcm,bcm4908-twd", "simple-mfd", "syscon";
@@ -348,13 +349,103 @@
};
};
gpio0: gpio-controller@500 {
/* GPIOs 0 .. 31 */
gpio0: gpio@500 {
compatible = "brcm,bcm6345-gpio";
reg = <0x500 0x04>, <0x528 0x04>;
reg-names = "dirout", "dat";
reg = <0x500 0x28>, <0x528 0x28>;
#gpio-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
};
/* GPIOs 32 .. 63 */
gpio1: gpio@504 {
compatible = "brcm,bcm6345-gpio";
reg = <0x504 0x04>, <0x52c 0x04>;
reg-names = "dirout", "dat";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
/* GPIOs 64 .. 95 */
gpio2: gpio@508 {
compatible = "brcm,bcm6345-gpio";
reg = <0x508 0x04>, <0x530 0x04>;
reg-names = "dirout", "dat";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
/* GPIOs 96 .. 127 */
gpio3: gpio@50c {
compatible = "brcm,bcm6345-gpio";
reg = <0x50c 0x04>, <0x534 0x04>;
reg-names = "dirout", "dat";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
/* GPIOs 128 .. 159 */
gpio4: gpio@510 {
compatible = "brcm,bcm6345-gpio";
reg = <0x510 0x04>, <0x538 0x04>;
reg-names = "dirout", "dat";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
/* GPIOs 160 .. 191 */
gpio5: gpio@514 {
compatible = "brcm,bcm6345-gpio";
reg = <0x514 0x04>, <0x53c 0x04>;
reg-names = "dirout", "dat";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
/* GPIOs 192 .. 223 */
gpio6: gpio@518 {
compatible = "brcm,bcm6345-gpio";
reg = <0x518 0x04>, <0x540 0x04>;
reg-names = "dirout", "dat";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
/* GPIOs 224 .. 255 */
gpio7: gpio@51c {
compatible = "brcm,bcm6345-gpio";
reg = <0x51c 0x04>, <0x544 0x04>;
reg-names = "dirout", "dat";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
/* GPIOs 256 .. 287 */
gpio8: gpio@520 {
compatible = "brcm,bcm6345-gpio";
reg = <0x520 0x04>, <0x548 0x04>;
reg-names = "dirout", "dat";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
/* GPIOs 288 .. 319 */
gpio9: gpio@524 {
compatible = "brcm,bcm6345-gpio";
reg = <0x524 0x04>, <0x54c 0x04>;
reg-names = "dirout", "dat";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
pinctrl@560 {
@@ -584,6 +675,12 @@
#size-cells = <0>;
};
rng@b80 {
compatible = "brcm,iproc-rng200";
reg = <0xb80 0x28>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
};
hsspi: spi@1000 {
#address-cells = <1>;
#size-cells = <0>;
@@ -636,6 +733,19 @@
#reset-cells = <1>;
};
};
pl081_dma: dma-controller@59000 {
compatible = "arm,pl081", "arm,primecell";
// The magic B105F00D info is missing
arm,primecell-periphid = <0x00041081>;
reg = <0x59000 0x1000>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
memcpy-burst-size = <256>;
memcpy-bus-width = <32>;
clocks = <&periph_clk>;
clock-names = "apb_pclk";
#dma-cells = <2>;
};
};
reboot {
arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
+129
View File
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Broadcom Ltd.
* This DTSI is for the B0 and later revision of the SoC
*/
#include <dt-bindings/interrupt-controller/irq.h>
@@ -125,6 +126,101 @@
#size-cells = <1>;
ranges = <0x0 0x0 0xff800000 0x800000>;
/* GPIOs 0 .. 31 */
gpio0: gpio@500 {
compatible = "brcm,bcm6345-gpio";
reg = <0x500 0x04>, <0x520 0x04>;
reg-names = "dirout", "dat";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
/* GPIOs 32 .. 63 */
gpio1: gpio@504 {
compatible = "brcm,bcm6345-gpio";
reg = <0x504 0x04>, <0x524 0x04>;
reg-names = "dirout", "dat";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
/* GPIOs 64 .. 95 */
gpio2: gpio@508 {
compatible = "brcm,bcm6345-gpio";
reg = <0x508 0x04>, <0x528 0x04>;
reg-names = "dirout", "dat";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
/* GPIOs 96 .. 127 */
gpio3: gpio@50c {
compatible = "brcm,bcm6345-gpio";
reg = <0x50c 0x04>, <0x52c 0x04>;
reg-names = "dirout", "dat";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
/* GPIOs 128 .. 159 */
gpio4: gpio@510 {
compatible = "brcm,bcm6345-gpio";
reg = <0x510 0x04>, <0x530 0x04>;
reg-names = "dirout", "dat";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
/* GPIOs 160 .. 191 */
gpio5: gpio@514 {
compatible = "brcm,bcm6345-gpio";
reg = <0x514 0x04>, <0x534 0x04>;
reg-names = "dirout", "dat";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
/* GPIOs 192 .. 223 */
gpio6: gpio@518 {
compatible = "brcm,bcm6345-gpio";
reg = <0x518 0x04>, <0x538 0x04>;
reg-names = "dirout", "dat";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
/* GPIOs 224 .. 255 */
gpio7: gpio@51c {
compatible = "brcm,bcm6345-gpio";
reg = <0x51c 0x04>, <0x53c 0x04>;
reg-names = "dirout", "dat";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
leds: led-controller@800 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "brcm,bcm63138-leds";
reg = <0x800 0xdc>;
status = "disabled";
};
rng@b80 {
compatible = "brcm,iproc-rng200";
reg = <0xb80 0x28>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
};
hsspi: spi@1000 {
#address-cells = <1>;
#size-cells = <0>;
@@ -151,6 +247,21 @@
};
};
/* B0 AHB Peripherals */
pl081_dma: dma-controller@11000 {
compatible = "arm,pl081", "arm,primecell";
// The magic B105F00D info is missing
arm,primecell-periphid = <0x00041081>;
reg = <0x11000 0x1000>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
memcpy-burst-size = <256>;
memcpy-bus-width = <32>;
clocks = <&periph_clk>;
clock-names = "apb_pclk";
#dma-cells = <2>;
};
/* B0 ARM UART Peripheral block */
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
@@ -159,5 +270,23 @@
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
uart1: serial@13000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x13000 0x1000>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart_clk>, <&uart_clk>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
uart2: serial@14000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x14000 0x1000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart_clk>, <&uart_clk>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
};
};
arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
+129 -1
View File
@@ -93,11 +93,103 @@
};
};
/* PERF Peripherals */
bus@ff800000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0xff800000 0x800000>;
ranges = <0x0 0x0 0xff800000 0x400000>;
watchdog@480 {
compatible = "brcm,bcm6345-wdt";
reg = <0x480 0x10>;
};
watchdog@4c0 {
compatible = "brcm,bcm6345-wdt";
reg = <0x4c0 0x10>;
status = "disabled";
};
/* GPIOs 0 .. 31 */
gpio0: gpio@500 {
compatible = "brcm,bcm6345-gpio";
reg = <0x500 0x04>, <0x520 0x04>;
reg-names = "dirout", "dat";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
/* GPIOs 32 .. 63 */
gpio1: gpio@504 {
compatible = "brcm,bcm6345-gpio";
reg = <0x504 0x04>, <0x524 0x04>;
reg-names = "dirout", "dat";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
/* GPIOs 64 .. 95 */
gpio2: gpio@508 {
compatible = "brcm,bcm6345-gpio";
reg = <0x508 0x04>, <0x528 0x04>;
reg-names = "dirout", "dat";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
/* GPIOs 96 .. 127 */
gpio3: gpio@50c {
compatible = "brcm,bcm6345-gpio";
reg = <0x50c 0x04>, <0x52c 0x04>;
reg-names = "dirout", "dat";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
/* GPIOs 128 .. 159 */
gpio4: gpio@510 {
compatible = "brcm,bcm6345-gpio";
reg = <0x510 0x04>, <0x530 0x04>;
reg-names = "dirout", "dat";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
/* GPIOs 160 .. 191 */
gpio5: gpio@514 {
compatible = "brcm,bcm6345-gpio";
reg = <0x514 0x04>, <0x534 0x04>;
reg-names = "dirout", "dat";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
/* GPIOs 192 .. 223 */
gpio6: gpio@518 {
compatible = "brcm,bcm6345-gpio";
reg = <0x518 0x04>, <0x538 0x04>;
reg-names = "dirout", "dat";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
/* GPIOs 224 .. 255 */
gpio7: gpio@51c {
compatible = "brcm,bcm6345-gpio";
reg = <0x51c 0x04>, <0x53c 0x04>;
reg-names = "dirout", "dat";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
uart0: serial@640 {
compatible = "brcm,bcm6345-uart";
@@ -108,6 +200,29 @@
status = "disabled";
};
uart1: serial@660 {
compatible = "brcm,bcm6345-uart";
reg = <0x660 0x18>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&periph_clk>;
clock-names = "refclk";
status = "disabled";
};
leds: led-controller@800 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "brcm,bcm63138-leds";
reg = <0x800 0xdc>;
status = "disabled";
};
rng@b80 {
compatible = "brcm,iproc-rng200";
reg = <0xb80 0x28>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
};
hsspi: spi@1000 {
#address-cells = <1>;
#size-cells = <0>;
@@ -133,5 +248,18 @@
reg = <0>;
};
};
pl081_dma: dma-controller@59000 {
compatible = "arm,pl081", "arm,primecell";
// The magic B105F00D info is missing
arm,primecell-periphid = <0x00041081>;
reg = <0x59000 0x1000>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
memcpy-burst-size = <256>;
memcpy-bus-width = <32>;
clocks = <&periph_clk>;
clock-names = "apb_pclk";
#dma-cells = <2>;
};
};
};
arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
+118 -1
View File
@@ -111,11 +111,12 @@
};
};
/* PERF Peripherals */
bus@ff800000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0xff800000 0x62000>;
ranges = <0x0 0x0 0xff800000 0x400000>;
twd: timer-mfd@400 {
compatible = "brcm,bcm4908-twd", "simple-mfd", "syscon";
@@ -136,6 +137,86 @@
};
};
/* GPIOs 0 .. 31 */
gpio0: gpio@500 {
compatible = "brcm,bcm6345-gpio";
reg = <0x500 0x04>, <0x520 0x04>;
reg-names = "dirout", "dat";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
/* GPIOs 32 .. 63 */
gpio1: gpio@504 {
compatible = "brcm,bcm6345-gpio";
reg = <0x504 0x04>, <0x524 0x04>;
reg-names = "dirout", "dat";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
/* GPIOs 64 .. 95 */
gpio2: gpio@508 {
compatible = "brcm,bcm6345-gpio";
reg = <0x508 0x04>, <0x528 0x04>;
reg-names = "dirout", "dat";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
/* GPIOs 96 .. 127 */
gpio3: gpio@50c {
compatible = "brcm,bcm6345-gpio";
reg = <0x50c 0x04>, <0x52c 0x04>;
reg-names = "dirout", "dat";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
/* GPIOs 128 .. 159 */
gpio4: gpio@510 {
compatible = "brcm,bcm6345-gpio";
reg = <0x510 0x04>, <0x530 0x04>;
reg-names = "dirout", "dat";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
/* GPIOs 160 .. 191 */
gpio5: gpio@514 {
compatible = "brcm,bcm6345-gpio";
reg = <0x514 0x04>, <0x534 0x04>;
reg-names = "dirout", "dat";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
/* GPIOs 192 .. 223 */
gpio6: gpio@518 {
compatible = "brcm,bcm6345-gpio";
reg = <0x518 0x04>, <0x538 0x04>;
reg-names = "dirout", "dat";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
/* GPIOs 224 .. 255 */
gpio7: gpio@51c {
compatible = "brcm,bcm6345-gpio";
reg = <0x51c 0x04>, <0x53c 0x04>;
reg-names = "dirout", "dat";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
uart0: serial@640 {
compatible = "brcm,bcm6345-uart";
reg = <0x640 0x18>;
@@ -145,6 +226,29 @@
status = "disabled";
};
uart1: serial@660 {
compatible = "brcm,bcm6345-uart";
reg = <0x660 0x18>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&periph_clk>;
clock-names = "refclk";
status = "disabled";
};
leds: led-controller@800 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "brcm,bcm63138-leds";
reg = <0x800 0xdc>;
status = "disabled";
};
rng@b80 {
compatible = "brcm,iproc-rng200";
reg = <0xb80 0x28>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
};
hsspi: spi@1000 {
#address-cells = <1>;
#size-cells = <0>;
@@ -170,5 +274,18 @@
reg = <0>;
};
};
pl081_dma: dma-controller@59000 {
compatible = "arm,pl081", "arm,primecell";
// The magic B105F00D info is missing
arm,primecell-periphid = <0x00041081>;
reg = <0x59000 0x1000>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
memcpy-burst-size = <256>;
memcpy-bus-width = <32>;
clocks = <&periph_clk>;
clock-names = "apb_pclk";
#dma-cells = <2>;
};
};
};
arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi
-8
View File
@@ -367,7 +367,6 @@
v2m0: v2m@0 {
compatible = "arm,gic-v2m-frame";
interrupt-parent = <&gic>;
msi-controller;
reg = <0x00000 0x1000>;
arm,msi-base-spi = <72>;
@@ -376,7 +375,6 @@
v2m1: v2m@10000 {
compatible = "arm,gic-v2m-frame";
interrupt-parent = <&gic>;
msi-controller;
reg = <0x10000 0x1000>;
arm,msi-base-spi = <88>;
@@ -385,7 +383,6 @@
v2m2: v2m@20000 {
compatible = "arm,gic-v2m-frame";
interrupt-parent = <&gic>;
msi-controller;
reg = <0x20000 0x1000>;
arm,msi-base-spi = <104>;
@@ -394,7 +391,6 @@
v2m3: v2m@30000 {
compatible = "arm,gic-v2m-frame";
interrupt-parent = <&gic>;
msi-controller;
reg = <0x30000 0x1000>;
arm,msi-base-spi = <120>;
@@ -403,7 +399,6 @@
v2m4: v2m@40000 {
compatible = "arm,gic-v2m-frame";
interrupt-parent = <&gic>;
msi-controller;
reg = <0x40000 0x1000>;
arm,msi-base-spi = <136>;
@@ -412,7 +407,6 @@
v2m5: v2m@50000 {
compatible = "arm,gic-v2m-frame";
interrupt-parent = <&gic>;
msi-controller;
reg = <0x50000 0x1000>;
arm,msi-base-spi = <152>;
@@ -421,7 +415,6 @@
v2m6: v2m@60000 {
compatible = "arm,gic-v2m-frame";
interrupt-parent = <&gic>;
msi-controller;
reg = <0x60000 0x1000>;
arm,msi-base-spi = <168>;
@@ -430,7 +423,6 @@
v2m7: v2m@70000 {
compatible = "arm,gic-v2m-frame";
interrupt-parent = <&gic>;
msi-controller;
reg = <0x70000 0x1000>;
arm,msi-base-spi = <184>;
arch/arm64/boot/dts/broadcom/rp1-common.dtsi
+42
View File
@@ -0,0 +1,42 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/raspberrypi,rp1-clocks.h>
pci_ep_bus: pci-ep-bus@1 {
compatible = "simple-bus";
ranges = <0x00 0x40000000 0x01 0x00 0x00000000 0x00 0x00400000>;
dma-ranges = <0x10 0x00000000 0x43000000 0x10 0x00000000 0x10 0x00000000>;
#address-cells = <2>;
#size-cells = <2>;
rp1_clocks: clocks@40018000 {
compatible = "raspberrypi,rp1-clocks";
reg = <0x00 0x40018000 0x0 0x10038>;
#clock-cells = <1>;
clocks = <&clk_rp1_xosc>;
assigned-clocks = <&rp1_clocks RP1_PLL_SYS_CORE>,
<&rp1_clocks RP1_PLL_SYS>,
<&rp1_clocks RP1_PLL_SYS_SEC>,
<&rp1_clocks RP1_CLK_SYS>;
assigned-clock-rates = <1000000000>, // RP1_PLL_SYS_CORE
<200000000>, // RP1_PLL_SYS
<125000000>, // RP1_PLL_SYS_SEC
<200000000>; // RP1_CLK_SYS
};
rp1_gpio: pinctrl@400d0000 {
compatible = "raspberrypi,rp1-gpio";
reg = <0x00 0x400d0000 0x0 0xc000>,
<0x00 0x400e0000 0x0 0xc000>,
<0x00 0x400f0000 0x0 0xc000>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
<1 IRQ_TYPE_LEVEL_HIGH>,
<2 IRQ_TYPE_LEVEL_HIGH>;
};
};
arch/arm64/boot/dts/broadcom/rp1-nexus.dtsi
+14
View File
@@ -0,0 +1,14 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
rp1_nexus {
compatible = "pci1de4,1";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01 0x00 0x00000000
0x02000000 0x00 0x00000000
0x0 0x400000>;
interrupt-controller;
#interrupt-cells = <2>;
#include "rp1-common.dtsi"
};
arch/arm64/boot/dts/broadcom/rp1.dtso
+11
View File
@@ -0,0 +1,11 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/dts-v1/;
/plugin/;
&pcie2 {
#address-cells = <3>;
#size-cells = <2>;
#include "rp1-nexus.dtsi"
};
include/dt-bindings/clock/raspberrypi,rp1-clocks.h
+61
View File
@@ -0,0 +1,61 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (C) 2021 Raspberry Pi Ltd.
*/
#ifndef __DT_BINDINGS_CLOCK_RASPBERRYPI_RP1
#define __DT_BINDINGS_CLOCK_RASPBERRYPI_RP1
#define RP1_PLL_SYS_CORE 0
#define RP1_PLL_AUDIO_CORE 1
#define RP1_PLL_VIDEO_CORE 2
#define RP1_PLL_SYS 3
#define RP1_PLL_AUDIO 4
#define RP1_PLL_VIDEO 5
#define RP1_PLL_SYS_PRI_PH 6
#define RP1_PLL_SYS_SEC_PH 7
#define RP1_PLL_AUDIO_PRI_PH 8
#define RP1_PLL_SYS_SEC 9
#define RP1_PLL_AUDIO_SEC 10
#define RP1_PLL_VIDEO_SEC 11
#define RP1_CLK_SYS 12
#define RP1_CLK_SLOW_SYS 13
#define RP1_CLK_DMA 14
#define RP1_CLK_UART 15
#define RP1_CLK_ETH 16
#define RP1_CLK_PWM0 17
#define RP1_CLK_PWM1 18
#define RP1_CLK_AUDIO_IN 19
#define RP1_CLK_AUDIO_OUT 20
#define RP1_CLK_I2S 21
#define RP1_CLK_MIPI0_CFG 22
#define RP1_CLK_MIPI1_CFG 23
#define RP1_CLK_PCIE_AUX 24
#define RP1_CLK_USBH0_MICROFRAME 25
#define RP1_CLK_USBH1_MICROFRAME 26
#define RP1_CLK_USBH0_SUSPEND 27
#define RP1_CLK_USBH1_SUSPEND 28
#define RP1_CLK_ETH_TSU 29
#define RP1_CLK_ADC 30
#define RP1_CLK_SDIO_TIMER 31
#define RP1_CLK_SDIO_ALT_SRC 32
#define RP1_CLK_GP0 33
#define RP1_CLK_GP1 34
#define RP1_CLK_GP2 35
#define RP1_CLK_GP3 36
#define RP1_CLK_GP4 37
#define RP1_CLK_GP5 38
#define RP1_CLK_VEC 39
#define RP1_CLK_DPI 40
#define RP1_CLK_MIPI0_DPI 41
#define RP1_CLK_MIPI1_DPI 42
/* Extra PLL output channels - RP1B0 only */
#define RP1_PLL_VIDEO_PRI_PH 43
#define RP1_PLL_AUDIO_TERN 44
#endif