clk: renesas: rzg2l: Drop MSTOP based power domain support
Since the configuration order between the individual MSTOP and CLKON bits cannot be preserved with the power domain abstraction, drop the power domain core code. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://lore.kernel.org/20250527112403.1254122-7-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Claudiu Beznea
committed by
Geert Uytterhoeven
Geert Uytterhoeven
parent
c496959527
commit
26a301a244
+17
-191
@@ -148,6 +148,7 @@ struct rzg2l_pll5_mux_dsi_div_param {
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* @num_resets: Number of Module Resets in info->resets[]
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* @last_dt_core_clk: ID of the last Core Clock exported to DT
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* @info: Pointer to platform data
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* @genpd: PM domain
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* @mux_dsi_div_params: pll5 mux and dsi div parameters
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*/
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struct rzg2l_cpg_priv {
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@@ -164,6 +165,8 @@ struct rzg2l_cpg_priv {
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const struct rzg2l_cpg_info *info;
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struct generic_pm_domain genpd;
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struct rzg2l_pll5_mux_dsi_div_param mux_dsi_div_params;
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};
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@@ -1763,39 +1766,14 @@ static int rzg2l_cpg_reset_controller_register(struct rzg2l_cpg_priv *priv)
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return devm_reset_controller_register(priv->dev, &priv->rcdev);
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}
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/**
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* struct rzg2l_cpg_pm_domains - RZ/G2L PM domains data structure
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* @onecell_data: cell data
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* @domains: generic PM domains
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*/
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struct rzg2l_cpg_pm_domains {
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struct genpd_onecell_data onecell_data;
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struct generic_pm_domain *domains[];
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};
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/**
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* struct rzg2l_cpg_pd - RZ/G2L power domain data structure
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* @genpd: generic PM domain
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* @priv: pointer to CPG private data structure
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* @conf: CPG PM domain configuration info
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* @id: RZ/G2L power domain ID
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*/
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struct rzg2l_cpg_pd {
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struct generic_pm_domain genpd;
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struct rzg2l_cpg_priv *priv;
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struct rzg2l_cpg_pm_domain_conf conf;
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u16 id;
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};
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static bool rzg2l_cpg_is_pm_clk(struct rzg2l_cpg_pd *pd,
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static bool rzg2l_cpg_is_pm_clk(struct rzg2l_cpg_priv *priv,
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const struct of_phandle_args *clkspec)
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{
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if (clkspec->np != pd->genpd.dev.of_node || clkspec->args_count != 2)
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if (clkspec->np != priv->genpd.dev.of_node || clkspec->args_count != 2)
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return false;
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switch (clkspec->args[0]) {
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case CPG_MOD: {
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struct rzg2l_cpg_priv *priv = pd->priv;
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const struct rzg2l_cpg_info *info = priv->info;
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unsigned int id = clkspec->args[1];
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@@ -1820,7 +1798,7 @@ static bool rzg2l_cpg_is_pm_clk(struct rzg2l_cpg_pd *pd,
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static int rzg2l_cpg_attach_dev(struct generic_pm_domain *domain, struct device *dev)
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{
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struct rzg2l_cpg_pd *pd = container_of(domain, struct rzg2l_cpg_pd, genpd);
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struct rzg2l_cpg_priv *priv = container_of(domain, struct rzg2l_cpg_priv, genpd);
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struct device_node *np = dev->of_node;
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struct of_phandle_args clkspec;
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bool once = true;
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@@ -1829,7 +1807,7 @@ static int rzg2l_cpg_attach_dev(struct generic_pm_domain *domain, struct device
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int error;
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for (i = 0; !of_parse_phandle_with_args(np, "clocks", "#clock-cells", i, &clkspec); i++) {
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if (!rzg2l_cpg_is_pm_clk(pd, &clkspec)) {
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if (!rzg2l_cpg_is_pm_clk(priv, &clkspec)) {
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of_node_put(clkspec.np);
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continue;
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}
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@@ -1874,183 +1852,31 @@ static void rzg2l_cpg_detach_dev(struct generic_pm_domain *unused, struct device
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}
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static void rzg2l_cpg_genpd_remove(void *data)
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{
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struct genpd_onecell_data *celldata = data;
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for (unsigned int i = 0; i < celldata->num_domains; i++)
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pm_genpd_remove(celldata->domains[i]);
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}
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static void rzg2l_cpg_genpd_remove_simple(void *data)
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{
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pm_genpd_remove(data);
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}
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static int rzg2l_cpg_power_on(struct generic_pm_domain *domain)
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{
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struct rzg2l_cpg_pd *pd = container_of(domain, struct rzg2l_cpg_pd, genpd);
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struct rzg2l_cpg_reg_conf mstop = pd->conf.mstop;
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struct rzg2l_cpg_priv *priv = pd->priv;
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/* Set MSTOP. */
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if (mstop.mask)
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writel(mstop.mask << 16, priv->base + mstop.off);
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return 0;
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}
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static int rzg2l_cpg_power_off(struct generic_pm_domain *domain)
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{
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struct rzg2l_cpg_pd *pd = container_of(domain, struct rzg2l_cpg_pd, genpd);
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struct rzg2l_cpg_reg_conf mstop = pd->conf.mstop;
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struct rzg2l_cpg_priv *priv = pd->priv;
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/* Set MSTOP. */
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if (mstop.mask)
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writel(mstop.mask | (mstop.mask << 16), priv->base + mstop.off);
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return 0;
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}
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static int __init rzg2l_cpg_pd_setup(struct rzg2l_cpg_pd *pd)
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{
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bool always_on = !!(pd->genpd.flags & GENPD_FLAG_ALWAYS_ON);
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struct dev_power_governor *governor;
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int ret;
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if (always_on)
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governor = &pm_domain_always_on_gov;
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else
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governor = &simple_qos_governor;
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pd->genpd.flags |= GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;
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pd->genpd.attach_dev = rzg2l_cpg_attach_dev;
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pd->genpd.detach_dev = rzg2l_cpg_detach_dev;
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pd->genpd.power_on = rzg2l_cpg_power_on;
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pd->genpd.power_off = rzg2l_cpg_power_off;
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ret = pm_genpd_init(&pd->genpd, governor, !always_on);
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if (ret)
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return ret;
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if (always_on)
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ret = rzg2l_cpg_power_on(&pd->genpd);
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return ret;
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}
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static int __init rzg2l_cpg_add_clk_domain(struct rzg2l_cpg_priv *priv)
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{
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struct device *dev = priv->dev;
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struct device_node *np = dev->of_node;
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struct rzg2l_cpg_pd *pd;
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struct generic_pm_domain *genpd = &priv->genpd;
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int ret;
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pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
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if (!pd)
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return -ENOMEM;
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pd->genpd.name = np->name;
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pd->genpd.flags = GENPD_FLAG_ALWAYS_ON;
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pd->priv = priv;
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ret = rzg2l_cpg_pd_setup(pd);
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genpd->name = np->name;
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genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |
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GENPD_FLAG_ACTIVE_WAKEUP;
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genpd->attach_dev = rzg2l_cpg_attach_dev;
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genpd->detach_dev = rzg2l_cpg_detach_dev;
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ret = pm_genpd_init(genpd, &pm_domain_always_on_gov, false);
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if (ret)
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return ret;
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ret = devm_add_action_or_reset(dev, rzg2l_cpg_genpd_remove_simple, &pd->genpd);
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ret = devm_add_action_or_reset(dev, rzg2l_cpg_genpd_remove, genpd);
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if (ret)
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return ret;
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return of_genpd_add_provider_simple(np, &pd->genpd);
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}
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static struct generic_pm_domain *
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rzg2l_cpg_pm_domain_xlate(const struct of_phandle_args *spec, void *data)
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{
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struct generic_pm_domain *domain = ERR_PTR(-ENOENT);
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struct genpd_onecell_data *genpd = data;
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if (spec->args_count != 1)
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return ERR_PTR(-EINVAL);
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for (unsigned int i = 0; i < genpd->num_domains; i++) {
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struct rzg2l_cpg_pd *pd = container_of(genpd->domains[i], struct rzg2l_cpg_pd,
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genpd);
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if (pd->id == spec->args[0]) {
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domain = &pd->genpd;
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break;
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}
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}
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return domain;
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}
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static int __init rzg2l_cpg_add_pm_domains(struct rzg2l_cpg_priv *priv)
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{
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const struct rzg2l_cpg_info *info = priv->info;
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struct device *dev = priv->dev;
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struct device_node *np = dev->of_node;
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struct rzg2l_cpg_pm_domains *domains;
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struct generic_pm_domain *parent;
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u32 ncells;
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int ret;
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ret = of_property_read_u32(np, "#power-domain-cells", &ncells);
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if (ret)
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return ret;
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/* For backward compatibility. */
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if (!ncells)
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return rzg2l_cpg_add_clk_domain(priv);
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domains = devm_kzalloc(dev, struct_size(domains, domains, info->num_pm_domains),
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GFP_KERNEL);
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if (!domains)
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return -ENOMEM;
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domains->onecell_data.domains = domains->domains;
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domains->onecell_data.num_domains = info->num_pm_domains;
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domains->onecell_data.xlate = rzg2l_cpg_pm_domain_xlate;
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ret = devm_add_action_or_reset(dev, rzg2l_cpg_genpd_remove, &domains->onecell_data);
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if (ret)
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return ret;
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for (unsigned int i = 0; i < info->num_pm_domains; i++) {
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struct rzg2l_cpg_pd *pd;
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pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
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if (!pd)
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return -ENOMEM;
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pd->genpd.name = info->pm_domains[i].name;
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pd->genpd.flags = info->pm_domains[i].genpd_flags;
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pd->conf = info->pm_domains[i].conf;
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pd->id = info->pm_domains[i].id;
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pd->priv = priv;
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ret = rzg2l_cpg_pd_setup(pd);
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if (ret)
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return ret;
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domains->domains[i] = &pd->genpd;
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/* Parent should be on the very first entry of info->pm_domains[]. */
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if (!i) {
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parent = &pd->genpd;
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continue;
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}
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ret = pm_genpd_add_subdomain(parent, &pd->genpd);
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if (ret)
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return ret;
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}
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ret = of_genpd_add_provider_onecell(np, &domains->onecell_data);
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if (ret)
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return ret;
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return 0;
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return of_genpd_add_provider_simple(np, genpd);
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}
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static int __init rzg2l_cpg_probe(struct platform_device *pdev)
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@@ -2113,7 +1939,7 @@ static int __init rzg2l_cpg_probe(struct platform_device *pdev)
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if (error)
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return error;
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error = rzg2l_cpg_add_pm_domains(priv);
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error = rzg2l_cpg_add_clk_domain(priv);
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if (error)
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return error;
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@@ -257,51 +257,6 @@ struct rzg2l_reset {
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#define DEF_RST(_id, _off, _bit) \
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DEF_RST_MON(_id, _off, _bit, -1)
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/**
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* struct rzg2l_cpg_reg_conf - RZ/G2L register configuration data structure
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* @off: register offset
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* @mask: register mask
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*/
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struct rzg2l_cpg_reg_conf {
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u16 off;
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u16 mask;
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};
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#define DEF_REG_CONF(_off, _mask) ((struct rzg2l_cpg_reg_conf) { .off = (_off), .mask = (_mask) })
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/**
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* struct rzg2l_cpg_pm_domain_conf - PM domain configuration data structure
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* @mstop: MSTOP register configuration
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*/
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struct rzg2l_cpg_pm_domain_conf {
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struct rzg2l_cpg_reg_conf mstop;
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};
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/**
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* struct rzg2l_cpg_pm_domain_init_data - PM domain init data
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* @name: PM domain name
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* @conf: PM domain configuration
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* @genpd_flags: genpd flags (see GENPD_FLAG_*)
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* @id: PM domain ID (similar to the ones defined in
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* include/dt-bindings/clock/<soc-id>-cpg.h)
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*/
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struct rzg2l_cpg_pm_domain_init_data {
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const char * const name;
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struct rzg2l_cpg_pm_domain_conf conf;
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u32 genpd_flags;
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u16 id;
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};
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#define DEF_PD(_name, _id, _mstop_conf, _flags) \
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{ \
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.name = (_name), \
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.id = (_id), \
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.conf = { \
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.mstop = (_mstop_conf), \
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}, \
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.genpd_flags = (_flags), \
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}
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/**
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* struct rzg2l_cpg_info - SoC-specific CPG Description
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*
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@@ -320,8 +275,6 @@ struct rzg2l_cpg_pm_domain_init_data {
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* @crit_mod_clks: Array with Module Clock IDs of critical clocks that
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* should not be disabled without a knowledgeable driver
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* @num_crit_mod_clks: Number of entries in crit_mod_clks[]
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* @pm_domains: PM domains init data array
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* @num_pm_domains: Number of PM domains
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* @has_clk_mon_regs: Flag indicating whether the SoC has CLK_MON registers
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*/
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struct rzg2l_cpg_info {
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@@ -348,10 +301,6 @@ struct rzg2l_cpg_info {
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const unsigned int *crit_mod_clks;
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unsigned int num_crit_mod_clks;
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/* Power domain. */
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const struct rzg2l_cpg_pm_domain_init_data *pm_domains;
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unsigned int num_pm_domains;
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bool has_clk_mon_regs;
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};
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