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drm/i915/sbi: split out intel_sbi_regs.h

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Split out display/intel_sbi_regs.h from i915_reg.h. Include both the SBI
interface MMIO as well as the known sideband offsets.

Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
Link: https://lore.kernel.org/r/c96197159e05ebcb63fcc05f0f0801624cd4fdeb.1748343520.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Jani Nikula
2025-06-04 16:28:42 +03:00
parent ad3cfb65ac
commit 0b6d7dbf18
6 changed files with 55 additions and 42 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/gpu/drm/i915/display/intel_pch_refclk.c
+1
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@@ -12,6 +12,7 @@
#include "intel_panel.h"
#include "intel_pch_refclk.h"
#include "intel_sbi.h"
#include "intel_sbi_regs.h"
static void lpt_fdi_reset_mphy(struct intel_display *display)
{
drivers/gpu/drm/i915/display/intel_sbi.c
+1 -1
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@@ -7,10 +7,10 @@
#include <drm/drm_print.h>
#include "i915_reg.h"
#include "intel_de.h"
#include "intel_display_core.h"
#include "intel_sbi.h"
#include "intel_sbi_regs.h"
/* SBI access */
static int intel_sbi_rw(struct intel_display *display, u16 reg,
drivers/gpu/drm/i915/display/intel_sbi_regs.h
+51
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@@ -0,0 +1,51 @@
/* SPDX-License-Identifier: MIT */
/* Copyright © 2025 Intel Corporation */
#ifndef __INTEL_SBI_REGS_H__
#define __INTEL_SBI_REGS_H__
#include "i915_reg_defs.h"
/*
* Sideband Interface (SBI) is programmed indirectly, via SBI_ADDR, which
* contains the register offset; and SBI_DATA, which contains the payload.
*/
#define SBI_ADDR _MMIO(0xC6000)
#define SBI_DATA _MMIO(0xC6004)
#define SBI_CTL_STAT _MMIO(0xC6008)
#define SBI_CTL_DEST_ICLK (0x0 << 16)
#define SBI_CTL_DEST_MPHY (0x1 << 16)
#define SBI_CTL_OP_IORD (0x2 << 8)
#define SBI_CTL_OP_IOWR (0x3 << 8)
#define SBI_CTL_OP_CRRD (0x6 << 8)
#define SBI_CTL_OP_CRWR (0x7 << 8)
#define SBI_RESPONSE_FAIL (0x1 << 1)
#define SBI_RESPONSE_SUCCESS (0x0 << 1)
#define SBI_BUSY (0x1 << 0)
#define SBI_READY (0x0 << 0)
/* SBI offsets */
#define SBI_SSCDIVINTPHASE 0x0200
#define SBI_SSCDIVINTPHASE6 0x0600
#define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1
#define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f << 1)
#define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x) << 1)
#define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8
#define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f << 8)
#define SBI_SSCDIVINTPHASE_INCVAL(x) ((x) << 8)
#define SBI_SSCDIVINTPHASE_DIR(x) ((x) << 15)
#define SBI_SSCDIVINTPHASE_PROPAGATE (1 << 0)
#define SBI_SSCDITHPHASE 0x0204
#define SBI_SSCCTL 0x020c
#define SBI_SSCCTL6 0x060C
#define SBI_SSCCTL_PATHALT (1 << 3)
#define SBI_SSCCTL_DISABLE (1 << 0)
#define SBI_SSCAUXDIV6 0x0610
#define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4
#define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1 << 4)
#define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x) << 4)
#define SBI_DBUFF0 0x2a00
#define SBI_GEN0 0x1f00
#define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1 << 0)
#endif /* __INTEL_SBI_REGS_H__ */
drivers/gpu/drm/i915/gvt/handlers.c
+1
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@@ -56,6 +56,7 @@
#include "display/intel_fdi_regs.h"
#include "display/intel_pps_regs.h"
#include "display/intel_psr_regs.h"
#include "display/intel_sbi_regs.h"
#include "display/intel_sprite_regs.h"
#include "display/intel_vga_regs.h"
#include "display/skl_universal_plane_regs.h"
drivers/gpu/drm/i915/i915_reg.h
-41
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@@ -3590,47 +3590,6 @@ enum skl_power_gate {
#define _DDI_DP_COMP_PAT_B 0x615F4
#define DDI_DP_COMP_PAT(pipe, i) _MMIO(_PIPE(pipe, _DDI_DP_COMP_PAT_A, _DDI_DP_COMP_PAT_B) + (i) * 4)
/* Sideband Interface (SBI) is programmed indirectly, via
* SBI_ADDR, which contains the register offset; and SBI_DATA,
* which contains the payload */
#define SBI_ADDR _MMIO(0xC6000)
#define SBI_DATA _MMIO(0xC6004)
#define SBI_CTL_STAT _MMIO(0xC6008)
#define SBI_CTL_DEST_ICLK (0x0 << 16)
#define SBI_CTL_DEST_MPHY (0x1 << 16)
#define SBI_CTL_OP_IORD (0x2 << 8)
#define SBI_CTL_OP_IOWR (0x3 << 8)
#define SBI_CTL_OP_CRRD (0x6 << 8)
#define SBI_CTL_OP_CRWR (0x7 << 8)
#define SBI_RESPONSE_FAIL (0x1 << 1)
#define SBI_RESPONSE_SUCCESS (0x0 << 1)
#define SBI_BUSY (0x1 << 0)
#define SBI_READY (0x0 << 0)
/* SBI offsets */
#define SBI_SSCDIVINTPHASE 0x0200
#define SBI_SSCDIVINTPHASE6 0x0600
#define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1
#define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f << 1)
#define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x) << 1)
#define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8
#define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f << 8)
#define SBI_SSCDIVINTPHASE_INCVAL(x) ((x) << 8)
#define SBI_SSCDIVINTPHASE_DIR(x) ((x) << 15)
#define SBI_SSCDIVINTPHASE_PROPAGATE (1 << 0)
#define SBI_SSCDITHPHASE 0x0204
#define SBI_SSCCTL 0x020c
#define SBI_SSCCTL6 0x060C
#define SBI_SSCCTL_PATHALT (1 << 3)
#define SBI_SSCCTL_DISABLE (1 << 0)
#define SBI_SSCAUXDIV6 0x0610
#define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4
#define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1 << 4)
#define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x) << 4)
#define SBI_DBUFF0 0x2a00
#define SBI_GEN0 0x1f00
#define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1 << 0)
/* LPT PIXCLK_GATE */
#define PIXCLK_GATE _MMIO(0xC6020)
#define PIXCLK_GATE_UNGATE (1 << 0)
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+1
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@@ -21,6 +21,7 @@
#include "display/intel_lvds_regs.h"
#include "display/intel_pfit_regs.h"
#include "display/intel_psr_regs.h"
#include "display/intel_sbi_regs.h"
#include "display/intel_sprite_regs.h"
#include "display/intel_vga_regs.h"
#include "display/skl_universal_plane_regs.h"