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dt-bindings: Correct indentation and style in DTS example

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DTS example in the bindings should be indented with 2- or 4-spaces and
aligned with opening '- |', so correct any differences like 3-spaces or
mixtures 2- and 4-spaces in one binding.

No functional changes here, but saves some comments during reviews of
new patches built on existing code.

Acked-by: Ulf Hansson <ulf.hansson@linaro.org> # For MMC
Acked-by: Lee Jones <lee@kernel.org>
Acked-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> # renesas
Link: https://lore.kernel.org/r/20250107131456.247610-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250725100241.120106-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
This commit is contained in:
Krzysztof Kozlowski
2025-07-28 19:56:29 -05:00
committed by Rob Herring (Arm)
parent 7ef2310b58
commit 0121898ec0
19 changed files with 342 additions and 342 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Documentation/devicetree/bindings/arm/arm,trace-buffer-extension.yaml
+5 -5
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@@ -41,10 +41,10 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
trbe {
compatible = "arm,trace-buffer-extension";
interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
};
trbe {
compatible = "arm,trace-buffer-extension";
interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
};
...
Documentation/devicetree/bindings/arm/stm32/st,mlahb.yaml
+10 -10
View File
@@ -55,17 +55,17 @@ unevaluatedProperties: false
examples:
- |
ahb {
compatible = "st,mlahb", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
dma-ranges = <0x00000000 0x38000000 0x10000>,
<0x10000000 0x10000000 0x60000>,
<0x30000000 0x30000000 0x60000>;
compatible = "st,mlahb", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
dma-ranges = <0x00000000 0x38000000 0x10000>,
<0x10000000 0x10000000 0x60000>,
<0x30000000 0x30000000 0x60000>;
m4_rproc: m4@10000000 {
reg = <0x10000000 0x40000>;
};
m4_rproc: m4@10000000 {
reg = <0x10000000 0x40000>;
};
};
...
Documentation/devicetree/bindings/dsp/mediatek,mt8195-dsp.yaml
+21 -21
View File
@@ -81,25 +81,25 @@ examples:
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
dsp@10803000 {
compatible = "mediatek,mt8195-dsp";
reg = <0x10803000 0x1000>,
<0x10840000 0x40000>;
reg-names = "cfg", "sram";
clocks = <&topckgen 10>, //CLK_TOP_ADSP
<&clk26m>,
<&topckgen 107>, //CLK_TOP_AUDIO_LOCAL_BUS
<&topckgen 136>, //CLK_TOP_MAINPLL_D7_D2
<&scp_adsp 0>, //CLK_SCP_ADSP_AUDIODSP
<&topckgen 34>; //CLK_TOP_AUDIO_H
clock-names = "adsp_sel",
"clk26m_ck",
"audio_local_bus",
"mainpll_d7_d2",
"scp_adsp_audiodsp",
"audio_h";
memory-region = <&adsp_dma_mem_reserved>,
<&adsp_mem_reserved>;
power-domains = <&spm 6>; //MT8195_POWER_DOMAIN_ADSP
mbox-names = "rx", "tx";
mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>;
compatible = "mediatek,mt8195-dsp";
reg = <0x10803000 0x1000>,
<0x10840000 0x40000>;
reg-names = "cfg", "sram";
clocks = <&topckgen 10>, //CLK_TOP_ADSP
<&clk26m>,
<&topckgen 107>, //CLK_TOP_AUDIO_LOCAL_BUS
<&topckgen 136>, //CLK_TOP_MAINPLL_D7_D2
<&scp_adsp 0>, //CLK_SCP_ADSP_AUDIODSP
<&topckgen 34>; //CLK_TOP_AUDIO_H
clock-names = "adsp_sel",
"clk26m_ck",
"audio_local_bus",
"mainpll_d7_d2",
"scp_adsp_audiodsp",
"audio_h";
memory-region = <&adsp_dma_mem_reserved>,
<&adsp_mem_reserved>;
power-domains = <&spm 6>; //MT8195_POWER_DOMAIN_ADSP
mbox-names = "rx", "tx";
mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>;
};
Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml
+26 -26
View File
@@ -62,33 +62,33 @@ examples:
#include <dt-bindings/gpio/gpio.h>
npe: npe@c8006000 {
compatible = "intel,ixp4xx-network-processing-engine";
reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "intel,ixp4xx-network-processing-engine";
reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
hss@0 {
compatible = "intel,ixp4xx-hss";
reg = <0>;
intel,npe-handle = <&npe 0>;
intel,queue-chl-rxtrig = <&qmgr 12>;
intel,queue-chl-txready = <&qmgr 34>;
intel,queue-pkt-rx = <&qmgr 13>;
intel,queue-pkt-tx = <&qmgr 14>, <&qmgr 15>, <&qmgr 16>, <&qmgr 17>;
intel,queue-pkt-rxfree = <&qmgr 18>, <&qmgr 19>, <&qmgr 20>, <&qmgr 21>;
intel,queue-pkt-txdone = <&qmgr 22>;
cts-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
rts-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
dcd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
dtr-gpios = <&gpio_74 2 GPIO_ACTIVE_LOW>;
clk-internal-gpios = <&gpio_74 0 GPIO_ACTIVE_HIGH>;
};
hss@0 {
compatible = "intel,ixp4xx-hss";
reg = <0>;
intel,npe-handle = <&npe 0>;
intel,queue-chl-rxtrig = <&qmgr 12>;
intel,queue-chl-txready = <&qmgr 34>;
intel,queue-pkt-rx = <&qmgr 13>;
intel,queue-pkt-tx = <&qmgr 14>, <&qmgr 15>, <&qmgr 16>, <&qmgr 17>;
intel,queue-pkt-rxfree = <&qmgr 18>, <&qmgr 19>, <&qmgr 20>, <&qmgr 21>;
intel,queue-pkt-txdone = <&qmgr 22>;
cts-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
rts-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
dcd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
dtr-gpios = <&gpio_74 2 GPIO_ACTIVE_LOW>;
clk-internal-gpios = <&gpio_74 0 GPIO_ACTIVE_HIGH>;
};
crypto {
compatible = "intel,ixp4xx-crypto";
intel,npe-handle = <&npe 2>;
queue-rx = <&qmgr 30>;
queue-txready = <&qmgr 29>;
};
crypto {
compatible = "intel,ixp4xx-crypto";
intel,npe-handle = <&npe 2>;
queue-rx = <&qmgr 30>;
queue-txready = <&qmgr 29>;
};
};
...
Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml
+1 -1
View File
@@ -27,7 +27,7 @@ additionalProperties: false
examples:
- |
versal_fpga: versal-fpga {
compatible = "xlnx,versal-fpga";
compatible = "xlnx,versal-fpga";
};
...
Documentation/devicetree/bindings/iommu/riscv,iommu.yaml
+3 -3
View File
@@ -139,9 +139,9 @@ examples:
/* The IOMMU programming interface uses slot 00:01.0 */
iommu0: iommu@1,0 {
compatible = "pci1efd,edf1", "riscv,pci-iommu";
reg = <0x800 0 0 0 0>;
#iommu-cells = <1>;
compatible = "pci1efd,edf1", "riscv,pci-iommu";
reg = <0x800 0 0 0 0>;
#iommu-cells = <1>;
};
};
};
Documentation/devicetree/bindings/leds/leds-mt6360.yaml
+97 -98
View File
@@ -87,106 +87,105 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/leds/common.h>
led-controller {
compatible = "mediatek,mt6360-led";
#address-cells = <1>;
#size-cells = <0>;
#include <dt-bindings/leds/common.h>
led-controller {
compatible = "mediatek,mt6360-led";
#address-cells = <1>;
#size-cells = <0>;
multi-led@0 {
reg = <0>;
function = LED_FUNCTION_INDICATOR;
color = <LED_COLOR_ID_RGB>;
led-max-microamp = <24000>;
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
color = <LED_COLOR_ID_RED>;
};
led@1 {
reg = <1>;
color = <LED_COLOR_ID_GREEN>;
};
led@2 {
reg = <2>;
color = <LED_COLOR_ID_BLUE>;
};
};
led@3 {
reg = <3>;
function = LED_FUNCTION_INDICATOR;
color = <LED_COLOR_ID_WHITE>;
led-max-microamp = <150000>;
};
led@4 {
reg = <4>;
function = LED_FUNCTION_FLASH;
color = <LED_COLOR_ID_WHITE>;
function-enumerator = <1>;
led-max-microamp = <200000>;
flash-max-microamp = <500000>;
flash-max-timeout-us = <1024000>;
};
led@5 {
reg = <5>;
function = LED_FUNCTION_FLASH;
color = <LED_COLOR_ID_WHITE>;
function-enumerator = <2>;
led-max-microamp = <200000>;
flash-max-microamp = <500000>;
flash-max-timeout-us = <1024000>;
};
};
multi-led@0 {
reg = <0>;
function = LED_FUNCTION_INDICATOR;
color = <LED_COLOR_ID_RGB>;
led-max-microamp = <24000>;
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
color = <LED_COLOR_ID_RED>;
};
led@1 {
reg = <1>;
color = <LED_COLOR_ID_GREEN>;
};
led@2 {
reg = <2>;
color = <LED_COLOR_ID_BLUE>;
};
};
led@3 {
reg = <3>;
function = LED_FUNCTION_INDICATOR;
color = <LED_COLOR_ID_WHITE>;
led-max-microamp = <150000>;
};
led@4 {
reg = <4>;
function = LED_FUNCTION_FLASH;
color = <LED_COLOR_ID_WHITE>;
function-enumerator = <1>;
led-max-microamp = <200000>;
flash-max-microamp = <500000>;
flash-max-timeout-us = <1024000>;
};
led@5 {
reg = <5>;
function = LED_FUNCTION_FLASH;
color = <LED_COLOR_ID_WHITE>;
function-enumerator = <2>;
led-max-microamp = <200000>;
flash-max-microamp = <500000>;
flash-max-timeout-us = <1024000>;
};
};
- |
led-controller {
compatible = "mediatek,mt6360-led";
#address-cells = <1>;
#size-cells = <0>;
led-controller {
compatible = "mediatek,mt6360-led";
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
function = LED_FUNCTION_INDICATOR;
color = <LED_COLOR_ID_RED>;
led-max-microamp = <24000>;
};
led@1 {
reg = <1>;
function = LED_FUNCTION_INDICATOR;
color = <LED_COLOR_ID_GREEN>;
led-max-microamp = <24000>;
};
led@2 {
reg = <2>;
function = LED_FUNCTION_INDICATOR;
color = <LED_COLOR_ID_BLUE>;
led-max-microamp = <24000>;
};
led@3 {
reg = <3>;
function = LED_FUNCTION_INDICATOR;
color = <LED_COLOR_ID_WHITE>;
led-max-microamp = <150000>;
};
led@4 {
reg = <4>;
function = LED_FUNCTION_FLASH;
color = <LED_COLOR_ID_WHITE>;
function-enumerator = <1>;
led-max-microamp = <200000>;
flash-max-microamp = <500000>;
flash-max-timeout-us = <1024000>;
};
led@5 {
reg = <5>;
function = LED_FUNCTION_FLASH;
color = <LED_COLOR_ID_WHITE>;
function-enumerator = <2>;
led-max-microamp = <200000>;
flash-max-microamp = <500000>;
flash-max-timeout-us = <1024000>;
};
};
led@0 {
reg = <0>;
function = LED_FUNCTION_INDICATOR;
color = <LED_COLOR_ID_RED>;
led-max-microamp = <24000>;
};
led@1 {
reg = <1>;
function = LED_FUNCTION_INDICATOR;
color = <LED_COLOR_ID_GREEN>;
led-max-microamp = <24000>;
};
led@2 {
reg = <2>;
function = LED_FUNCTION_INDICATOR;
color = <LED_COLOR_ID_BLUE>;
led-max-microamp = <24000>;
};
led@3 {
reg = <3>;
function = LED_FUNCTION_INDICATOR;
color = <LED_COLOR_ID_WHITE>;
led-max-microamp = <150000>;
};
led@4 {
reg = <4>;
function = LED_FUNCTION_FLASH;
color = <LED_COLOR_ID_WHITE>;
function-enumerator = <1>;
led-max-microamp = <200000>;
flash-max-microamp = <500000>;
flash-max-timeout-us = <1024000>;
};
led@5 {
reg = <5>;
function = LED_FUNCTION_FLASH;
color = <LED_COLOR_ID_WHITE>;
function-enumerator = <2>;
led-max-microamp = <200000>;
flash-max-microamp = <500000>;
flash-max-timeout-us = <1024000>;
};
};
...
Documentation/devicetree/bindings/mips/brcm/soc.yaml
+21 -21
View File
@@ -92,29 +92,29 @@ additionalProperties: true
examples:
- |
/ {
compatible = "brcm,bcm3368";
#address-cells = <1>;
#size-cells = <1>;
model = "Broadcom 3368";
/ {
compatible = "brcm,bcm3368";
#address-cells = <1>;
#size-cells = <1>;
model = "Broadcom 3368";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
mips-hpt-frequency = <150000000>;
mips-hpt-frequency = <150000000>;
cpu@0 {
compatible = "brcm,bmips4350";
device_type = "cpu";
reg = <0>;
};
cpu@0 {
compatible = "brcm,bmips4350";
device_type = "cpu";
reg = <0>;
};
cpu@1 {
compatible = "brcm,bmips4350";
device_type = "cpu";
reg = <1>;
};
};
};
cpu@1 {
compatible = "brcm,bmips4350";
device_type = "cpu";
reg = <1>;
};
};
};
...
Documentation/devicetree/bindings/misc/intel,ixp4xx-ahb-queue-manager.yaml
+3 -3
View File
@@ -45,7 +45,7 @@ examples:
#include <dt-bindings/interrupt-controller/irq.h>
qmgr: queue-manager@60000000 {
compatible = "intel,ixp4xx-ahb-queue-manager";
reg = <0x60000000 0x4000>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH>, <4 IRQ_TYPE_LEVEL_HIGH>;
compatible = "intel,ixp4xx-ahb-queue-manager";
reg = <0x60000000 0x4000>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH>, <4 IRQ_TYPE_LEVEL_HIGH>;
};
Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
+38 -38
View File
@@ -245,49 +245,49 @@ examples:
#include <dt-bindings/power/r8a7790-sysc.h>
sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
reg = <0xee100000 0x328>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 314>;
dmas = <&dmac0 0xcd>, <&dmac0 0xce>, <&dmac1 0xcd>, <&dmac1 0xce>;
dma-names = "tx", "rx", "tx", "rx";
max-frequency = <195000000>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 314>;
compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
reg = <0xee100000 0x328>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 314>;
dmas = <&dmac0 0xcd>, <&dmac0 0xce>, <&dmac1 0xcd>, <&dmac1 0xce>;
dma-names = "tx", "rx", "tx", "rx";
max-frequency = <195000000>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 314>;
};
sdhi1: mmc@ee120000 {
compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
reg = <0xee120000 0x328>;
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 313>;
dmas = <&dmac0 0xc9>, <&dmac0 0xca>, <&dmac1 0xc9>, <&dmac1 0xca>;
dma-names = "tx", "rx", "tx", "rx";
max-frequency = <195000000>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 313>;
compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
reg = <0xee120000 0x328>;
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 313>;
dmas = <&dmac0 0xc9>, <&dmac0 0xca>, <&dmac1 0xc9>, <&dmac1 0xca>;
dma-names = "tx", "rx", "tx", "rx";
max-frequency = <195000000>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 313>;
};
sdhi2: mmc@ee140000 {
compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
reg = <0xee140000 0x100>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 312>;
dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, <&dmac1 0xc1>, <&dmac1 0xc2>;
dma-names = "tx", "rx", "tx", "rx";
max-frequency = <97500000>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 312>;
};
compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
reg = <0xee140000 0x100>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 312>;
dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, <&dmac1 0xc1>, <&dmac1 0xc2>;
dma-names = "tx", "rx", "tx", "rx";
max-frequency = <97500000>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 312>;
};
sdhi3: mmc@ee160000 {
compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
reg = <0xee160000 0x100>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 311>;
dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, <&dmac1 0xd3>, <&dmac1 0xd4>;
dma-names = "tx", "rx", "tx", "rx";
max-frequency = <97500000>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 311>;
sdhi3: mmc@ee160000 {
compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
reg = <0xee160000 0x100>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 311>;
dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, <&dmac1 0xd3>, <&dmac1 0xd4>;
dma-names = "tx", "rx", "tx", "rx";
max-frequency = <97500000>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 311>;
};
Documentation/devicetree/bindings/mtd/technologic,nand.yaml
+1 -1
View File
@@ -40,6 +40,6 @@ examples:
#address-cells = <1>;
#size-cells = <0>;
nand@0 {
reg = <0>;
reg = <0>;
};
};
Documentation/devicetree/bindings/nvmem/amlogic,meson6-efuse.yaml
+1 -1
View File
@@ -53,6 +53,6 @@ examples:
};
temperature_calib: calib@1f4 {
reg = <0x1f4 0x4>;
reg = <0x1f4 0x4>;
};
};
Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
+17 -17
View File
@@ -123,21 +123,21 @@ examples:
#size-cells = <2>;
pcie0_ep: pcie-ep@d000000 {
compatible = "ti,j721e-pcie-ep";
reg = <0x00 0x02900000 0x00 0x1000>,
<0x00 0x02907000 0x00 0x400>,
<0x00 0x0d000000 0x00 0x00800000>,
<0x00 0x10000000 0x00 0x08000000>;
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;
max-link-speed = <3>;
num-lanes = <2>;
power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 239 1>;
clock-names = "fck";
max-functions = /bits/ 8 <6>;
dma-coherent;
phys = <&serdes0_pcie_link>;
phy-names = "pcie-phy";
};
compatible = "ti,j721e-pcie-ep";
reg = <0x00 0x02900000 0x00 0x1000>,
<0x00 0x02907000 0x00 0x400>,
<0x00 0x0d000000 0x00 0x00800000>,
<0x00 0x10000000 0x00 0x08000000>;
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;
max-link-speed = <3>;
num-lanes = <2>;
power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 239 1>;
clock-names = "fck";
max-functions = /bits/ 8 <6>;
dma-coherent;
phys = <&serdes0_pcie_link>;
phy-names = "pcie-phy";
};
};
Documentation/devicetree/bindings/power/reset/qcom,pon.yaml
+31 -31
View File
@@ -115,40 +115,40 @@ allOf:
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/spmi/spmi.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/spmi/spmi.h>
spmi@c440000 {
reg = <0x0c440000 0x1100>;
#address-cells = <2>;
#size-cells = <0>;
spmi@c440000 {
reg = <0x0c440000 0x1100>;
#address-cells = <2>;
#size-cells = <0>;
pmic@0 {
reg = <0x0 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmic@0 {
reg = <0x0 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pon@800 {
compatible = "qcom,pm8998-pon";
reg = <0x800>;
pon@800 {
compatible = "qcom,pm8998-pon";
reg = <0x800>;
pwrkey {
compatible = "qcom,pm8941-pwrkey";
interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>;
bias-pull-up;
linux,code = <KEY_POWER>;
};
pwrkey {
compatible = "qcom,pm8941-pwrkey";
interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>;
bias-pull-up;
linux,code = <KEY_POWER>;
};
resin {
compatible = "qcom,pm8941-resin";
interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>;
bias-pull-up;
linux,code = <KEY_VOLUMEDOWN>;
};
};
};
};
resin {
compatible = "qcom,pm8941-resin";
interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>;
bias-pull-up;
linux,code = <KEY_VOLUMEDOWN>;
};
};
};
};
...
Documentation/devicetree/bindings/reserved-memory/nvidia,tegra264-bpmp-shmem.yaml
+8 -7
View File
@@ -36,12 +36,13 @@ required:
examples:
- |
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
dram_cpu_bpmp_mail: shmem@f1be0000 {
compatible = "nvidia,tegra264-bpmp-shmem";
reg = <0x0 0xf1be0000 0x0 0x2000>;
no-map;
};
#address-cells = <2>;
#size-cells = <2>;
shmem@f1be0000 {
compatible = "nvidia,tegra264-bpmp-shmem";
reg = <0x0 0xf1be0000 0x0 0x2000>;
no-map;
};
};
...
Documentation/devicetree/bindings/rtc/renesas,rzn1-rtc.yaml
+11 -11
View File
@@ -61,14 +61,14 @@ examples:
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/r9a06g032-sysctrl.h>
rtc@40006000 {
compatible = "renesas,r9a06g032-rtc", "renesas,rzn1-rtc";
reg = <0x40006000 0x1000>;
interrupts = <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 67 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "alarm", "timer", "pps";
clocks = <&sysctrl R9A06G032_HCLK_RTC>;
clock-names = "hclk";
power-domains = <&sysctrl>;
start-year = <2000>;
};
compatible = "renesas,r9a06g032-rtc", "renesas,rzn1-rtc";
reg = <0x40006000 0x1000>;
interrupts = <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 67 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "alarm", "timer", "pps";
clocks = <&sysctrl R9A06G032_HCLK_RTC>;
clock-names = "hclk";
power-domains = <&sysctrl>;
start-year = <2000>;
};
Documentation/devicetree/bindings/soc/amlogic/amlogic,meson-gx-hhi-sysctrl.yaml
+13 -13
View File
@@ -186,22 +186,22 @@ examples:
};
power-controller {
compatible = "amlogic,meson-axg-pwrc";
#power-domain-cells = <1>;
amlogic,ao-sysctrl = <&sysctrl_AO>;
compatible = "amlogic,meson-axg-pwrc";
#power-domain-cells = <1>;
amlogic,ao-sysctrl = <&sysctrl_AO>;
resets = <&reset_viu>,
<&reset_venc>,
<&reset_vcbus>,
<&reset_vencl>,
<&reset_vid_lock>;
reset-names = "viu", "venc", "vcbus", "vencl", "vid_lock";
clocks = <&clk_vpu>, <&clk_vapb>;
clock-names = "vpu", "vapb";
resets = <&reset_viu>,
<&reset_venc>,
<&reset_vcbus>,
<&reset_vencl>,
<&reset_vid_lock>;
reset-names = "viu", "venc", "vcbus", "vencl", "vid_lock";
clocks = <&clk_vpu>, <&clk_vapb>;
clock-names = "vpu", "vapb";
};
phy {
compatible = "amlogic,axg-mipi-pcie-analog-phy";
#phy-cells = <0>;
compatible = "amlogic,axg-mipi-pcie-analog-phy";
#phy-cells = <0>;
};
};
Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml
+19 -19
View File
@@ -55,25 +55,25 @@ additionalProperties: false
examples:
- |
eud@88e0000 {
compatible = "qcom,sc7280-eud", "qcom,eud";
reg = <0x88e0000 0x2000>,
<0x88e2000 0x1000>;
compatible = "qcom,sc7280-eud", "qcom,eud";
reg = <0x88e0000 0x2000>,
<0x88e2000 0x1000>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
eud_ep: endpoint {
remote-endpoint = <&usb2_role_switch>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
eud_ep: endpoint {
remote-endpoint = <&usb2_role_switch>;
};
};
port@1 {
reg = <1>;
eud_con: endpoint {
remote-endpoint = <&con_eud>;
};
};
};
port@1 {
reg = <1>;
eud_con: endpoint {
remote-endpoint = <&con_eud>;
};
};
};
};
Documentation/devicetree/bindings/soc/ti/wkup-m3-ipc.yaml
+16 -16
View File
@@ -121,13 +121,13 @@ examples:
};
wkup_m3_ipc@1324 {
compatible = "ti,am3352-wkup-m3-ipc";
reg = <0x1324 0x24>;
interrupts = <78>;
ti,rproc = <&wkup_m3>;
mboxes = <&am335x_mailbox &mbox_wkupm3>;
ti,vtt-gpio-pin = <7>;
firmware-name = "am335x-evm-scale-data.bin";
compatible = "ti,am3352-wkup-m3-ipc";
reg = <0x1324 0x24>;
interrupts = <78>;
ti,rproc = <&wkup_m3>;
mboxes = <&am335x_mailbox &mbox_wkupm3>;
ti,vtt-gpio-pin = <7>;
firmware-name = "am335x-evm-scale-data.bin";
};
};
@@ -155,20 +155,20 @@ examples:
pinctrl-0 = <&ddr3_vtt_toggle_default>;
ddr3_vtt_toggle_default: ddr_vtt_toggle_default {
pinctrl-single,pins = <
pinctrl-single,pins = <
0x25C (DS0_PULL_UP_DOWN_EN | PIN_OUTPUT_PULLUP | DS0_FORCE_OFF_MODE | MUX_MODE7)
>;
>;
};
};
wkup_m3_ipc@1324 {
compatible = "ti,am4372-wkup-m3-ipc";
reg = <0x1324 0x24>;
interrupts = <78>;
ti,rproc = <&wkup_m3>;
mboxes = <&am437x_mailbox &mbox_wkupm3>;
ti,set-io-isolation;
firmware-name = "am43x-evm-scale-data.bin";
compatible = "ti,am4372-wkup-m3-ipc";
reg = <0x1324 0x24>;
interrupts = <78>;
ti,rproc = <&wkup_m3>;
mboxes = <&am437x_mailbox &mbox_wkupm3>;
ti,set-io-isolation;
firmware-name = "am43x-evm-scale-data.bin";
};
};