mirror of
https://github.com/clearlinux/kvmtool.git
synced 2026-09-04 20:51:28 +00:00
kvm: Remove duplicate headers
We're in the kernel source tree now so remove duplicate headers. Signed-off-by: Pekka Enberg <penberg@kernel.org>
This commit is contained in:
Pekka Enberg
committed by
Will Deacon
Will Deacon
parent
a267e01b64
commit
20c64ecabe
@@ -40,7 +40,7 @@ ifeq ($(uname_M),x86_64)
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endif
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endif
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CFLAGS += $(CPPFLAGS) $(DEFINES) -Iinclude -Os -g
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CFLAGS += $(CPPFLAGS) $(DEFINES) -Iinclude -I../../include -Os -g
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WARNINGS += -Werror
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WARNINGS += -Wall
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+2
-2
@@ -1,7 +1,5 @@
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#include "kvm/blk-virtio.h"
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#include "kvm/virtio_ring.h"
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#include "kvm/virtio_blk.h"
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#include "kvm/virtio_pci.h"
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#include "kvm/disk-image.h"
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#include "kvm/ioport.h"
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@@ -9,6 +7,8 @@
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#include "kvm/kvm.h"
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#include "kvm/pci.h"
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#include <linux/virtio_ring.h>
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#include <linux/virtio_blk.h>
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#include <inttypes.h>
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#include <assert.h>
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@@ -1,324 +0,0 @@
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#ifndef _ASM_X86_KVM_H
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#define _ASM_X86_KVM_H
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/*
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* KVM x86 specific structures and definitions
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*
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*/
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#include <linux/types.h>
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#include <linux/ioctl.h>
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/* Select x86 specific features in <linux/kvm.h> */
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#define __KVM_HAVE_PIT
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#define __KVM_HAVE_IOAPIC
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#define __KVM_HAVE_DEVICE_ASSIGNMENT
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#define __KVM_HAVE_MSI
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#define __KVM_HAVE_USER_NMI
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#define __KVM_HAVE_GUEST_DEBUG
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#define __KVM_HAVE_MSIX
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#define __KVM_HAVE_MCE
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#define __KVM_HAVE_PIT_STATE2
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#define __KVM_HAVE_XEN_HVM
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#define __KVM_HAVE_VCPU_EVENTS
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#define __KVM_HAVE_DEBUGREGS
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#define __KVM_HAVE_XSAVE
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#define __KVM_HAVE_XCRS
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/* Architectural interrupt line count. */
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#define KVM_NR_INTERRUPTS 256
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struct kvm_memory_alias {
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__u32 slot; /* this has a different namespace than memory slots */
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__u32 flags;
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__u64 guest_phys_addr;
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__u64 memory_size;
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__u64 target_phys_addr;
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};
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/* for KVM_GET_IRQCHIP and KVM_SET_IRQCHIP */
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struct kvm_pic_state {
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__u8 last_irr; /* edge detection */
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__u8 irr; /* interrupt request register */
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__u8 imr; /* interrupt mask register */
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__u8 isr; /* interrupt service register */
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__u8 priority_add; /* highest irq priority */
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__u8 irq_base;
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__u8 read_reg_select;
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__u8 poll;
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__u8 special_mask;
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__u8 init_state;
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__u8 auto_eoi;
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__u8 rotate_on_auto_eoi;
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__u8 special_fully_nested_mode;
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__u8 init4; /* true if 4 byte init */
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__u8 elcr; /* PIIX edge/trigger selection */
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__u8 elcr_mask;
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};
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#define KVM_IOAPIC_NUM_PINS 24
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struct kvm_ioapic_state {
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__u64 base_address;
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__u32 ioregsel;
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__u32 id;
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__u32 irr;
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__u32 pad;
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union {
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__u64 bits;
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struct {
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__u8 vector;
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__u8 delivery_mode:3;
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__u8 dest_mode:1;
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__u8 delivery_status:1;
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__u8 polarity:1;
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__u8 remote_irr:1;
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__u8 trig_mode:1;
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__u8 mask:1;
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__u8 reserve:7;
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__u8 reserved[4];
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__u8 dest_id;
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} fields;
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} redirtbl[KVM_IOAPIC_NUM_PINS];
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};
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#define KVM_IRQCHIP_PIC_MASTER 0
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#define KVM_IRQCHIP_PIC_SLAVE 1
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#define KVM_IRQCHIP_IOAPIC 2
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#define KVM_NR_IRQCHIPS 3
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/* for KVM_GET_REGS and KVM_SET_REGS */
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struct kvm_regs {
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/* out (KVM_GET_REGS) / in (KVM_SET_REGS) */
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__u64 rax, rbx, rcx, rdx;
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__u64 rsi, rdi, rsp, rbp;
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__u64 r8, r9, r10, r11;
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__u64 r12, r13, r14, r15;
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__u64 rip, rflags;
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};
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/* for KVM_GET_LAPIC and KVM_SET_LAPIC */
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#define KVM_APIC_REG_SIZE 0x400
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struct kvm_lapic_state {
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char regs[KVM_APIC_REG_SIZE];
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};
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struct kvm_segment {
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__u64 base;
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__u32 limit;
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__u16 selector;
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__u8 type;
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__u8 present, dpl, db, s, l, g, avl;
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__u8 unusable;
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__u8 padding;
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};
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struct kvm_dtable {
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__u64 base;
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__u16 limit;
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__u16 padding[3];
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};
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/* for KVM_GET_SREGS and KVM_SET_SREGS */
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struct kvm_sregs {
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/* out (KVM_GET_SREGS) / in (KVM_SET_SREGS) */
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struct kvm_segment cs, ds, es, fs, gs, ss;
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struct kvm_segment tr, ldt;
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struct kvm_dtable gdt, idt;
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__u64 cr0, cr2, cr3, cr4, cr8;
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__u64 efer;
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__u64 apic_base;
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__u64 interrupt_bitmap[(KVM_NR_INTERRUPTS + 63) / 64];
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};
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/* for KVM_GET_FPU and KVM_SET_FPU */
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struct kvm_fpu {
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__u8 fpr[8][16];
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__u16 fcw;
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__u16 fsw;
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__u8 ftwx; /* in fxsave format */
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__u8 pad1;
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__u16 last_opcode;
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__u64 last_ip;
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__u64 last_dp;
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__u8 xmm[16][16];
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__u32 mxcsr;
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__u32 pad2;
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};
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struct kvm_msr_entry {
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__u32 index;
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__u32 reserved;
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__u64 data;
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};
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/* for KVM_GET_MSRS and KVM_SET_MSRS */
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struct kvm_msrs {
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__u32 nmsrs; /* number of msrs in entries */
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__u32 pad;
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struct kvm_msr_entry entries[0];
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};
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/* for KVM_GET_MSR_INDEX_LIST */
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struct kvm_msr_list {
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__u32 nmsrs; /* number of msrs in entries */
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__u32 indices[0];
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};
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struct kvm_cpuid_entry {
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__u32 function;
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__u32 eax;
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__u32 ebx;
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__u32 ecx;
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__u32 edx;
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__u32 padding;
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};
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/* for KVM_SET_CPUID */
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struct kvm_cpuid {
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__u32 nent;
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__u32 padding;
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struct kvm_cpuid_entry entries[0];
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};
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struct kvm_cpuid_entry2 {
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__u32 function;
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__u32 index;
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__u32 flags;
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__u32 eax;
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__u32 ebx;
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__u32 ecx;
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__u32 edx;
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__u32 padding[3];
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};
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#define KVM_CPUID_FLAG_SIGNIFCANT_INDEX 1
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#define KVM_CPUID_FLAG_STATEFUL_FUNC 2
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#define KVM_CPUID_FLAG_STATE_READ_NEXT 4
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/* for KVM_SET_CPUID2 */
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struct kvm_cpuid2 {
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__u32 nent;
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__u32 padding;
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struct kvm_cpuid_entry2 entries[0];
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};
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/* for KVM_GET_PIT and KVM_SET_PIT */
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struct kvm_pit_channel_state {
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__u32 count; /* can be 65536 */
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__u16 latched_count;
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__u8 count_latched;
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__u8 status_latched;
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__u8 status;
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__u8 read_state;
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__u8 write_state;
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__u8 write_latch;
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__u8 rw_mode;
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__u8 mode;
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__u8 bcd;
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__u8 gate;
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__s64 count_load_time;
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};
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struct kvm_debug_exit_arch {
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__u32 exception;
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__u32 pad;
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__u64 pc;
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__u64 dr6;
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__u64 dr7;
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};
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#define KVM_GUESTDBG_USE_SW_BP 0x00010000
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#define KVM_GUESTDBG_USE_HW_BP 0x00020000
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#define KVM_GUESTDBG_INJECT_DB 0x00040000
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#define KVM_GUESTDBG_INJECT_BP 0x00080000
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/* for KVM_SET_GUEST_DEBUG */
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struct kvm_guest_debug_arch {
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__u64 debugreg[8];
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};
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struct kvm_pit_state {
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struct kvm_pit_channel_state channels[3];
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};
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#define KVM_PIT_FLAGS_HPET_LEGACY 0x00000001
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struct kvm_pit_state2 {
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struct kvm_pit_channel_state channels[3];
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__u32 flags;
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__u32 reserved[9];
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};
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struct kvm_reinject_control {
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__u8 pit_reinject;
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__u8 reserved[31];
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};
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/* When set in flags, include corresponding fields on KVM_SET_VCPU_EVENTS */
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#define KVM_VCPUEVENT_VALID_NMI_PENDING 0x00000001
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#define KVM_VCPUEVENT_VALID_SIPI_VECTOR 0x00000002
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#define KVM_VCPUEVENT_VALID_SHADOW 0x00000004
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/* Interrupt shadow states */
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#define KVM_X86_SHADOW_INT_MOV_SS 0x01
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#define KVM_X86_SHADOW_INT_STI 0x02
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/* for KVM_GET/SET_VCPU_EVENTS */
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struct kvm_vcpu_events {
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struct {
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__u8 injected;
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__u8 nr;
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__u8 has_error_code;
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__u8 pad;
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__u32 error_code;
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} exception;
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struct {
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__u8 injected;
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__u8 nr;
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__u8 soft;
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__u8 shadow;
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} interrupt;
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struct {
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__u8 injected;
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__u8 pending;
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__u8 masked;
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__u8 pad;
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} nmi;
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__u32 sipi_vector;
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__u32 flags;
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__u32 reserved[10];
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};
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/* for KVM_GET/SET_DEBUGREGS */
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struct kvm_debugregs {
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__u64 db[4];
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__u64 dr6;
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__u64 dr7;
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__u64 flags;
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__u64 reserved[9];
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};
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/* for KVM_CAP_XSAVE */
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struct kvm_xsave {
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__u32 region[1024];
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};
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#define KVM_MAX_XCRS 16
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struct kvm_xcr {
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__u32 xcr;
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__u32 reserved;
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__u64 value;
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};
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struct kvm_xcrs {
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__u32 nr_xcrs;
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__u32 flags;
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struct kvm_xcr xcrs[KVM_MAX_XCRS];
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__u64 padding[16];
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};
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#endif /* _ASM_X86_KVM_H */
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+1
-1
@@ -3,7 +3,7 @@
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#include <inttypes.h>
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#include "pci_regs.h"
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#include <linux/pci_regs.h>
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/*
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* PCI Configuration Mechanism #1 I/O ports. See Section 3.7.4.1.
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@@ -1,686 +0,0 @@
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/*
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* pci_regs.h
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*
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* PCI standard defines
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* Copyright 1994, Drew Eckhardt
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* Copyright 1997--1999 Martin Mares <mj@ucw.cz>
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*
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* For more information, please consult the following manuals (look at
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* http://www.pcisig.com/ for how to get them):
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*
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* PCI BIOS Specification
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* PCI Local Bus Specification
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* PCI to PCI Bridge Specification
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* PCI System Design Guide
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*
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* For hypertransport information, please consult the following manuals
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* from http://www.hypertransport.org
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*
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* The Hypertransport I/O Link Specification
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*/
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#ifndef LINUX_PCI_REGS_H
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#define LINUX_PCI_REGS_H
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/*
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* Under PCI, each device has 256 bytes of configuration address space,
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* of which the first 64 bytes are standardized as follows:
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*/
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#define PCI_VENDOR_ID 0x00 /* 16 bits */
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#define PCI_DEVICE_ID 0x02 /* 16 bits */
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#define PCI_COMMAND 0x04 /* 16 bits */
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#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
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#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
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#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
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#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
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#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
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#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
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#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
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#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
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#define PCI_COMMAND_SERR 0x100 /* Enable SERR */
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#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
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#define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
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#define PCI_STATUS 0x06 /* 16 bits */
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#define PCI_STATUS_INTERRUPT 0x08 /* Interrupt status */
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#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
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#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
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#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
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#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
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#define PCI_STATUS_PARITY 0x100 /* Detected parity error */
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#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
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#define PCI_STATUS_DEVSEL_FAST 0x000
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#define PCI_STATUS_DEVSEL_MEDIUM 0x200
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#define PCI_STATUS_DEVSEL_SLOW 0x400
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#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
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#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
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#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
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#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
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#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
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#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 revision */
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#define PCI_REVISION_ID 0x08 /* Revision ID */
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#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
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#define PCI_CLASS_DEVICE 0x0a /* Device class */
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#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
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#define PCI_LATENCY_TIMER 0x0d /* 8 bits */
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#define PCI_HEADER_TYPE 0x0e /* 8 bits */
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#define PCI_HEADER_TYPE_NORMAL 0
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#define PCI_HEADER_TYPE_BRIDGE 1
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#define PCI_HEADER_TYPE_CARDBUS 2
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#define PCI_BIST 0x0f /* 8 bits */
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#define PCI_BIST_CODE_MASK 0x0f /* Return result */
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#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
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#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
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/*
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* Base addresses specify locations in memory or I/O space.
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* Decoded size can be determined by writing a value of
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* 0xffffffff to the register, and reading it back. Only
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* 1 bits are decoded.
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*/
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#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
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#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
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#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
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#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
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#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
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#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
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#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
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#define PCI_BASE_ADDRESS_SPACE_IO 0x01
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#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
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#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
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#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
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#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
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#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
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#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
|
||||
#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
|
||||
#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL)
|
||||
/* bit 1 is reserved if address_space = 1 */
|
||||
|
||||
/* Header type 0 (normal devices) */
|
||||
#define PCI_CARDBUS_CIS 0x28
|
||||
#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
|
||||
#define PCI_SUBSYSTEM_ID 0x2e
|
||||
#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
|
||||
#define PCI_ROM_ADDRESS_ENABLE 0x01
|
||||
#define PCI_ROM_ADDRESS_MASK (~0x7ffUL)
|
||||
|
||||
#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
|
||||
|
||||
/* 0x35-0x3b are reserved */
|
||||
#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
|
||||
#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
|
||||
#define PCI_MIN_GNT 0x3e /* 8 bits */
|
||||
#define PCI_MAX_LAT 0x3f /* 8 bits */
|
||||
|
||||
/* Header type 1 (PCI-to-PCI bridges) */
|
||||
#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
|
||||
#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
|
||||
#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
|
||||
#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
|
||||
#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
|
||||
#define PCI_IO_LIMIT 0x1d
|
||||
#define PCI_IO_RANGE_TYPE_MASK 0x0fUL /* I/O bridging type */
|
||||
#define PCI_IO_RANGE_TYPE_16 0x00
|
||||
#define PCI_IO_RANGE_TYPE_32 0x01
|
||||
#define PCI_IO_RANGE_MASK (~0x0fUL)
|
||||
#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
|
||||
#define PCI_MEMORY_BASE 0x20 /* Memory range behind */
|
||||
#define PCI_MEMORY_LIMIT 0x22
|
||||
#define PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL
|
||||
#define PCI_MEMORY_RANGE_MASK (~0x0fUL)
|
||||
#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
|
||||
#define PCI_PREF_MEMORY_LIMIT 0x26
|
||||
#define PCI_PREF_RANGE_TYPE_MASK 0x0fUL
|
||||
#define PCI_PREF_RANGE_TYPE_32 0x00
|
||||
#define PCI_PREF_RANGE_TYPE_64 0x01
|
||||
#define PCI_PREF_RANGE_MASK (~0x0fUL)
|
||||
#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
|
||||
#define PCI_PREF_LIMIT_UPPER32 0x2c
|
||||
#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
|
||||
#define PCI_IO_LIMIT_UPPER16 0x32
|
||||
/* 0x34 same as for htype 0 */
|
||||
/* 0x35-0x3b is reserved */
|
||||
#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
|
||||
/* 0x3c-0x3d are same as for htype 0 */
|
||||
#define PCI_BRIDGE_CONTROL 0x3e
|
||||
#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
|
||||
#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
|
||||
#define PCI_BRIDGE_CTL_ISA 0x04 /* Enable ISA mode */
|
||||
#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
|
||||
#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
|
||||
#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
|
||||
#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
|
||||
|
||||
/* Header type 2 (CardBus bridges) */
|
||||
#define PCI_CB_CAPABILITY_LIST 0x14
|
||||
/* 0x15 reserved */
|
||||
#define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
|
||||
#define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
|
||||
#define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
|
||||
#define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
|
||||
#define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
|
||||
#define PCI_CB_MEMORY_BASE_0 0x1c
|
||||
#define PCI_CB_MEMORY_LIMIT_0 0x20
|
||||
#define PCI_CB_MEMORY_BASE_1 0x24
|
||||
#define PCI_CB_MEMORY_LIMIT_1 0x28
|
||||
#define PCI_CB_IO_BASE_0 0x2c
|
||||
#define PCI_CB_IO_BASE_0_HI 0x2e
|
||||
#define PCI_CB_IO_LIMIT_0 0x30
|
||||
#define PCI_CB_IO_LIMIT_0_HI 0x32
|
||||
#define PCI_CB_IO_BASE_1 0x34
|
||||
#define PCI_CB_IO_BASE_1_HI 0x36
|
||||
#define PCI_CB_IO_LIMIT_1 0x38
|
||||
#define PCI_CB_IO_LIMIT_1_HI 0x3a
|
||||
#define PCI_CB_IO_RANGE_MASK (~0x03UL)
|
||||
/* 0x3c-0x3d are same as for htype 0 */
|
||||
#define PCI_CB_BRIDGE_CONTROL 0x3e
|
||||
#define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
|
||||
#define PCI_CB_BRIDGE_CTL_SERR 0x02
|
||||
#define PCI_CB_BRIDGE_CTL_ISA 0x04
|
||||
#define PCI_CB_BRIDGE_CTL_VGA 0x08
|
||||
#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
|
||||
#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
|
||||
#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
|
||||
#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
|
||||
#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
|
||||
#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
|
||||
#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
|
||||
#define PCI_CB_SUBSYSTEM_ID 0x42
|
||||
#define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
|
||||
/* 0x48-0x7f reserved */
|
||||
|
||||
/* Capability lists */
|
||||
|
||||
#define PCI_CAP_LIST_ID 0 /* Capability ID */
|
||||
#define PCI_CAP_ID_PM 0x01 /* Power Management */
|
||||
#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
|
||||
#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
|
||||
#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
|
||||
#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
|
||||
#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
|
||||
#define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
|
||||
#define PCI_CAP_ID_HT 0x08 /* HyperTransport */
|
||||
#define PCI_CAP_ID_VNDR 0x09 /* Vendor specific */
|
||||
#define PCI_CAP_ID_DBG 0x0A /* Debug port */
|
||||
#define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */
|
||||
#define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
|
||||
#define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */
|
||||
#define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */
|
||||
#define PCI_CAP_ID_EXP 0x10 /* PCI Express */
|
||||
#define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
|
||||
#define PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */
|
||||
#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
|
||||
#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
|
||||
#define PCI_CAP_SIZEOF 4
|
||||
|
||||
/* Power Management Registers */
|
||||
|
||||
#define PCI_PM_PMC 2 /* PM Capabilities Register */
|
||||
#define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
|
||||
#define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
|
||||
#define PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */
|
||||
#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
|
||||
#define PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxilliary power support mask */
|
||||
#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
|
||||
#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
|
||||
#define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
|
||||
#define PCI_PM_CAP_PME_MASK 0xF800 /* PME Mask of all supported states */
|
||||
#define PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */
|
||||
#define PCI_PM_CAP_PME_D1 0x1000 /* PME# from D1 */
|
||||
#define PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */
|
||||
#define PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */
|
||||
#define PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */
|
||||
#define PCI_PM_CAP_PME_SHIFT 11 /* Start of the PME Mask in PMC */
|
||||
#define PCI_PM_CTRL 4 /* PM control and status register */
|
||||
#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
|
||||
#define PCI_PM_CTRL_NO_SOFT_RESET 0x0008 /* No reset for D3hot->D0 */
|
||||
#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
|
||||
#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
|
||||
#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
|
||||
#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
|
||||
#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
|
||||
#define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
|
||||
#define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
|
||||
#define PCI_PM_DATA_REGISTER 7 /* (??) */
|
||||
#define PCI_PM_SIZEOF 8
|
||||
|
||||
/* AGP registers */
|
||||
|
||||
#define PCI_AGP_VERSION 2 /* BCD version number */
|
||||
#define PCI_AGP_RFU 3 /* Rest of capability flags */
|
||||
#define PCI_AGP_STATUS 4 /* Status register */
|
||||
#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
|
||||
#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
|
||||
#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
|
||||
#define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
|
||||
#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
|
||||
#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
|
||||
#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
|
||||
#define PCI_AGP_COMMAND 8 /* Control register */
|
||||
#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
|
||||
#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
|
||||
#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
|
||||
#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
|
||||
#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
|
||||
#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
|
||||
#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate */
|
||||
#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate */
|
||||
#define PCI_AGP_SIZEOF 12
|
||||
|
||||
/* Vital Product Data */
|
||||
|
||||
#define PCI_VPD_ADDR 2 /* Address to access (15 bits!) */
|
||||
#define PCI_VPD_ADDR_MASK 0x7fff /* Address mask */
|
||||
#define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */
|
||||
#define PCI_VPD_DATA 4 /* 32-bits of data returned here */
|
||||
|
||||
/* Slot Identification */
|
||||
|
||||
#define PCI_SID_ESR 2 /* Expansion Slot Register */
|
||||
#define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
|
||||
#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
|
||||
#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
|
||||
|
||||
/* Message Signalled Interrupts registers */
|
||||
|
||||
#define PCI_MSI_FLAGS 2 /* Various flags */
|
||||
#define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
|
||||
#define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
|
||||
#define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
|
||||
#define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
|
||||
#define PCI_MSI_FLAGS_MASKBIT 0x100 /* 64-bit mask bits allowed */
|
||||
#define PCI_MSI_RFU 3 /* Rest of capability flags */
|
||||
#define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
|
||||
#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
|
||||
#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
|
||||
#define PCI_MSI_MASK_32 12 /* Mask bits register for 32-bit devices */
|
||||
#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
|
||||
#define PCI_MSI_MASK_64 16 /* Mask bits register for 64-bit devices */
|
||||
|
||||
/* MSI-X registers (these are at offset PCI_MSIX_FLAGS) */
|
||||
#define PCI_MSIX_FLAGS 2
|
||||
#define PCI_MSIX_FLAGS_QSIZE 0x7FF
|
||||
#define PCI_MSIX_FLAGS_ENABLE (1 << 15)
|
||||
#define PCI_MSIX_FLAGS_MASKALL (1 << 14)
|
||||
#define PCI_MSIX_FLAGS_BIRMASK (7 << 0)
|
||||
|
||||
/* CompactPCI Hotswap Register */
|
||||
|
||||
#define PCI_CHSWP_CSR 2 /* Control and Status Register */
|
||||
#define PCI_CHSWP_DHA 0x01 /* Device Hiding Arm */
|
||||
#define PCI_CHSWP_EIM 0x02 /* ENUM# Signal Mask */
|
||||
#define PCI_CHSWP_PIE 0x04 /* Pending Insert or Extract */
|
||||
#define PCI_CHSWP_LOO 0x08 /* LED On / Off */
|
||||
#define PCI_CHSWP_PI 0x30 /* Programming Interface */
|
||||
#define PCI_CHSWP_EXT 0x40 /* ENUM# status - extraction */
|
||||
#define PCI_CHSWP_INS 0x80 /* ENUM# status - insertion */
|
||||
|
||||
/* PCI Advanced Feature registers */
|
||||
|
||||
#define PCI_AF_LENGTH 2
|
||||
#define PCI_AF_CAP 3
|
||||
#define PCI_AF_CAP_TP 0x01
|
||||
#define PCI_AF_CAP_FLR 0x02
|
||||
#define PCI_AF_CTRL 4
|
||||
#define PCI_AF_CTRL_FLR 0x01
|
||||
#define PCI_AF_STATUS 5
|
||||
#define PCI_AF_STATUS_TP 0x01
|
||||
|
||||
/* PCI-X registers */
|
||||
|
||||
#define PCI_X_CMD 2 /* Modes & Features */
|
||||
#define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
|
||||
#define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
|
||||
#define PCI_X_CMD_READ_512 0x0000 /* 512 byte maximum read byte count */
|
||||
#define PCI_X_CMD_READ_1K 0x0004 /* 1Kbyte maximum read byte count */
|
||||
#define PCI_X_CMD_READ_2K 0x0008 /* 2Kbyte maximum read byte count */
|
||||
#define PCI_X_CMD_READ_4K 0x000c /* 4Kbyte maximum read byte count */
|
||||
#define PCI_X_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */
|
||||
/* Max # of outstanding split transactions */
|
||||
#define PCI_X_CMD_SPLIT_1 0x0000 /* Max 1 */
|
||||
#define PCI_X_CMD_SPLIT_2 0x0010 /* Max 2 */
|
||||
#define PCI_X_CMD_SPLIT_3 0x0020 /* Max 3 */
|
||||
#define PCI_X_CMD_SPLIT_4 0x0030 /* Max 4 */
|
||||
#define PCI_X_CMD_SPLIT_8 0x0040 /* Max 8 */
|
||||
#define PCI_X_CMD_SPLIT_12 0x0050 /* Max 12 */
|
||||
#define PCI_X_CMD_SPLIT_16 0x0060 /* Max 16 */
|
||||
#define PCI_X_CMD_SPLIT_32 0x0070 /* Max 32 */
|
||||
#define PCI_X_CMD_MAX_SPLIT 0x0070 /* Max Outstanding Split Transactions */
|
||||
#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */
|
||||
#define PCI_X_STATUS 4 /* PCI-X capabilities */
|
||||
#define PCI_X_STATUS_DEVFN 0x000000ff /* A copy of devfn */
|
||||
#define PCI_X_STATUS_BUS 0x0000ff00 /* A copy of bus nr */
|
||||
#define PCI_X_STATUS_64BIT 0x00010000 /* 64-bit device */
|
||||
#define PCI_X_STATUS_133MHZ 0x00020000 /* 133 MHz capable */
|
||||
#define PCI_X_STATUS_SPL_DISC 0x00040000 /* Split Completion Discarded */
|
||||
#define PCI_X_STATUS_UNX_SPL 0x00080000 /* Unexpected Split Completion */
|
||||
#define PCI_X_STATUS_COMPLEX 0x00100000 /* Device Complexity */
|
||||
#define PCI_X_STATUS_MAX_READ 0x00600000 /* Designed Max Memory Read Count */
|
||||
#define PCI_X_STATUS_MAX_SPLIT 0x03800000 /* Designed Max Outstanding Split Transactions */
|
||||
#define PCI_X_STATUS_MAX_CUM 0x1c000000 /* Designed Max Cumulative Read Size */
|
||||
#define PCI_X_STATUS_SPL_ERR 0x20000000 /* Rcvd Split Completion Error Msg */
|
||||
#define PCI_X_STATUS_266MHZ 0x40000000 /* 266 MHz capable */
|
||||
#define PCI_X_STATUS_533MHZ 0x80000000 /* 533 MHz capable */
|
||||
|
||||
/* PCI Bridge Subsystem ID registers */
|
||||
|
||||
#define PCI_SSVID_VENDOR_ID 4 /* PCI-Bridge subsystem vendor id register */
|
||||
#define PCI_SSVID_DEVICE_ID 6 /* PCI-Bridge subsystem device id register */
|
||||
|
||||
/* PCI Express capability registers */
|
||||
|
||||
#define PCI_EXP_FLAGS 2 /* Capabilities register */
|
||||
#define PCI_EXP_FLAGS_VERS 0x000f /* Capability version */
|
||||
#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
|
||||
#define PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */
|
||||
#define PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */
|
||||
#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
|
||||
#define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
|
||||
#define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
|
||||
#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */
|
||||
#define PCI_EXP_TYPE_RC_END 0x9 /* Root Complex Integrated Endpoint */
|
||||
#define PCI_EXP_TYPE_RC_EC 0x10 /* Root Complex Event Collector */
|
||||
#define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
|
||||
#define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
|
||||
#define PCI_EXP_DEVCAP 4 /* Device capabilities */
|
||||
#define PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */
|
||||
#define PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */
|
||||
#define PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */
|
||||
#define PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */
|
||||
#define PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */
|
||||
#define PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */
|
||||
#define PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */
|
||||
#define PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */
|
||||
#define PCI_EXP_DEVCAP_RBER 0x8000 /* Role-Based Error Reporting */
|
||||
#define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
|
||||
#define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
|
||||
#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */
|
||||
#define PCI_EXP_DEVCTL 8 /* Device Control */
|
||||
#define PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */
|
||||
#define PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */
|
||||
#define PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */
|
||||
#define PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */
|
||||
#define PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */
|
||||
#define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */
|
||||
#define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
|
||||
#define PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */
|
||||
#define PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */
|
||||
#define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */
|
||||
#define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
|
||||
#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */
|
||||
#define PCI_EXP_DEVSTA 10 /* Device Status */
|
||||
#define PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */
|
||||
#define PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */
|
||||
#define PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */
|
||||
#define PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Request Detected */
|
||||
#define PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */
|
||||
#define PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */
|
||||
#define PCI_EXP_LNKCAP 12 /* Link Capabilities */
|
||||
#define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */
|
||||
#define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */
|
||||
#define PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */
|
||||
#define PCI_EXP_LNKCAP_L0SEL 0x00007000 /* L0s Exit Latency */
|
||||
#define PCI_EXP_LNKCAP_L1EL 0x00038000 /* L1 Exit Latency */
|
||||
#define PCI_EXP_LNKCAP_CLKPM 0x00040000 /* L1 Clock Power Management */
|
||||
#define PCI_EXP_LNKCAP_SDERC 0x00080000 /* Suprise Down Error Reporting Capable */
|
||||
#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */
|
||||
#define PCI_EXP_LNKCAP_LBNC 0x00200000 /* Link Bandwidth Notification Capability */
|
||||
#define PCI_EXP_LNKCAP_PN 0xff000000 /* Port Number */
|
||||
#define PCI_EXP_LNKCTL 16 /* Link Control */
|
||||
#define PCI_EXP_LNKCTL_ASPMC 0x0003 /* ASPM Control */
|
||||
#define PCI_EXP_LNKCTL_RCB 0x0008 /* Read Completion Boundary */
|
||||
#define PCI_EXP_LNKCTL_LD 0x0010 /* Link Disable */
|
||||
#define PCI_EXP_LNKCTL_RL 0x0020 /* Retrain Link */
|
||||
#define PCI_EXP_LNKCTL_CCC 0x0040 /* Common Clock Configuration */
|
||||
#define PCI_EXP_LNKCTL_ES 0x0080 /* Extended Synch */
|
||||
#define PCI_EXP_LNKCTL_CLKREQ_EN 0x100 /* Enable clkreq */
|
||||
#define PCI_EXP_LNKCTL_HAWD 0x0200 /* Hardware Autonomous Width Disable */
|
||||
#define PCI_EXP_LNKCTL_LBMIE 0x0400 /* Link Bandwidth Management Interrupt Enable */
|
||||
#define PCI_EXP_LNKCTL_LABIE 0x0800 /* Lnk Autonomous Bandwidth Interrupt Enable */
|
||||
#define PCI_EXP_LNKSTA 18 /* Link Status */
|
||||
#define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */
|
||||
#define PCI_EXP_LNKSTA_CLS_2_5GB 0x01 /* Current Link Speed 2.5GT/s */
|
||||
#define PCI_EXP_LNKSTA_CLS_5_0GB 0x02 /* Current Link Speed 5.0GT/s */
|
||||
#define PCI_EXP_LNKSTA_NLW 0x03f0 /* Nogotiated Link Width */
|
||||
#define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */
|
||||
#define PCI_EXP_LNKSTA_LT 0x0800 /* Link Training */
|
||||
#define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */
|
||||
#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */
|
||||
#define PCI_EXP_LNKSTA_LBMS 0x4000 /* Link Bandwidth Management Status */
|
||||
#define PCI_EXP_LNKSTA_LABS 0x8000 /* Link Autonomous Bandwidth Status */
|
||||
#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
|
||||
#define PCI_EXP_SLTCAP_ABP 0x00000001 /* Attention Button Present */
|
||||
#define PCI_EXP_SLTCAP_PCP 0x00000002 /* Power Controller Present */
|
||||
#define PCI_EXP_SLTCAP_MRLSP 0x00000004 /* MRL Sensor Present */
|
||||
#define PCI_EXP_SLTCAP_AIP 0x00000008 /* Attention Indicator Present */
|
||||
#define PCI_EXP_SLTCAP_PIP 0x00000010 /* Power Indicator Present */
|
||||
#define PCI_EXP_SLTCAP_HPS 0x00000020 /* Hot-Plug Surprise */
|
||||
#define PCI_EXP_SLTCAP_HPC 0x00000040 /* Hot-Plug Capable */
|
||||
#define PCI_EXP_SLTCAP_SPLV 0x00007f80 /* Slot Power Limit Value */
|
||||
#define PCI_EXP_SLTCAP_SPLS 0x00018000 /* Slot Power Limit Scale */
|
||||
#define PCI_EXP_SLTCAP_EIP 0x00020000 /* Electromechanical Interlock Present */
|
||||
#define PCI_EXP_SLTCAP_NCCS 0x00040000 /* No Command Completed Support */
|
||||
#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */
|
||||
#define PCI_EXP_SLTCTL 24 /* Slot Control */
|
||||
#define PCI_EXP_SLTCTL_ABPE 0x0001 /* Attention Button Pressed Enable */
|
||||
#define PCI_EXP_SLTCTL_PFDE 0x0002 /* Power Fault Detected Enable */
|
||||
#define PCI_EXP_SLTCTL_MRLSCE 0x0004 /* MRL Sensor Changed Enable */
|
||||
#define PCI_EXP_SLTCTL_PDCE 0x0008 /* Presence Detect Changed Enable */
|
||||
#define PCI_EXP_SLTCTL_CCIE 0x0010 /* Command Completed Interrupt Enable */
|
||||
#define PCI_EXP_SLTCTL_HPIE 0x0020 /* Hot-Plug Interrupt Enable */
|
||||
#define PCI_EXP_SLTCTL_AIC 0x00c0 /* Attention Indicator Control */
|
||||
#define PCI_EXP_SLTCTL_PIC 0x0300 /* Power Indicator Control */
|
||||
#define PCI_EXP_SLTCTL_PCC 0x0400 /* Power Controller Control */
|
||||
#define PCI_EXP_SLTCTL_EIC 0x0800 /* Electromechanical Interlock Control */
|
||||
#define PCI_EXP_SLTCTL_DLLSCE 0x1000 /* Data Link Layer State Changed Enable */
|
||||
#define PCI_EXP_SLTSTA 26 /* Slot Status */
|
||||
#define PCI_EXP_SLTSTA_ABP 0x0001 /* Attention Button Pressed */
|
||||
#define PCI_EXP_SLTSTA_PFD 0x0002 /* Power Fault Detected */
|
||||
#define PCI_EXP_SLTSTA_MRLSC 0x0004 /* MRL Sensor Changed */
|
||||
#define PCI_EXP_SLTSTA_PDC 0x0008 /* Presence Detect Changed */
|
||||
#define PCI_EXP_SLTSTA_CC 0x0010 /* Command Completed */
|
||||
#define PCI_EXP_SLTSTA_MRLSS 0x0020 /* MRL Sensor State */
|
||||
#define PCI_EXP_SLTSTA_PDS 0x0040 /* Presence Detect State */
|
||||
#define PCI_EXP_SLTSTA_EIS 0x0080 /* Electromechanical Interlock Status */
|
||||
#define PCI_EXP_SLTSTA_DLLSC 0x0100 /* Data Link Layer State Changed */
|
||||
#define PCI_EXP_RTCTL 28 /* Root Control */
|
||||
#define PCI_EXP_RTCTL_SECEE 0x01 /* System Error on Correctable Error */
|
||||
#define PCI_EXP_RTCTL_SENFEE 0x02 /* System Error on Non-Fatal Error */
|
||||
#define PCI_EXP_RTCTL_SEFEE 0x04 /* System Error on Fatal Error */
|
||||
#define PCI_EXP_RTCTL_PMEIE 0x08 /* PME Interrupt Enable */
|
||||
#define PCI_EXP_RTCTL_CRSSVE 0x10 /* CRS Software Visibility Enable */
|
||||
#define PCI_EXP_RTCAP 30 /* Root Capabilities */
|
||||
#define PCI_EXP_RTSTA 32 /* Root Status */
|
||||
#define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */
|
||||
#define PCI_EXP_DEVCAP2_ARI 0x20 /* Alternative Routing-ID */
|
||||
#define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
|
||||
#define PCI_EXP_DEVCTL2_ARI 0x20 /* Alternative Routing-ID */
|
||||
#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
|
||||
#define PCI_EXP_SLTCTL2 56 /* Slot Control 2 */
|
||||
|
||||
/* Extended Capabilities (PCI-X 2.0 and Express) */
|
||||
#define PCI_EXT_CAP_ID(header) (header & 0x0000ffff)
|
||||
#define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf)
|
||||
#define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
|
||||
|
||||
#define PCI_EXT_CAP_ID_ERR 1
|
||||
#define PCI_EXT_CAP_ID_VC 2
|
||||
#define PCI_EXT_CAP_ID_DSN 3
|
||||
#define PCI_EXT_CAP_ID_PWR 4
|
||||
#define PCI_EXT_CAP_ID_VNDR 11
|
||||
#define PCI_EXT_CAP_ID_ACS 13
|
||||
#define PCI_EXT_CAP_ID_ARI 14
|
||||
#define PCI_EXT_CAP_ID_ATS 15
|
||||
#define PCI_EXT_CAP_ID_SRIOV 16
|
||||
|
||||
/* Advanced Error Reporting */
|
||||
#define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */
|
||||
#define PCI_ERR_UNC_TRAIN 0x00000001 /* Training */
|
||||
#define PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */
|
||||
#define PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */
|
||||
#define PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */
|
||||
#define PCI_ERR_UNC_COMP_TIME 0x00004000 /* Completion Timeout */
|
||||
#define PCI_ERR_UNC_COMP_ABORT 0x00008000 /* Completer Abort */
|
||||
#define PCI_ERR_UNC_UNX_COMP 0x00010000 /* Unexpected Completion */
|
||||
#define PCI_ERR_UNC_RX_OVER 0x00020000 /* Receiver Overflow */
|
||||
#define PCI_ERR_UNC_MALF_TLP 0x00040000 /* Malformed TLP */
|
||||
#define PCI_ERR_UNC_ECRC 0x00080000 /* ECRC Error Status */
|
||||
#define PCI_ERR_UNC_UNSUP 0x00100000 /* Unsupported Request */
|
||||
#define PCI_ERR_UNCOR_MASK 8 /* Uncorrectable Error Mask */
|
||||
/* Same bits as above */
|
||||
#define PCI_ERR_UNCOR_SEVER 12 /* Uncorrectable Error Severity */
|
||||
/* Same bits as above */
|
||||
#define PCI_ERR_COR_STATUS 16 /* Correctable Error Status */
|
||||
#define PCI_ERR_COR_RCVR 0x00000001 /* Receiver Error Status */
|
||||
#define PCI_ERR_COR_BAD_TLP 0x00000040 /* Bad TLP Status */
|
||||
#define PCI_ERR_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */
|
||||
#define PCI_ERR_COR_REP_ROLL 0x00000100 /* REPLAY_NUM Rollover */
|
||||
#define PCI_ERR_COR_REP_TIMER 0x00001000 /* Replay Timer Timeout */
|
||||
#define PCI_ERR_COR_MASK 20 /* Correctable Error Mask */
|
||||
/* Same bits as above */
|
||||
#define PCI_ERR_CAP 24 /* Advanced Error Capabilities */
|
||||
#define PCI_ERR_CAP_FEP(x) ((x) & 31) /* First Error Pointer */
|
||||
#define PCI_ERR_CAP_ECRC_GENC 0x00000020 /* ECRC Generation Capable */
|
||||
#define PCI_ERR_CAP_ECRC_GENE 0x00000040 /* ECRC Generation Enable */
|
||||
#define PCI_ERR_CAP_ECRC_CHKC 0x00000080 /* ECRC Check Capable */
|
||||
#define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */
|
||||
#define PCI_ERR_HEADER_LOG 28 /* Header Log Register (16 bytes) */
|
||||
#define PCI_ERR_ROOT_COMMAND 44 /* Root Error Command */
|
||||
/* Correctable Err Reporting Enable */
|
||||
#define PCI_ERR_ROOT_CMD_COR_EN 0x00000001
|
||||
/* Non-fatal Err Reporting Enable */
|
||||
#define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002
|
||||
/* Fatal Err Reporting Enable */
|
||||
#define PCI_ERR_ROOT_CMD_FATAL_EN 0x00000004
|
||||
#define PCI_ERR_ROOT_STATUS 48
|
||||
#define PCI_ERR_ROOT_COR_RCV 0x00000001 /* ERR_COR Received */
|
||||
/* Multi ERR_COR Received */
|
||||
#define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002
|
||||
/* ERR_FATAL/NONFATAL Recevied */
|
||||
#define PCI_ERR_ROOT_UNCOR_RCV 0x00000004
|
||||
/* Multi ERR_FATAL/NONFATAL Recevied */
|
||||
#define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008
|
||||
#define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 /* First Fatal */
|
||||
#define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Received */
|
||||
#define PCI_ERR_ROOT_FATAL_RCV 0x00000040 /* Fatal Received */
|
||||
#define PCI_ERR_ROOT_ERR_SRC 52 /* Error Source Identification */
|
||||
|
||||
/* Virtual Channel */
|
||||
#define PCI_VC_PORT_REG1 4
|
||||
#define PCI_VC_PORT_REG2 8
|
||||
#define PCI_VC_PORT_CTRL 12
|
||||
#define PCI_VC_PORT_STATUS 14
|
||||
#define PCI_VC_RES_CAP 16
|
||||
#define PCI_VC_RES_CTRL 20
|
||||
#define PCI_VC_RES_STATUS 26
|
||||
|
||||
/* Power Budgeting */
|
||||
#define PCI_PWR_DSR 4 /* Data Select Register */
|
||||
#define PCI_PWR_DATA 8 /* Data Register */
|
||||
#define PCI_PWR_DATA_BASE(x) ((x) & 0xff) /* Base Power */
|
||||
#define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale */
|
||||
#define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) /* PM Sub State */
|
||||
#define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */
|
||||
#define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) /* Type */
|
||||
#define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */
|
||||
#define PCI_PWR_CAP 12 /* Capability */
|
||||
#define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */
|
||||
|
||||
/*
|
||||
* Hypertransport sub capability types
|
||||
*
|
||||
* Unfortunately there are both 3 bit and 5 bit capability types defined
|
||||
* in the HT spec, catering for that is a little messy. You probably don't
|
||||
* want to use these directly, just use pci_find_ht_capability() and it
|
||||
* will do the right thing for you.
|
||||
*/
|
||||
#define HT_3BIT_CAP_MASK 0xE0
|
||||
#define HT_CAPTYPE_SLAVE 0x00 /* Slave/Primary link configuration */
|
||||
#define HT_CAPTYPE_HOST 0x20 /* Host/Secondary link configuration */
|
||||
|
||||
#define HT_5BIT_CAP_MASK 0xF8
|
||||
#define HT_CAPTYPE_IRQ 0x80 /* IRQ Configuration */
|
||||
#define HT_CAPTYPE_REMAPPING_40 0xA0 /* 40 bit address remapping */
|
||||
#define HT_CAPTYPE_REMAPPING_64 0xA2 /* 64 bit address remapping */
|
||||
#define HT_CAPTYPE_UNITID_CLUMP 0x90 /* Unit ID clumping */
|
||||
#define HT_CAPTYPE_EXTCONF 0x98 /* Extended Configuration Space Access */
|
||||
#define HT_CAPTYPE_MSI_MAPPING 0xA8 /* MSI Mapping Capability */
|
||||
#define HT_MSI_FLAGS 0x02 /* Offset to flags */
|
||||
#define HT_MSI_FLAGS_ENABLE 0x1 /* Mapping enable */
|
||||
#define HT_MSI_FLAGS_FIXED 0x2 /* Fixed mapping only */
|
||||
#define HT_MSI_FIXED_ADDR 0x00000000FEE00000ULL /* Fixed addr */
|
||||
#define HT_MSI_ADDR_LO 0x04 /* Offset to low addr bits */
|
||||
#define HT_MSI_ADDR_LO_MASK 0xFFF00000 /* Low address bit mask */
|
||||
#define HT_MSI_ADDR_HI 0x08 /* Offset to high addr bits */
|
||||
#define HT_CAPTYPE_DIRECT_ROUTE 0xB0 /* Direct routing configuration */
|
||||
#define HT_CAPTYPE_VCSET 0xB8 /* Virtual Channel configuration */
|
||||
#define HT_CAPTYPE_ERROR_RETRY 0xC0 /* Retry on error configuration */
|
||||
#define HT_CAPTYPE_GEN3 0xD0 /* Generation 3 hypertransport configuration */
|
||||
#define HT_CAPTYPE_PM 0xE0 /* Hypertransport powermanagement configuration */
|
||||
|
||||
/* Alternative Routing-ID Interpretation */
|
||||
#define PCI_ARI_CAP 0x04 /* ARI Capability Register */
|
||||
#define PCI_ARI_CAP_MFVC 0x0001 /* MFVC Function Groups Capability */
|
||||
#define PCI_ARI_CAP_ACS 0x0002 /* ACS Function Groups Capability */
|
||||
#define PCI_ARI_CAP_NFN(x) (((x) >> 8) & 0xff) /* Next Function Number */
|
||||
#define PCI_ARI_CTRL 0x06 /* ARI Control Register */
|
||||
#define PCI_ARI_CTRL_MFVC 0x0001 /* MFVC Function Groups Enable */
|
||||
#define PCI_ARI_CTRL_ACS 0x0002 /* ACS Function Groups Enable */
|
||||
#define PCI_ARI_CTRL_FG(x) (((x) >> 4) & 7) /* Function Group */
|
||||
|
||||
/* Address Translation Service */
|
||||
#define PCI_ATS_CAP 0x04 /* ATS Capability Register */
|
||||
#define PCI_ATS_CAP_QDEP(x) ((x) & 0x1f) /* Invalidate Queue Depth */
|
||||
#define PCI_ATS_MAX_QDEP 32 /* Max Invalidate Queue Depth */
|
||||
#define PCI_ATS_CTRL 0x06 /* ATS Control Register */
|
||||
#define PCI_ATS_CTRL_ENABLE 0x8000 /* ATS Enable */
|
||||
#define PCI_ATS_CTRL_STU(x) ((x) & 0x1f) /* Smallest Translation Unit */
|
||||
#define PCI_ATS_MIN_STU 12 /* shift of minimum STU block */
|
||||
|
||||
/* Single Root I/O Virtualization */
|
||||
#define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */
|
||||
#define PCI_SRIOV_CAP_VFM 0x01 /* VF Migration Capable */
|
||||
#define PCI_SRIOV_CAP_INTR(x) ((x) >> 21) /* Interrupt Message Number */
|
||||
#define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */
|
||||
#define PCI_SRIOV_CTRL_VFE 0x01 /* VF Enable */
|
||||
#define PCI_SRIOV_CTRL_VFM 0x02 /* VF Migration Enable */
|
||||
#define PCI_SRIOV_CTRL_INTR 0x04 /* VF Migration Interrupt Enable */
|
||||
#define PCI_SRIOV_CTRL_MSE 0x08 /* VF Memory Space Enable */
|
||||
#define PCI_SRIOV_CTRL_ARI 0x10 /* ARI Capable Hierarchy */
|
||||
#define PCI_SRIOV_STATUS 0x0a /* SR-IOV Status */
|
||||
#define PCI_SRIOV_STATUS_VFM 0x01 /* VF Migration Status */
|
||||
#define PCI_SRIOV_INITIAL_VF 0x0c /* Initial VFs */
|
||||
#define PCI_SRIOV_TOTAL_VF 0x0e /* Total VFs */
|
||||
#define PCI_SRIOV_NUM_VF 0x10 /* Number of VFs */
|
||||
#define PCI_SRIOV_FUNC_LINK 0x12 /* Function Dependency Link */
|
||||
#define PCI_SRIOV_VF_OFFSET 0x14 /* First VF Offset */
|
||||
#define PCI_SRIOV_VF_STRIDE 0x16 /* Following VF Stride */
|
||||
#define PCI_SRIOV_VF_DID 0x1a /* VF Device ID */
|
||||
#define PCI_SRIOV_SUP_PGSIZE 0x1c /* Supported Page Sizes */
|
||||
#define PCI_SRIOV_SYS_PGSIZE 0x20 /* System Page Size */
|
||||
#define PCI_SRIOV_BAR 0x24 /* VF BAR0 */
|
||||
#define PCI_SRIOV_NUM_BARS 6 /* Number of VF BARs */
|
||||
#define PCI_SRIOV_VFM 0x3c /* VF Migration State Array Offset*/
|
||||
#define PCI_SRIOV_VFM_BIR(x) ((x) & 7) /* State BIR */
|
||||
#define PCI_SRIOV_VFM_OFFSET(x) ((x) & ~7) /* State Offset */
|
||||
#define PCI_SRIOV_VFM_UA 0x0 /* Inactive.Unavailable */
|
||||
#define PCI_SRIOV_VFM_MI 0x1 /* Dormant.MigrateIn */
|
||||
#define PCI_SRIOV_VFM_MO 0x2 /* Active.MigrateOut */
|
||||
#define PCI_SRIOV_VFM_AV 0x3 /* Active.Available */
|
||||
|
||||
/* Access Control Service */
|
||||
#define PCI_ACS_CAP 0x04 /* ACS Capability Register */
|
||||
#define PCI_ACS_SV 0x01 /* Source Validation */
|
||||
#define PCI_ACS_TB 0x02 /* Translation Blocking */
|
||||
#define PCI_ACS_RR 0x04 /* P2P Request Redirect */
|
||||
#define PCI_ACS_CR 0x08 /* P2P Completion Redirect */
|
||||
#define PCI_ACS_UF 0x10 /* Upstream Forwarding */
|
||||
#define PCI_ACS_EC 0x20 /* P2P Egress Control */
|
||||
#define PCI_ACS_DT 0x40 /* Direct Translated P2P */
|
||||
#define PCI_ACS_CTRL 0x06 /* ACS Control Register */
|
||||
#define PCI_ACS_EGRESS_CTL_V 0x08 /* ACS Egress Control Vector */
|
||||
|
||||
#endif /* LINUX_PCI_REGS_H */
|
||||
@@ -1,97 +0,0 @@
|
||||
#ifndef _LINUX_VIRTIO_BLK_H
|
||||
#define _LINUX_VIRTIO_BLK_H
|
||||
|
||||
#include <inttypes.h>
|
||||
|
||||
/* Feature bits */
|
||||
#define VIRTIO_BLK_F_BARRIER 0 /* Does host support barriers? */
|
||||
#define VIRTIO_BLK_F_SIZE_MAX 1 /* Indicates maximum segment size */
|
||||
#define VIRTIO_BLK_F_SEG_MAX 2 /* Indicates maximum # of segments */
|
||||
#define VIRTIO_BLK_F_GEOMETRY 4 /* Legacy geometry available */
|
||||
#define VIRTIO_BLK_F_RO 5 /* Disk is read-only */
|
||||
#define VIRTIO_BLK_F_BLK_SIZE 6 /* Block size of disk is available*/
|
||||
#define VIRTIO_BLK_F_SCSI 7 /* Supports scsi command passthru */
|
||||
#define VIRTIO_BLK_F_FLUSH 9 /* Cache flush command support */
|
||||
#define VIRTIO_BLK_F_TOPOLOGY 10 /* Topology information is available */
|
||||
|
||||
#define VIRTIO_BLK_ID_BYTES 20 /* ID string length */
|
||||
|
||||
struct virtio_blk_config {
|
||||
/* The capacity (in 512-byte sectors). */
|
||||
uint64_t capacity;
|
||||
/* The maximum segment size (if VIRTIO_BLK_F_SIZE_MAX) */
|
||||
uint32_t size_max;
|
||||
/* The maximum number of segments (if VIRTIO_BLK_F_SEG_MAX) */
|
||||
uint32_t seg_max;
|
||||
/* geometry the device (if VIRTIO_BLK_F_GEOMETRY) */
|
||||
struct virtio_blk_geometry {
|
||||
uint16_t cylinders;
|
||||
uint8_t heads;
|
||||
uint8_t sectors;
|
||||
} geometry;
|
||||
|
||||
/* block size of device (if VIRTIO_BLK_F_BLK_SIZE) */
|
||||
uint32_t blk_size;
|
||||
|
||||
/* the next 4 entries are guarded by VIRTIO_BLK_F_TOPOLOGY */
|
||||
/* exponent for physical block per logical block. */
|
||||
uint8_t physical_block_exp;
|
||||
/* alignment offset in logical blocks. */
|
||||
uint8_t alignment_offset;
|
||||
/* minimum I/O size without performance penalty in logical blocks. */
|
||||
uint16_t min_io_size;
|
||||
/* optimal sustained I/O size in logical blocks. */
|
||||
uint32_t opt_io_size;
|
||||
|
||||
} __attribute__((packed));
|
||||
|
||||
/*
|
||||
* Command types
|
||||
*
|
||||
* Usage is a bit tricky as some bits are used as flags and some are not.
|
||||
*
|
||||
* Rules:
|
||||
* VIRTIO_BLK_T_OUT may be combined with VIRTIO_BLK_T_SCSI_CMD or
|
||||
* VIRTIO_BLK_T_BARRIER. VIRTIO_BLK_T_FLUSH is a command of its own
|
||||
* and may not be combined with any of the other flags.
|
||||
*/
|
||||
|
||||
/* These two define direction. */
|
||||
#define VIRTIO_BLK_T_IN 0
|
||||
#define VIRTIO_BLK_T_OUT 1
|
||||
|
||||
/* This bit says it's a scsi command, not an actual read or write. */
|
||||
#define VIRTIO_BLK_T_SCSI_CMD 2
|
||||
|
||||
/* Cache flush command */
|
||||
#define VIRTIO_BLK_T_FLUSH 4
|
||||
|
||||
/* Get device ID command */
|
||||
#define VIRTIO_BLK_T_GET_ID 8
|
||||
|
||||
/* Barrier before this op. */
|
||||
#define VIRTIO_BLK_T_BARRIER 0x80000000
|
||||
|
||||
/* This is the first element of the read scatter-gather list. */
|
||||
struct virtio_blk_outhdr {
|
||||
/* VIRTIO_BLK_T* */
|
||||
uint32_t type;
|
||||
/* io priority. */
|
||||
uint32_t ioprio;
|
||||
/* Sector (ie. 512 byte offset) */
|
||||
uint64_t sector;
|
||||
};
|
||||
|
||||
struct virtio_scsi_inhdr {
|
||||
uint32_t errors;
|
||||
uint32_t data_len;
|
||||
uint32_t sense_len;
|
||||
uint32_t residual;
|
||||
};
|
||||
|
||||
/* And this is the final byte of the write scatter-gather list. */
|
||||
#define VIRTIO_BLK_S_OK 0
|
||||
#define VIRTIO_BLK_S_IOERR 1
|
||||
#define VIRTIO_BLK_S_UNSUPP 2
|
||||
|
||||
#endif /* _LINUX_VIRTIO_BLK_H */
|
||||
@@ -1,107 +0,0 @@
|
||||
/*
|
||||
* Code is taken from include/linux/virtio_ring.h
|
||||
*/
|
||||
|
||||
#ifndef _LINUX_VIRTIO_RING_H
|
||||
#define _LINUX_VIRTIO_RING_H
|
||||
|
||||
#include <inttypes.h>
|
||||
|
||||
/* This marks a buffer as continuing via the next field. */
|
||||
#define VRING_DESC_F_NEXT 1
|
||||
/* This marks a buffer as write-only (otherwise read-only). */
|
||||
#define VRING_DESC_F_WRITE 2
|
||||
/* This means the buffer contains a list of buffer descriptors. */
|
||||
#define VRING_DESC_F_INDIRECT 4
|
||||
|
||||
/* The Host uses this in used->flags to advise the Guest: don't kick me when
|
||||
* you add a buffer. It's unreliable, so it's simply an optimization. Guest
|
||||
* will still kick if it's out of buffers. */
|
||||
#define VRING_USED_F_NO_NOTIFY 1
|
||||
/* The Guest uses this in avail->flags to advise the Host: don't interrupt me
|
||||
* when you consume a buffer. It's unreliable, so it's simply an
|
||||
* optimization. */
|
||||
#define VRING_AVAIL_F_NO_INTERRUPT 1
|
||||
|
||||
/* We support indirect buffer descriptors */
|
||||
#define VIRTIO_RING_F_INDIRECT_DESC 28
|
||||
|
||||
/* Virtio ring descriptors: 16 bytes. These can chain together via "next". */
|
||||
struct vring_desc {
|
||||
/* Address (guest-physical). */
|
||||
uint64_t addr;
|
||||
/* Length. */
|
||||
uint32_t len;
|
||||
/* The flags as indicated above. */
|
||||
uint16_t flags;
|
||||
/* We chain unused descriptors via this, too */
|
||||
uint16_t next;
|
||||
};
|
||||
|
||||
struct vring_avail {
|
||||
uint16_t flags;
|
||||
uint16_t idx;
|
||||
uint16_t ring[];
|
||||
};
|
||||
|
||||
/* uint32_t is used here for ids for padding reasons. */
|
||||
struct vring_used_elem {
|
||||
/* Index of start of used descriptor chain. */
|
||||
uint32_t id;
|
||||
/* Total length of the descriptor chain which was used (written to) */
|
||||
uint32_t len;
|
||||
};
|
||||
|
||||
struct vring_used {
|
||||
uint16_t flags;
|
||||
uint16_t idx;
|
||||
struct vring_used_elem ring[];
|
||||
};
|
||||
|
||||
struct vring {
|
||||
unsigned int num;
|
||||
struct vring_desc *desc;
|
||||
struct vring_avail *avail;
|
||||
struct vring_used *used;
|
||||
};
|
||||
|
||||
/* The standard layout for the ring is a continuous chunk of memory which looks
|
||||
* like this. We assume num is a power of 2.
|
||||
*
|
||||
* struct vring
|
||||
* {
|
||||
* // The actual descriptors (16 bytes each)
|
||||
* struct vring_desc desc[num];
|
||||
*
|
||||
* // A ring of available descriptor heads with free-running index.
|
||||
* uint16_t avail_flags;
|
||||
* uint16_t avail_idx;
|
||||
* uint16_t available[num];
|
||||
*
|
||||
* // Padding to the next align boundary.
|
||||
* char pad[];
|
||||
*
|
||||
* // A ring of used descriptor heads with free-running index.
|
||||
* uint16_t used_flags;
|
||||
* uint16_t used_idx;
|
||||
* struct vring_used_elem used[num];
|
||||
* };
|
||||
*/
|
||||
static inline void vring_init(struct vring *vr, unsigned int num, void *p,
|
||||
unsigned long align)
|
||||
{
|
||||
vr->num = num;
|
||||
vr->desc = p;
|
||||
vr->avail = p + num*sizeof(struct vring_desc);
|
||||
vr->used = (void *)(((unsigned long)&vr->avail->ring[num] + align-1)
|
||||
& ~(align - 1));
|
||||
}
|
||||
|
||||
static inline unsigned vring_size(unsigned int num, unsigned long align)
|
||||
{
|
||||
return ((sizeof(struct vring_desc) * num + sizeof(uint16_t) * (2 + num)
|
||||
+ align - 1) & ~(align - 1)) + sizeof(uint16_t) * 2
|
||||
+ sizeof(struct vring_used_elem) * num;
|
||||
}
|
||||
|
||||
#endif /* _LINUX_VIRTIO_RING_H */
|
||||
@@ -1,6 +0,0 @@
|
||||
#ifndef LINUX_COMPILER_H
|
||||
#define LINUX_COMPILER_H
|
||||
|
||||
#define __user
|
||||
|
||||
#endif /* LINUX_COMPILER_H */
|
||||
@@ -1,785 +0,0 @@
|
||||
#ifndef __LINUX_KVM_H
|
||||
#define __LINUX_KVM_H
|
||||
|
||||
/*
|
||||
* Userspace interface for /dev/kvm - kernel based virtual machine
|
||||
*
|
||||
* Note: you must update KVM_API_VERSION if you change this interface.
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/compiler.h>
|
||||
#include <linux/ioctl.h>
|
||||
#include <asm/kvm.h>
|
||||
|
||||
#define KVM_API_VERSION 12
|
||||
|
||||
/* *** Deprecated interfaces *** */
|
||||
|
||||
#define KVM_TRC_SHIFT 16
|
||||
|
||||
#define KVM_TRC_ENTRYEXIT (1 << KVM_TRC_SHIFT)
|
||||
#define KVM_TRC_HANDLER (1 << (KVM_TRC_SHIFT + 1))
|
||||
|
||||
#define KVM_TRC_VMENTRY (KVM_TRC_ENTRYEXIT + 0x01)
|
||||
#define KVM_TRC_VMEXIT (KVM_TRC_ENTRYEXIT + 0x02)
|
||||
#define KVM_TRC_PAGE_FAULT (KVM_TRC_HANDLER + 0x01)
|
||||
|
||||
#define KVM_TRC_HEAD_SIZE 12
|
||||
#define KVM_TRC_CYCLE_SIZE 8
|
||||
#define KVM_TRC_EXTRA_MAX 7
|
||||
|
||||
#define KVM_TRC_INJ_VIRQ (KVM_TRC_HANDLER + 0x02)
|
||||
#define KVM_TRC_REDELIVER_EVT (KVM_TRC_HANDLER + 0x03)
|
||||
#define KVM_TRC_PEND_INTR (KVM_TRC_HANDLER + 0x04)
|
||||
#define KVM_TRC_IO_READ (KVM_TRC_HANDLER + 0x05)
|
||||
#define KVM_TRC_IO_WRITE (KVM_TRC_HANDLER + 0x06)
|
||||
#define KVM_TRC_CR_READ (KVM_TRC_HANDLER + 0x07)
|
||||
#define KVM_TRC_CR_WRITE (KVM_TRC_HANDLER + 0x08)
|
||||
#define KVM_TRC_DR_READ (KVM_TRC_HANDLER + 0x09)
|
||||
#define KVM_TRC_DR_WRITE (KVM_TRC_HANDLER + 0x0A)
|
||||
#define KVM_TRC_MSR_READ (KVM_TRC_HANDLER + 0x0B)
|
||||
#define KVM_TRC_MSR_WRITE (KVM_TRC_HANDLER + 0x0C)
|
||||
#define KVM_TRC_CPUID (KVM_TRC_HANDLER + 0x0D)
|
||||
#define KVM_TRC_INTR (KVM_TRC_HANDLER + 0x0E)
|
||||
#define KVM_TRC_NMI (KVM_TRC_HANDLER + 0x0F)
|
||||
#define KVM_TRC_VMMCALL (KVM_TRC_HANDLER + 0x10)
|
||||
#define KVM_TRC_HLT (KVM_TRC_HANDLER + 0x11)
|
||||
#define KVM_TRC_CLTS (KVM_TRC_HANDLER + 0x12)
|
||||
#define KVM_TRC_LMSW (KVM_TRC_HANDLER + 0x13)
|
||||
#define KVM_TRC_APIC_ACCESS (KVM_TRC_HANDLER + 0x14)
|
||||
#define KVM_TRC_TDP_FAULT (KVM_TRC_HANDLER + 0x15)
|
||||
#define KVM_TRC_GTLB_WRITE (KVM_TRC_HANDLER + 0x16)
|
||||
#define KVM_TRC_STLB_WRITE (KVM_TRC_HANDLER + 0x17)
|
||||
#define KVM_TRC_STLB_INVAL (KVM_TRC_HANDLER + 0x18)
|
||||
#define KVM_TRC_PPC_INSTR (KVM_TRC_HANDLER + 0x19)
|
||||
|
||||
struct kvm_user_trace_setup {
|
||||
__u32 buf_size;
|
||||
__u32 buf_nr;
|
||||
};
|
||||
|
||||
#define __KVM_DEPRECATED_MAIN_W_0x06 \
|
||||
_IOW(KVMIO, 0x06, struct kvm_user_trace_setup)
|
||||
#define __KVM_DEPRECATED_MAIN_0x07 _IO(KVMIO, 0x07)
|
||||
#define __KVM_DEPRECATED_MAIN_0x08 _IO(KVMIO, 0x08)
|
||||
|
||||
#define __KVM_DEPRECATED_VM_R_0x70 _IOR(KVMIO, 0x70, struct kvm_assigned_irq)
|
||||
|
||||
struct kvm_breakpoint {
|
||||
__u32 enabled;
|
||||
__u32 padding;
|
||||
__u64 address;
|
||||
};
|
||||
|
||||
struct kvm_debug_guest {
|
||||
__u32 enabled;
|
||||
__u32 pad;
|
||||
struct kvm_breakpoint breakpoints[4];
|
||||
__u32 singlestep;
|
||||
};
|
||||
|
||||
#define __KVM_DEPRECATED_VCPU_W_0x87 _IOW(KVMIO, 0x87, struct kvm_debug_guest)
|
||||
|
||||
/* *** End of deprecated interfaces *** */
|
||||
|
||||
|
||||
/* for KVM_CREATE_MEMORY_REGION */
|
||||
struct kvm_memory_region {
|
||||
__u32 slot;
|
||||
__u32 flags;
|
||||
__u64 guest_phys_addr;
|
||||
__u64 memory_size; /* bytes */
|
||||
};
|
||||
|
||||
/* for KVM_SET_USER_MEMORY_REGION */
|
||||
struct kvm_userspace_memory_region {
|
||||
__u32 slot;
|
||||
__u32 flags;
|
||||
__u64 guest_phys_addr;
|
||||
__u64 memory_size; /* bytes */
|
||||
__u64 userspace_addr; /* start of the userspace allocated memory */
|
||||
};
|
||||
|
||||
/* for kvm_memory_region::flags */
|
||||
#define KVM_MEM_LOG_DIRTY_PAGES 1UL
|
||||
#define KVM_MEMSLOT_INVALID (1UL << 1)
|
||||
|
||||
/* for KVM_IRQ_LINE */
|
||||
struct kvm_irq_level {
|
||||
/*
|
||||
* ACPI gsi notion of irq.
|
||||
* For IA-64 (APIC model) IOAPIC0: irq 0-23; IOAPIC1: irq 24-47..
|
||||
* For X86 (standard AT mode) PIC0/1: irq 0-15. IOAPIC0: 0-23..
|
||||
*/
|
||||
union {
|
||||
__u32 irq;
|
||||
__s32 status;
|
||||
};
|
||||
__u32 level;
|
||||
};
|
||||
|
||||
|
||||
struct kvm_irqchip {
|
||||
__u32 chip_id;
|
||||
__u32 pad;
|
||||
union {
|
||||
char dummy[512]; /* reserving space */
|
||||
#ifdef __KVM_HAVE_PIT
|
||||
struct kvm_pic_state pic;
|
||||
#endif
|
||||
#ifdef __KVM_HAVE_IOAPIC
|
||||
struct kvm_ioapic_state ioapic;
|
||||
#endif
|
||||
} chip;
|
||||
};
|
||||
|
||||
/* for KVM_CREATE_PIT2 */
|
||||
struct kvm_pit_config {
|
||||
__u32 flags;
|
||||
__u32 pad[15];
|
||||
};
|
||||
|
||||
#define KVM_PIT_SPEAKER_DUMMY 1
|
||||
|
||||
#define KVM_EXIT_UNKNOWN 0
|
||||
#define KVM_EXIT_EXCEPTION 1
|
||||
#define KVM_EXIT_IO 2
|
||||
#define KVM_EXIT_HYPERCALL 3
|
||||
#define KVM_EXIT_DEBUG 4
|
||||
#define KVM_EXIT_HLT 5
|
||||
#define KVM_EXIT_MMIO 6
|
||||
#define KVM_EXIT_IRQ_WINDOW_OPEN 7
|
||||
#define KVM_EXIT_SHUTDOWN 8
|
||||
#define KVM_EXIT_FAIL_ENTRY 9
|
||||
#define KVM_EXIT_INTR 10
|
||||
#define KVM_EXIT_SET_TPR 11
|
||||
#define KVM_EXIT_TPR_ACCESS 12
|
||||
#define KVM_EXIT_S390_SIEIC 13
|
||||
#define KVM_EXIT_S390_RESET 14
|
||||
#define KVM_EXIT_DCR 15
|
||||
#define KVM_EXIT_NMI 16
|
||||
#define KVM_EXIT_INTERNAL_ERROR 17
|
||||
#define KVM_EXIT_OSI 18
|
||||
|
||||
/* For KVM_EXIT_INTERNAL_ERROR */
|
||||
#define KVM_INTERNAL_ERROR_EMULATION 1
|
||||
#define KVM_INTERNAL_ERROR_SIMUL_EX 2
|
||||
|
||||
/* for KVM_RUN, returned by mmap(vcpu_fd, offset=0) */
|
||||
struct kvm_run {
|
||||
/* in */
|
||||
__u8 request_interrupt_window;
|
||||
__u8 padding1[7];
|
||||
|
||||
/* out */
|
||||
__u32 exit_reason;
|
||||
__u8 ready_for_interrupt_injection;
|
||||
__u8 if_flag;
|
||||
__u8 padding2[2];
|
||||
|
||||
/* in (pre_kvm_run), out (post_kvm_run) */
|
||||
__u64 cr8;
|
||||
__u64 apic_base;
|
||||
|
||||
#ifdef __KVM_S390
|
||||
/* the processor status word for s390 */
|
||||
__u64 psw_mask; /* psw upper half */
|
||||
__u64 psw_addr; /* psw lower half */
|
||||
#endif
|
||||
union {
|
||||
/* KVM_EXIT_UNKNOWN */
|
||||
struct {
|
||||
__u64 hardware_exit_reason;
|
||||
} hw;
|
||||
/* KVM_EXIT_FAIL_ENTRY */
|
||||
struct {
|
||||
__u64 hardware_entry_failure_reason;
|
||||
} fail_entry;
|
||||
/* KVM_EXIT_EXCEPTION */
|
||||
struct {
|
||||
__u32 exception;
|
||||
__u32 error_code;
|
||||
} ex;
|
||||
/* KVM_EXIT_IO */
|
||||
struct {
|
||||
#define KVM_EXIT_IO_IN 0
|
||||
#define KVM_EXIT_IO_OUT 1
|
||||
__u8 direction;
|
||||
__u8 size; /* bytes */
|
||||
__u16 port;
|
||||
__u32 count;
|
||||
__u64 data_offset; /* relative to kvm_run start */
|
||||
} io;
|
||||
struct {
|
||||
struct kvm_debug_exit_arch arch;
|
||||
} debug;
|
||||
/* KVM_EXIT_MMIO */
|
||||
struct {
|
||||
__u64 phys_addr;
|
||||
__u8 data[8];
|
||||
__u32 len;
|
||||
__u8 is_write;
|
||||
} mmio;
|
||||
/* KVM_EXIT_HYPERCALL */
|
||||
struct {
|
||||
__u64 nr;
|
||||
__u64 args[6];
|
||||
__u64 ret;
|
||||
__u32 longmode;
|
||||
__u32 pad;
|
||||
} hypercall;
|
||||
/* KVM_EXIT_TPR_ACCESS */
|
||||
struct {
|
||||
__u64 rip;
|
||||
__u32 is_write;
|
||||
__u32 pad;
|
||||
} tpr_access;
|
||||
/* KVM_EXIT_S390_SIEIC */
|
||||
struct {
|
||||
__u8 icptcode;
|
||||
__u16 ipa;
|
||||
__u32 ipb;
|
||||
} s390_sieic;
|
||||
/* KVM_EXIT_S390_RESET */
|
||||
#define KVM_S390_RESET_POR 1
|
||||
#define KVM_S390_RESET_CLEAR 2
|
||||
#define KVM_S390_RESET_SUBSYSTEM 4
|
||||
#define KVM_S390_RESET_CPU_INIT 8
|
||||
#define KVM_S390_RESET_IPL 16
|
||||
__u64 s390_reset_flags;
|
||||
/* KVM_EXIT_DCR */
|
||||
struct {
|
||||
__u32 dcrn;
|
||||
__u32 data;
|
||||
__u8 is_write;
|
||||
} dcr;
|
||||
struct {
|
||||
__u32 suberror;
|
||||
/* Available with KVM_CAP_INTERNAL_ERROR_DATA: */
|
||||
__u32 ndata;
|
||||
__u64 data[16];
|
||||
} internal;
|
||||
/* KVM_EXIT_OSI */
|
||||
struct {
|
||||
__u64 gprs[32];
|
||||
} osi;
|
||||
/* Fix the size of the union. */
|
||||
char padding[256];
|
||||
};
|
||||
};
|
||||
|
||||
/* for KVM_REGISTER_COALESCED_MMIO / KVM_UNREGISTER_COALESCED_MMIO */
|
||||
|
||||
struct kvm_coalesced_mmio_zone {
|
||||
__u64 addr;
|
||||
__u32 size;
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
struct kvm_coalesced_mmio {
|
||||
__u64 phys_addr;
|
||||
__u32 len;
|
||||
__u32 pad;
|
||||
__u8 data[8];
|
||||
};
|
||||
|
||||
struct kvm_coalesced_mmio_ring {
|
||||
__u32 first, last;
|
||||
struct kvm_coalesced_mmio coalesced_mmio[0];
|
||||
};
|
||||
|
||||
#define KVM_COALESCED_MMIO_MAX \
|
||||
((PAGE_SIZE - sizeof(struct kvm_coalesced_mmio_ring)) / \
|
||||
sizeof(struct kvm_coalesced_mmio))
|
||||
|
||||
/* for KVM_TRANSLATE */
|
||||
struct kvm_translation {
|
||||
/* in */
|
||||
__u64 linear_address;
|
||||
|
||||
/* out */
|
||||
__u64 physical_address;
|
||||
__u8 valid;
|
||||
__u8 writeable;
|
||||
__u8 usermode;
|
||||
__u8 pad[5];
|
||||
};
|
||||
|
||||
/* for KVM_INTERRUPT */
|
||||
struct kvm_interrupt {
|
||||
/* in */
|
||||
__u32 irq;
|
||||
};
|
||||
|
||||
/* for KVM_GET_DIRTY_LOG */
|
||||
struct kvm_dirty_log {
|
||||
__u32 slot;
|
||||
__u32 padding1;
|
||||
union {
|
||||
void __user *dirty_bitmap; /* one bit per page */
|
||||
__u64 padding2;
|
||||
};
|
||||
};
|
||||
|
||||
/* for KVM_SET_SIGNAL_MASK */
|
||||
struct kvm_signal_mask {
|
||||
__u32 len;
|
||||
__u8 sigset[0];
|
||||
};
|
||||
|
||||
/* for KVM_TPR_ACCESS_REPORTING */
|
||||
struct kvm_tpr_access_ctl {
|
||||
__u32 enabled;
|
||||
__u32 flags;
|
||||
__u32 reserved[8];
|
||||
};
|
||||
|
||||
/* for KVM_SET_VAPIC_ADDR */
|
||||
struct kvm_vapic_addr {
|
||||
__u64 vapic_addr;
|
||||
};
|
||||
|
||||
/* for KVM_SET_MPSTATE */
|
||||
|
||||
#define KVM_MP_STATE_RUNNABLE 0
|
||||
#define KVM_MP_STATE_UNINITIALIZED 1
|
||||
#define KVM_MP_STATE_INIT_RECEIVED 2
|
||||
#define KVM_MP_STATE_HALTED 3
|
||||
#define KVM_MP_STATE_SIPI_RECEIVED 4
|
||||
|
||||
struct kvm_mp_state {
|
||||
__u32 mp_state;
|
||||
};
|
||||
|
||||
struct kvm_s390_psw {
|
||||
__u64 mask;
|
||||
__u64 addr;
|
||||
};
|
||||
|
||||
/* valid values for type in kvm_s390_interrupt */
|
||||
#define KVM_S390_SIGP_STOP 0xfffe0000u
|
||||
#define KVM_S390_PROGRAM_INT 0xfffe0001u
|
||||
#define KVM_S390_SIGP_SET_PREFIX 0xfffe0002u
|
||||
#define KVM_S390_RESTART 0xfffe0003u
|
||||
#define KVM_S390_INT_VIRTIO 0xffff2603u
|
||||
#define KVM_S390_INT_SERVICE 0xffff2401u
|
||||
#define KVM_S390_INT_EMERGENCY 0xffff1201u
|
||||
|
||||
struct kvm_s390_interrupt {
|
||||
__u32 type;
|
||||
__u32 parm;
|
||||
__u64 parm64;
|
||||
};
|
||||
|
||||
/* for KVM_SET_GUEST_DEBUG */
|
||||
|
||||
#define KVM_GUESTDBG_ENABLE 0x00000001
|
||||
#define KVM_GUESTDBG_SINGLESTEP 0x00000002
|
||||
|
||||
struct kvm_guest_debug {
|
||||
__u32 control;
|
||||
__u32 pad;
|
||||
struct kvm_guest_debug_arch arch;
|
||||
};
|
||||
|
||||
enum {
|
||||
kvm_ioeventfd_flag_nr_datamatch,
|
||||
kvm_ioeventfd_flag_nr_pio,
|
||||
kvm_ioeventfd_flag_nr_deassign,
|
||||
kvm_ioeventfd_flag_nr_max,
|
||||
};
|
||||
|
||||
#define KVM_IOEVENTFD_FLAG_DATAMATCH (1 << kvm_ioeventfd_flag_nr_datamatch)
|
||||
#define KVM_IOEVENTFD_FLAG_PIO (1 << kvm_ioeventfd_flag_nr_pio)
|
||||
#define KVM_IOEVENTFD_FLAG_DEASSIGN (1 << kvm_ioeventfd_flag_nr_deassign)
|
||||
|
||||
#define KVM_IOEVENTFD_VALID_FLAG_MASK ((1 << kvm_ioeventfd_flag_nr_max) - 1)
|
||||
|
||||
struct kvm_ioeventfd {
|
||||
__u64 datamatch;
|
||||
__u64 addr; /* legal pio/mmio address */
|
||||
__u32 len; /* 1, 2, 4, or 8 bytes */
|
||||
__s32 fd;
|
||||
__u32 flags;
|
||||
__u8 pad[36];
|
||||
};
|
||||
|
||||
/* for KVM_ENABLE_CAP */
|
||||
struct kvm_enable_cap {
|
||||
/* in */
|
||||
__u32 cap;
|
||||
__u32 flags;
|
||||
__u64 args[4];
|
||||
__u8 pad[64];
|
||||
};
|
||||
|
||||
#define KVMIO 0xAE
|
||||
|
||||
/*
|
||||
* ioctls for /dev/kvm fds:
|
||||
*/
|
||||
#define KVM_GET_API_VERSION _IO(KVMIO, 0x00)
|
||||
#define KVM_CREATE_VM _IO(KVMIO, 0x01) /* returns a VM fd */
|
||||
#define KVM_GET_MSR_INDEX_LIST _IOWR(KVMIO, 0x02, struct kvm_msr_list)
|
||||
|
||||
#define KVM_S390_ENABLE_SIE _IO(KVMIO, 0x06)
|
||||
/*
|
||||
* Check if a kvm extension is available. Argument is extension number,
|
||||
* return is 1 (yes) or 0 (no, sorry).
|
||||
*/
|
||||
#define KVM_CHECK_EXTENSION _IO(KVMIO, 0x03)
|
||||
/*
|
||||
* Get size for mmap(vcpu_fd)
|
||||
*/
|
||||
#define KVM_GET_VCPU_MMAP_SIZE _IO(KVMIO, 0x04) /* in bytes */
|
||||
#define KVM_GET_SUPPORTED_CPUID _IOWR(KVMIO, 0x05, struct kvm_cpuid2)
|
||||
#define KVM_TRACE_ENABLE __KVM_DEPRECATED_MAIN_W_0x06
|
||||
#define KVM_TRACE_PAUSE __KVM_DEPRECATED_MAIN_0x07
|
||||
#define KVM_TRACE_DISABLE __KVM_DEPRECATED_MAIN_0x08
|
||||
|
||||
/*
|
||||
* Extension capability list.
|
||||
*/
|
||||
#define KVM_CAP_IRQCHIP 0
|
||||
#define KVM_CAP_HLT 1
|
||||
#define KVM_CAP_MMU_SHADOW_CACHE_CONTROL 2
|
||||
#define KVM_CAP_USER_MEMORY 3
|
||||
#define KVM_CAP_SET_TSS_ADDR 4
|
||||
#define KVM_CAP_VAPIC 6
|
||||
#define KVM_CAP_EXT_CPUID 7
|
||||
#define KVM_CAP_CLOCKSOURCE 8
|
||||
#define KVM_CAP_NR_VCPUS 9 /* returns max vcpus per vm */
|
||||
#define KVM_CAP_NR_MEMSLOTS 10 /* returns max memory slots per vm */
|
||||
#define KVM_CAP_PIT 11
|
||||
#define KVM_CAP_NOP_IO_DELAY 12
|
||||
#define KVM_CAP_PV_MMU 13
|
||||
#define KVM_CAP_MP_STATE 14
|
||||
#define KVM_CAP_COALESCED_MMIO 15
|
||||
#define KVM_CAP_SYNC_MMU 16 /* Changes to host mmap are reflected in guest */
|
||||
#ifdef __KVM_HAVE_DEVICE_ASSIGNMENT
|
||||
#define KVM_CAP_DEVICE_ASSIGNMENT 17
|
||||
#endif
|
||||
#define KVM_CAP_IOMMU 18
|
||||
#ifdef __KVM_HAVE_MSI
|
||||
#define KVM_CAP_DEVICE_MSI 20
|
||||
#endif
|
||||
/* Bug in KVM_SET_USER_MEMORY_REGION fixed: */
|
||||
#define KVM_CAP_DESTROY_MEMORY_REGION_WORKS 21
|
||||
#ifdef __KVM_HAVE_USER_NMI
|
||||
#define KVM_CAP_USER_NMI 22
|
||||
#endif
|
||||
#ifdef __KVM_HAVE_GUEST_DEBUG
|
||||
#define KVM_CAP_SET_GUEST_DEBUG 23
|
||||
#endif
|
||||
#ifdef __KVM_HAVE_PIT
|
||||
#define KVM_CAP_REINJECT_CONTROL 24
|
||||
#endif
|
||||
#ifdef __KVM_HAVE_IOAPIC
|
||||
#define KVM_CAP_IRQ_ROUTING 25
|
||||
#endif
|
||||
#define KVM_CAP_IRQ_INJECT_STATUS 26
|
||||
#ifdef __KVM_HAVE_DEVICE_ASSIGNMENT
|
||||
#define KVM_CAP_DEVICE_DEASSIGNMENT 27
|
||||
#endif
|
||||
#ifdef __KVM_HAVE_MSIX
|
||||
#define KVM_CAP_DEVICE_MSIX 28
|
||||
#endif
|
||||
#define KVM_CAP_ASSIGN_DEV_IRQ 29
|
||||
/* Another bug in KVM_SET_USER_MEMORY_REGION fixed: */
|
||||
#define KVM_CAP_JOIN_MEMORY_REGIONS_WORKS 30
|
||||
#ifdef __KVM_HAVE_MCE
|
||||
#define KVM_CAP_MCE 31
|
||||
#endif
|
||||
#define KVM_CAP_IRQFD 32
|
||||
#ifdef __KVM_HAVE_PIT
|
||||
#define KVM_CAP_PIT2 33
|
||||
#endif
|
||||
#define KVM_CAP_SET_BOOT_CPU_ID 34
|
||||
#ifdef __KVM_HAVE_PIT_STATE2
|
||||
#define KVM_CAP_PIT_STATE2 35
|
||||
#endif
|
||||
#define KVM_CAP_IOEVENTFD 36
|
||||
#define KVM_CAP_SET_IDENTITY_MAP_ADDR 37
|
||||
#ifdef __KVM_HAVE_XEN_HVM
|
||||
#define KVM_CAP_XEN_HVM 38
|
||||
#endif
|
||||
#define KVM_CAP_ADJUST_CLOCK 39
|
||||
#define KVM_CAP_INTERNAL_ERROR_DATA 40
|
||||
#ifdef __KVM_HAVE_VCPU_EVENTS
|
||||
#define KVM_CAP_VCPU_EVENTS 41
|
||||
#endif
|
||||
#define KVM_CAP_S390_PSW 42
|
||||
#define KVM_CAP_PPC_SEGSTATE 43
|
||||
#define KVM_CAP_HYPERV 44
|
||||
#define KVM_CAP_HYPERV_VAPIC 45
|
||||
#define KVM_CAP_HYPERV_SPIN 46
|
||||
#define KVM_CAP_PCI_SEGMENT 47
|
||||
#define KVM_CAP_PPC_PAIRED_SINGLES 48
|
||||
#define KVM_CAP_INTR_SHADOW 49
|
||||
#ifdef __KVM_HAVE_DEBUGREGS
|
||||
#define KVM_CAP_DEBUGREGS 50
|
||||
#endif
|
||||
#define KVM_CAP_X86_ROBUST_SINGLESTEP 51
|
||||
#define KVM_CAP_PPC_OSI 52
|
||||
#define KVM_CAP_PPC_UNSET_IRQ 53
|
||||
#define KVM_CAP_ENABLE_CAP 54
|
||||
#ifdef __KVM_HAVE_XSAVE
|
||||
#define KVM_CAP_XSAVE 55
|
||||
#endif
|
||||
#ifdef __KVM_HAVE_XCRS
|
||||
#define KVM_CAP_XCRS 56
|
||||
#endif
|
||||
|
||||
#ifdef KVM_CAP_IRQ_ROUTING
|
||||
|
||||
struct kvm_irq_routing_irqchip {
|
||||
__u32 irqchip;
|
||||
__u32 pin;
|
||||
};
|
||||
|
||||
struct kvm_irq_routing_msi {
|
||||
__u32 address_lo;
|
||||
__u32 address_hi;
|
||||
__u32 data;
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
/* gsi routing entry types */
|
||||
#define KVM_IRQ_ROUTING_IRQCHIP 1
|
||||
#define KVM_IRQ_ROUTING_MSI 2
|
||||
|
||||
struct kvm_irq_routing_entry {
|
||||
__u32 gsi;
|
||||
__u32 type;
|
||||
__u32 flags;
|
||||
__u32 pad;
|
||||
union {
|
||||
struct kvm_irq_routing_irqchip irqchip;
|
||||
struct kvm_irq_routing_msi msi;
|
||||
__u32 pad[8];
|
||||
} u;
|
||||
};
|
||||
|
||||
struct kvm_irq_routing {
|
||||
__u32 nr;
|
||||
__u32 flags;
|
||||
struct kvm_irq_routing_entry entries[0];
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef KVM_CAP_MCE
|
||||
/* x86 MCE */
|
||||
struct kvm_x86_mce {
|
||||
__u64 status;
|
||||
__u64 addr;
|
||||
__u64 misc;
|
||||
__u64 mcg_status;
|
||||
__u8 bank;
|
||||
__u8 pad1[7];
|
||||
__u64 pad2[3];
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef KVM_CAP_XEN_HVM
|
||||
struct kvm_xen_hvm_config {
|
||||
__u32 flags;
|
||||
__u32 msr;
|
||||
__u64 blob_addr_32;
|
||||
__u64 blob_addr_64;
|
||||
__u8 blob_size_32;
|
||||
__u8 blob_size_64;
|
||||
__u8 pad2[30];
|
||||
};
|
||||
#endif
|
||||
|
||||
#define KVM_IRQFD_FLAG_DEASSIGN (1 << 0)
|
||||
|
||||
struct kvm_irqfd {
|
||||
__u32 fd;
|
||||
__u32 gsi;
|
||||
__u32 flags;
|
||||
__u8 pad[20];
|
||||
};
|
||||
|
||||
struct kvm_clock_data {
|
||||
__u64 clock;
|
||||
__u32 flags;
|
||||
__u32 pad[9];
|
||||
};
|
||||
|
||||
/*
|
||||
* ioctls for VM fds
|
||||
*/
|
||||
#define KVM_SET_MEMORY_REGION _IOW(KVMIO, 0x40, struct kvm_memory_region)
|
||||
/*
|
||||
* KVM_CREATE_VCPU receives as a parameter the vcpu slot, and returns
|
||||
* a vcpu fd.
|
||||
*/
|
||||
#define KVM_CREATE_VCPU _IO(KVMIO, 0x41)
|
||||
#define KVM_GET_DIRTY_LOG _IOW(KVMIO, 0x42, struct kvm_dirty_log)
|
||||
/* KVM_SET_MEMORY_ALIAS is obsolete: */
|
||||
#define KVM_SET_MEMORY_ALIAS _IOW(KVMIO, 0x43, struct kvm_memory_alias)
|
||||
#define KVM_SET_NR_MMU_PAGES _IO(KVMIO, 0x44)
|
||||
#define KVM_GET_NR_MMU_PAGES _IO(KVMIO, 0x45)
|
||||
#define KVM_SET_USER_MEMORY_REGION _IOW(KVMIO, 0x46, \
|
||||
struct kvm_userspace_memory_region)
|
||||
#define KVM_SET_TSS_ADDR _IO(KVMIO, 0x47)
|
||||
#define KVM_SET_IDENTITY_MAP_ADDR _IOW(KVMIO, 0x48, __u64)
|
||||
/* Device model IOC */
|
||||
#define KVM_CREATE_IRQCHIP _IO(KVMIO, 0x60)
|
||||
#define KVM_IRQ_LINE _IOW(KVMIO, 0x61, struct kvm_irq_level)
|
||||
#define KVM_GET_IRQCHIP _IOWR(KVMIO, 0x62, struct kvm_irqchip)
|
||||
#define KVM_SET_IRQCHIP _IOR(KVMIO, 0x63, struct kvm_irqchip)
|
||||
#define KVM_CREATE_PIT _IO(KVMIO, 0x64)
|
||||
#define KVM_GET_PIT _IOWR(KVMIO, 0x65, struct kvm_pit_state)
|
||||
#define KVM_SET_PIT _IOR(KVMIO, 0x66, struct kvm_pit_state)
|
||||
#define KVM_IRQ_LINE_STATUS _IOWR(KVMIO, 0x67, struct kvm_irq_level)
|
||||
#define KVM_REGISTER_COALESCED_MMIO \
|
||||
_IOW(KVMIO, 0x67, struct kvm_coalesced_mmio_zone)
|
||||
#define KVM_UNREGISTER_COALESCED_MMIO \
|
||||
_IOW(KVMIO, 0x68, struct kvm_coalesced_mmio_zone)
|
||||
#define KVM_ASSIGN_PCI_DEVICE _IOR(KVMIO, 0x69, \
|
||||
struct kvm_assigned_pci_dev)
|
||||
#define KVM_SET_GSI_ROUTING _IOW(KVMIO, 0x6a, struct kvm_irq_routing)
|
||||
/* deprecated, replaced by KVM_ASSIGN_DEV_IRQ */
|
||||
#define KVM_ASSIGN_IRQ __KVM_DEPRECATED_VM_R_0x70
|
||||
#define KVM_ASSIGN_DEV_IRQ _IOW(KVMIO, 0x70, struct kvm_assigned_irq)
|
||||
#define KVM_REINJECT_CONTROL _IO(KVMIO, 0x71)
|
||||
#define KVM_DEASSIGN_PCI_DEVICE _IOW(KVMIO, 0x72, \
|
||||
struct kvm_assigned_pci_dev)
|
||||
#define KVM_ASSIGN_SET_MSIX_NR _IOW(KVMIO, 0x73, \
|
||||
struct kvm_assigned_msix_nr)
|
||||
#define KVM_ASSIGN_SET_MSIX_ENTRY _IOW(KVMIO, 0x74, \
|
||||
struct kvm_assigned_msix_entry)
|
||||
#define KVM_DEASSIGN_DEV_IRQ _IOW(KVMIO, 0x75, struct kvm_assigned_irq)
|
||||
#define KVM_IRQFD _IOW(KVMIO, 0x76, struct kvm_irqfd)
|
||||
#define KVM_CREATE_PIT2 _IOW(KVMIO, 0x77, struct kvm_pit_config)
|
||||
#define KVM_SET_BOOT_CPU_ID _IO(KVMIO, 0x78)
|
||||
#define KVM_IOEVENTFD _IOW(KVMIO, 0x79, struct kvm_ioeventfd)
|
||||
#define KVM_XEN_HVM_CONFIG _IOW(KVMIO, 0x7a, struct kvm_xen_hvm_config)
|
||||
#define KVM_SET_CLOCK _IOW(KVMIO, 0x7b, struct kvm_clock_data)
|
||||
#define KVM_GET_CLOCK _IOR(KVMIO, 0x7c, struct kvm_clock_data)
|
||||
/* Available with KVM_CAP_PIT_STATE2 */
|
||||
#define KVM_GET_PIT2 _IOR(KVMIO, 0x9f, struct kvm_pit_state2)
|
||||
#define KVM_SET_PIT2 _IOW(KVMIO, 0xa0, struct kvm_pit_state2)
|
||||
|
||||
/*
|
||||
* ioctls for vcpu fds
|
||||
*/
|
||||
#define KVM_RUN _IO(KVMIO, 0x80)
|
||||
#define KVM_GET_REGS _IOR(KVMIO, 0x81, struct kvm_regs)
|
||||
#define KVM_SET_REGS _IOW(KVMIO, 0x82, struct kvm_regs)
|
||||
#define KVM_GET_SREGS _IOR(KVMIO, 0x83, struct kvm_sregs)
|
||||
#define KVM_SET_SREGS _IOW(KVMIO, 0x84, struct kvm_sregs)
|
||||
#define KVM_TRANSLATE _IOWR(KVMIO, 0x85, struct kvm_translation)
|
||||
#define KVM_INTERRUPT _IOW(KVMIO, 0x86, struct kvm_interrupt)
|
||||
/* KVM_DEBUG_GUEST is no longer supported, use KVM_SET_GUEST_DEBUG instead */
|
||||
#define KVM_DEBUG_GUEST __KVM_DEPRECATED_VCPU_W_0x87
|
||||
#define KVM_GET_MSRS _IOWR(KVMIO, 0x88, struct kvm_msrs)
|
||||
#define KVM_SET_MSRS _IOW(KVMIO, 0x89, struct kvm_msrs)
|
||||
#define KVM_SET_CPUID _IOW(KVMIO, 0x8a, struct kvm_cpuid)
|
||||
#define KVM_SET_SIGNAL_MASK _IOW(KVMIO, 0x8b, struct kvm_signal_mask)
|
||||
#define KVM_GET_FPU _IOR(KVMIO, 0x8c, struct kvm_fpu)
|
||||
#define KVM_SET_FPU _IOW(KVMIO, 0x8d, struct kvm_fpu)
|
||||
#define KVM_GET_LAPIC _IOR(KVMIO, 0x8e, struct kvm_lapic_state)
|
||||
#define KVM_SET_LAPIC _IOW(KVMIO, 0x8f, struct kvm_lapic_state)
|
||||
#define KVM_SET_CPUID2 _IOW(KVMIO, 0x90, struct kvm_cpuid2)
|
||||
#define KVM_GET_CPUID2 _IOWR(KVMIO, 0x91, struct kvm_cpuid2)
|
||||
/* Available with KVM_CAP_VAPIC */
|
||||
#define KVM_TPR_ACCESS_REPORTING _IOWR(KVMIO, 0x92, struct kvm_tpr_access_ctl)
|
||||
/* Available with KVM_CAP_VAPIC */
|
||||
#define KVM_SET_VAPIC_ADDR _IOW(KVMIO, 0x93, struct kvm_vapic_addr)
|
||||
/* valid for virtual machine (for floating interrupt)_and_ vcpu */
|
||||
#define KVM_S390_INTERRUPT _IOW(KVMIO, 0x94, struct kvm_s390_interrupt)
|
||||
/* store status for s390 */
|
||||
#define KVM_S390_STORE_STATUS_NOADDR (-1ul)
|
||||
#define KVM_S390_STORE_STATUS_PREFIXED (-2ul)
|
||||
#define KVM_S390_STORE_STATUS _IOW(KVMIO, 0x95, unsigned long)
|
||||
/* initial ipl psw for s390 */
|
||||
#define KVM_S390_SET_INITIAL_PSW _IOW(KVMIO, 0x96, struct kvm_s390_psw)
|
||||
/* initial reset for s390 */
|
||||
#define KVM_S390_INITIAL_RESET _IO(KVMIO, 0x97)
|
||||
#define KVM_GET_MP_STATE _IOR(KVMIO, 0x98, struct kvm_mp_state)
|
||||
#define KVM_SET_MP_STATE _IOW(KVMIO, 0x99, struct kvm_mp_state)
|
||||
/* Available with KVM_CAP_NMI */
|
||||
#define KVM_NMI _IO(KVMIO, 0x9a)
|
||||
/* Available with KVM_CAP_SET_GUEST_DEBUG */
|
||||
#define KVM_SET_GUEST_DEBUG _IOW(KVMIO, 0x9b, struct kvm_guest_debug)
|
||||
/* MCE for x86 */
|
||||
#define KVM_X86_SETUP_MCE _IOW(KVMIO, 0x9c, __u64)
|
||||
#define KVM_X86_GET_MCE_CAP_SUPPORTED _IOR(KVMIO, 0x9d, __u64)
|
||||
#define KVM_X86_SET_MCE _IOW(KVMIO, 0x9e, struct kvm_x86_mce)
|
||||
/* IA64 stack access */
|
||||
#define KVM_IA64_VCPU_GET_STACK _IOR(KVMIO, 0x9a, void *)
|
||||
#define KVM_IA64_VCPU_SET_STACK _IOW(KVMIO, 0x9b, void *)
|
||||
/* Available with KVM_CAP_VCPU_EVENTS */
|
||||
#define KVM_GET_VCPU_EVENTS _IOR(KVMIO, 0x9f, struct kvm_vcpu_events)
|
||||
#define KVM_SET_VCPU_EVENTS _IOW(KVMIO, 0xa0, struct kvm_vcpu_events)
|
||||
/* Available with KVM_CAP_DEBUGREGS */
|
||||
#define KVM_GET_DEBUGREGS _IOR(KVMIO, 0xa1, struct kvm_debugregs)
|
||||
#define KVM_SET_DEBUGREGS _IOW(KVMIO, 0xa2, struct kvm_debugregs)
|
||||
#define KVM_ENABLE_CAP _IOW(KVMIO, 0xa3, struct kvm_enable_cap)
|
||||
/* Available with KVM_CAP_XSAVE */
|
||||
#define KVM_GET_XSAVE _IOR(KVMIO, 0xa4, struct kvm_xsave)
|
||||
#define KVM_SET_XSAVE _IOW(KVMIO, 0xa5, struct kvm_xsave)
|
||||
/* Available with KVM_CAP_XCRS */
|
||||
#define KVM_GET_XCRS _IOR(KVMIO, 0xa6, struct kvm_xcrs)
|
||||
#define KVM_SET_XCRS _IOW(KVMIO, 0xa7, struct kvm_xcrs)
|
||||
|
||||
#define KVM_DEV_ASSIGN_ENABLE_IOMMU (1 << 0)
|
||||
|
||||
struct kvm_assigned_pci_dev {
|
||||
__u32 assigned_dev_id;
|
||||
__u32 busnr;
|
||||
__u32 devfn;
|
||||
__u32 flags;
|
||||
__u32 segnr;
|
||||
union {
|
||||
__u32 reserved[11];
|
||||
};
|
||||
};
|
||||
|
||||
#define KVM_DEV_IRQ_HOST_INTX (1 << 0)
|
||||
#define KVM_DEV_IRQ_HOST_MSI (1 << 1)
|
||||
#define KVM_DEV_IRQ_HOST_MSIX (1 << 2)
|
||||
|
||||
#define KVM_DEV_IRQ_GUEST_INTX (1 << 8)
|
||||
#define KVM_DEV_IRQ_GUEST_MSI (1 << 9)
|
||||
#define KVM_DEV_IRQ_GUEST_MSIX (1 << 10)
|
||||
|
||||
#define KVM_DEV_IRQ_HOST_MASK 0x00ff
|
||||
#define KVM_DEV_IRQ_GUEST_MASK 0xff00
|
||||
|
||||
struct kvm_assigned_irq {
|
||||
__u32 assigned_dev_id;
|
||||
__u32 host_irq;
|
||||
__u32 guest_irq;
|
||||
__u32 flags;
|
||||
union {
|
||||
struct {
|
||||
__u32 addr_lo;
|
||||
__u32 addr_hi;
|
||||
__u32 data;
|
||||
} guest_msi;
|
||||
__u32 reserved[12];
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
struct kvm_assigned_msix_nr {
|
||||
__u32 assigned_dev_id;
|
||||
__u16 entry_nr;
|
||||
__u16 padding;
|
||||
};
|
||||
|
||||
#define KVM_MAX_MSIX_PER_DEV 256
|
||||
struct kvm_assigned_msix_entry {
|
||||
__u32 assigned_dev_id;
|
||||
__u32 gsi;
|
||||
__u16 entry; /* The index of entry in the MSI-X table */
|
||||
__u16 padding[3];
|
||||
};
|
||||
|
||||
#endif /* __LINUX_KVM_H */
|
||||
Reference in New Issue
Block a user