OERV-RUNTIME/boringssl
2
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

update main-with-bazel from master branch

Browse Source
This commit is contained in:
BoringSSL Robot
2023-12-12 03:36:26 +00:00
parent c75452e60e 10c24cb433
commit 4e2ea1f092
28 changed files with 634 additions and 586 deletions
Download Patch File Download Diff File Expand all files Collapse all files
apple-aarch64/crypto/fipsmodule/sha1-armv8-apple.S
+6 -15
View File
@@ -8,23 +8,13 @@
.text
.private_extern _OPENSSL_armcap_P
.globl _sha1_block_data_order
.private_extern _sha1_block_data_order
.globl _sha1_block_data_order_nohw
.private_extern _sha1_block_data_order_nohw
.align 6
_sha1_block_data_order:
_sha1_block_data_order_nohw:
// Armv8.3-A PAuth: even though x30 is pushed to stack it is not popped later.
AARCH64_VALID_CALL_TARGET
#if defined(OPENSSL_HWASAN) && __clang_major__ >= 10
adrp x16,:pg_hi21_nc:_OPENSSL_armcap_P
#else
adrp x16,_OPENSSL_armcap_P@PAGE
#endif
ldr w16,[x16,_OPENSSL_armcap_P@PAGEOFF]
tst w16,#ARMV8_SHA1
b.ne Lv8_entry
stp x29,x30,[sp,#-96]!
add x29,sp,#0
@@ -1081,12 +1071,13 @@ Loop:
ldr x29,[sp],#96
ret
.globl _sha1_block_data_order_hw
.private_extern _sha1_block_data_order_hw
.align 6
sha1_block_armv8:
_sha1_block_data_order_hw:
// Armv8.3-A PAuth: even though x30 is pushed to stack it is not popped later.
AARCH64_VALID_CALL_TARGET
Lv8_entry:
stp x29,x30,[sp,#-16]!
add x29,sp,#0
apple-aarch64/crypto/fipsmodule/sha256-armv8-apple.S
+7 -18
View File
@@ -50,24 +50,11 @@
.text
.private_extern _OPENSSL_armcap_P
.globl _sha256_block_data_order
.private_extern _sha256_block_data_order
.globl _sha256_block_data_order_nohw
.private_extern _sha256_block_data_order_nohw
.align 6
_sha256_block_data_order:
AARCH64_VALID_CALL_TARGET
#ifndef __KERNEL__
#if defined(OPENSSL_HWASAN) && __clang_major__ >= 10
adrp x16,:pg_hi21_nc:_OPENSSL_armcap_P
#else
adrp x16,_OPENSSL_armcap_P@PAGE
#endif
ldr w16,[x16,_OPENSSL_armcap_P@PAGEOFF]
tst w16,#ARMV8_SHA256
b.ne Lv8_entry
#endif
_sha256_block_data_order_nohw:
AARCH64_SIGN_LINK_REGISTER
stp x29,x30,[sp,#-128]!
add x29,sp,#0
@@ -1060,11 +1047,13 @@ LK256:
.align 2
.text
#ifndef __KERNEL__
.globl _sha256_block_data_order_hw
.private_extern _sha256_block_data_order_hw
.align 6
sha256_block_armv8:
Lv8_entry:
_sha256_block_data_order_hw:
// Armv8.3-A PAuth: even though x30 is pushed to stack it is not popped later.
AARCH64_VALID_CALL_TARGET
stp x29,x30,[sp,#-16]!
add x29,sp,#0
apple-aarch64/crypto/fipsmodule/sha512-armv8-apple.S
+8 -18
View File
@@ -50,24 +50,11 @@
.text
.private_extern _OPENSSL_armcap_P
.globl _sha512_block_data_order
.private_extern _sha512_block_data_order
.globl _sha512_block_data_order_nohw
.private_extern _sha512_block_data_order_nohw
.align 6
_sha512_block_data_order:
AARCH64_VALID_CALL_TARGET
#ifndef __KERNEL__
#if defined(OPENSSL_HWASAN) && __clang_major__ >= 10
adrp x16,:pg_hi21_nc:_OPENSSL_armcap_P
#else
adrp x16,_OPENSSL_armcap_P@PAGE
#endif
ldr w16,[x16,_OPENSSL_armcap_P@PAGEOFF]
tst w16,#ARMV8_SHA512
b.ne Lv8_entry
#endif
_sha512_block_data_order_nohw:
AARCH64_SIGN_LINK_REGISTER
stp x29,x30,[sp,#-128]!
add x29,sp,#0
@@ -1084,10 +1071,13 @@ LK512:
.align 2
.text
#ifndef __KERNEL__
.globl _sha512_block_data_order_hw
.private_extern _sha512_block_data_order_hw
.align 6
sha512_block_armv8:
Lv8_entry:
_sha512_block_data_order_hw:
// Armv8.3-A PAuth: even though x30 is pushed to stack it is not popped later.
AARCH64_VALID_CALL_TARGET
stp x29,x30,[sp,#-16]!
add x29,sp,#0
apple-x86_64/crypto/fipsmodule/sha1-x86_64-apple.S
+19 -32
View File
@@ -6,34 +6,13 @@
#if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_X86_64) && defined(__APPLE__)
.text
.globl _sha1_block_data_order
.private_extern _sha1_block_data_order
.globl _sha1_block_data_order_nohw
.private_extern _sha1_block_data_order_nohw
.p2align 4
_sha1_block_data_order:
_sha1_block_data_order_nohw:
_CET_ENDBR
leaq _OPENSSL_ia32cap_P(%rip),%r10
movl 0(%r10),%r9d
movl 4(%r10),%r8d
movl 8(%r10),%r10d
testl $512,%r8d
jz L$ialu
testl $536870912,%r10d
jnz _shaext_shortcut
andl $296,%r10d
cmpl $296,%r10d
je _avx2_shortcut
andl $268435456,%r8d
andl $1073741824,%r9d
orl %r9d,%r8d
cmpl $1342177280,%r8d
je _avx_shortcut
jmp _ssse3_shortcut
.p2align 4
L$ialu:
movq %rsp,%rax
pushq %rbx
@@ -1264,11 +1243,13 @@ L$epilogue:
ret
.globl _sha1_block_data_order_hw
.private_extern _sha1_block_data_order_hw
.p2align 5
sha1_block_data_order_shaext:
_shaext_shortcut:
_sha1_block_data_order_hw:
_CET_ENDBR
movdqu (%rdi),%xmm0
movd 16(%rdi),%xmm1
movdqa K_XX_XX+160(%rip),%xmm3
@@ -1434,11 +1415,13 @@ L$oop_shaext:
ret
.globl _sha1_block_data_order_ssse3
.private_extern _sha1_block_data_order_ssse3
.p2align 4
sha1_block_data_order_ssse3:
_ssse3_shortcut:
_sha1_block_data_order_ssse3:
_CET_ENDBR
movq %rsp,%r11
pushq %rbx
@@ -2622,11 +2605,13 @@ L$epilogue_ssse3:
ret
.globl _sha1_block_data_order_avx
.private_extern _sha1_block_data_order_avx
.p2align 4
sha1_block_data_order_avx:
_avx_shortcut:
_sha1_block_data_order_avx:
_CET_ENDBR
movq %rsp,%r11
pushq %rbx
@@ -3750,11 +3735,13 @@ L$epilogue_avx:
ret
.globl _sha1_block_data_order_avx2
.private_extern _sha1_block_data_order_avx2
.p2align 4
sha1_block_data_order_avx2:
_avx2_shortcut:
_sha1_block_data_order_avx2:
_CET_ENDBR
movq %rsp,%r11
pushq %rbx
apple-x86_64/crypto/fipsmodule/sha256-x86_64-apple.S
+15 -23
View File
@@ -6,27 +6,13 @@
#if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_X86_64) && defined(__APPLE__)
.text
.globl _sha256_block_data_order
.private_extern _sha256_block_data_order
.globl _sha256_block_data_order_nohw
.private_extern _sha256_block_data_order_nohw
.p2align 4
_sha256_block_data_order:
_sha256_block_data_order_nohw:
_CET_ENDBR
leaq _OPENSSL_ia32cap_P(%rip),%r11
movl 0(%r11),%r9d
movl 4(%r11),%r10d
movl 8(%r11),%r11d
testl $536870912,%r11d
jnz L$shaext_shortcut
andl $1073741824,%r9d
andl $268435968,%r10d
orl %r9d,%r10d
cmpl $1342177792,%r10d
je L$avx_shortcut
testl $512,%r10d
jnz L$ssse3_shortcut
movq %rsp,%rax
pushq %rbx
@@ -1778,11 +1764,13 @@ K256:
.long 0xffffffff,0xffffffff,0x03020100,0x0b0a0908
.byte 83,72,65,50,53,54,32,98,108,111,99,107,32,116,114,97,110,115,102,111,114,109,32,102,111,114,32,120,56,54,95,54,52,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0
.text
.globl _sha256_block_data_order_hw
.private_extern _sha256_block_data_order_hw
.p2align 6
sha256_block_data_order_shaext:
_sha256_block_data_order_hw:
L$shaext_shortcut:
_CET_ENDBR
leaq K256+128(%rip),%rcx
movdqu (%rdi),%xmm1
movdqu 16(%rdi),%xmm2
@@ -1987,11 +1975,13 @@ L$oop_shaext:
ret
.globl _sha256_block_data_order_ssse3
.private_extern _sha256_block_data_order_ssse3
.p2align 6
sha256_block_data_order_ssse3:
_sha256_block_data_order_ssse3:
L$ssse3_shortcut:
_CET_ENDBR
movq %rsp,%rax
pushq %rbx
@@ -3100,11 +3090,13 @@ L$epilogue_ssse3:
ret
.globl _sha256_block_data_order_avx
.private_extern _sha256_block_data_order_avx
.p2align 6
sha256_block_data_order_avx:
_sha256_block_data_order_avx:
L$avx_shortcut:
_CET_ENDBR
movq %rsp,%rax
pushq %rbx
apple-x86_64/crypto/fipsmodule/sha512-x86_64-apple.S
+7 -15
View File
@@ -6,23 +6,13 @@
#if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_X86_64) && defined(__APPLE__)
.text
.globl _sha512_block_data_order
.private_extern _sha512_block_data_order
.globl _sha512_block_data_order_nohw
.private_extern _sha512_block_data_order_nohw
.p2align 4
_sha512_block_data_order:
_sha512_block_data_order_nohw:
_CET_ENDBR
leaq _OPENSSL_ia32cap_P(%rip),%r11
movl 0(%r11),%r9d
movl 4(%r11),%r10d
movl 8(%r11),%r11d
andl $1073741824,%r9d
andl $268435968,%r10d
orl %r9d,%r10d
cmpl $1342177792,%r10d
je L$avx_shortcut
movq %rsp,%rax
pushq %rbx
@@ -1818,11 +1808,13 @@ K512:
.quad 0x0001020304050607,0x08090a0b0c0d0e0f
.byte 83,72,65,53,49,50,32,98,108,111,99,107,32,116,114,97,110,115,102,111,114,109,32,102,111,114,32,120,56,54,95,54,52,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0
.text
.globl _sha512_block_data_order_avx
.private_extern _sha512_block_data_order_avx
.p2align 6
sha512_block_data_order_avx:
_sha512_block_data_order_avx:
L$avx_shortcut:
_CET_ENDBR
movq %rsp,%rax
pushq %rbx
linux-aarch64/crypto/fipsmodule/sha1-armv8-linux.S
+10 -19
View File
@@ -8,23 +8,13 @@
.text
.hidden OPENSSL_armcap_P
.globl sha1_block_data_order
.hidden sha1_block_data_order
.type sha1_block_data_order,%function
.globl sha1_block_data_order_nohw
.hidden sha1_block_data_order_nohw
.type sha1_block_data_order_nohw,%function
.align 6
sha1_block_data_order:
sha1_block_data_order_nohw:
// Armv8.3-A PAuth: even though x30 is pushed to stack it is not popped later.
AARCH64_VALID_CALL_TARGET
#if defined(OPENSSL_HWASAN) && __clang_major__ >= 10
adrp x16,:pg_hi21_nc:OPENSSL_armcap_P
#else
adrp x16,OPENSSL_armcap_P
#endif
ldr w16,[x16,:lo12:OPENSSL_armcap_P]
tst w16,#ARMV8_SHA1
b.ne .Lv8_entry
stp x29,x30,[sp,#-96]!
add x29,sp,#0
@@ -1080,13 +1070,14 @@ sha1_block_data_order:
ldp x27,x28,[sp,#80]
ldr x29,[sp],#96
ret
.size sha1_block_data_order,.-sha1_block_data_order
.type sha1_block_armv8,%function
.size sha1_block_data_order_nohw,.-sha1_block_data_order_nohw
.globl sha1_block_data_order_hw
.hidden sha1_block_data_order_hw
.type sha1_block_data_order_hw,%function
.align 6
sha1_block_armv8:
sha1_block_data_order_hw:
// Armv8.3-A PAuth: even though x30 is pushed to stack it is not popped later.
AARCH64_VALID_CALL_TARGET
.Lv8_entry:
stp x29,x30,[sp,#-16]!
add x29,sp,#0
@@ -1213,7 +1204,7 @@ sha1_block_armv8:
ldr x29,[sp],#16
ret
.size sha1_block_armv8,.-sha1_block_armv8
.size sha1_block_data_order_hw,.-sha1_block_data_order_hw
.section .rodata
.align 6
.Lconst:
linux-aarch64/crypto/fipsmodule/sha256-armv8-linux.S
+11 -22
View File
@@ -50,24 +50,11 @@
.text
.hidden OPENSSL_armcap_P
.globl sha256_block_data_order
.hidden sha256_block_data_order
.type sha256_block_data_order,%function
.globl sha256_block_data_order_nohw
.hidden sha256_block_data_order_nohw
.type sha256_block_data_order_nohw,%function
.align 6
sha256_block_data_order:
AARCH64_VALID_CALL_TARGET
#ifndef __KERNEL__
#if defined(OPENSSL_HWASAN) && __clang_major__ >= 10
adrp x16,:pg_hi21_nc:OPENSSL_armcap_P
#else
adrp x16,OPENSSL_armcap_P
#endif
ldr w16,[x16,:lo12:OPENSSL_armcap_P]
tst w16,#ARMV8_SHA256
b.ne .Lv8_entry
#endif
sha256_block_data_order_nohw:
AARCH64_SIGN_LINK_REGISTER
stp x29,x30,[sp,#-128]!
add x29,sp,#0
@@ -1031,7 +1018,7 @@ sha256_block_data_order:
ldp x29,x30,[sp],#128
AARCH64_VALIDATE_LINK_REGISTER
ret
.size sha256_block_data_order,.-sha256_block_data_order
.size sha256_block_data_order_nohw,.-sha256_block_data_order_nohw
.section .rodata
.align 6
@@ -1060,11 +1047,13 @@ sha256_block_data_order:
.align 2
.text
#ifndef __KERNEL__
.type sha256_block_armv8,%function
.globl sha256_block_data_order_hw
.hidden sha256_block_data_order_hw
.type sha256_block_data_order_hw,%function
.align 6
sha256_block_armv8:
.Lv8_entry:
sha256_block_data_order_hw:
// Armv8.3-A PAuth: even though x30 is pushed to stack it is not popped later.
AARCH64_VALID_CALL_TARGET
stp x29,x30,[sp,#-16]!
add x29,sp,#0
@@ -1199,6 +1188,6 @@ sha256_block_armv8:
ldr x29,[sp],#16
ret
.size sha256_block_armv8,.-sha256_block_armv8
.size sha256_block_data_order_hw,.-sha256_block_data_order_hw
#endif
#endif // !OPENSSL_NO_ASM && defined(OPENSSL_AARCH64) && defined(__ELF__)
linux-aarch64/crypto/fipsmodule/sha512-armv8-linux.S
+12 -22
View File
@@ -50,24 +50,11 @@
.text
.hidden OPENSSL_armcap_P
.globl sha512_block_data_order
.hidden sha512_block_data_order
.type sha512_block_data_order,%function
.globl sha512_block_data_order_nohw
.hidden sha512_block_data_order_nohw
.type sha512_block_data_order_nohw,%function
.align 6
sha512_block_data_order:
AARCH64_VALID_CALL_TARGET
#ifndef __KERNEL__
#if defined(OPENSSL_HWASAN) && __clang_major__ >= 10
adrp x16,:pg_hi21_nc:OPENSSL_armcap_P
#else
adrp x16,OPENSSL_armcap_P
#endif
ldr w16,[x16,:lo12:OPENSSL_armcap_P]
tst w16,#ARMV8_SHA512
b.ne .Lv8_entry
#endif
sha512_block_data_order_nohw:
AARCH64_SIGN_LINK_REGISTER
stp x29,x30,[sp,#-128]!
add x29,sp,#0
@@ -1031,7 +1018,7 @@ sha512_block_data_order:
ldp x29,x30,[sp],#128
AARCH64_VALIDATE_LINK_REGISTER
ret
.size sha512_block_data_order,.-sha512_block_data_order
.size sha512_block_data_order_nohw,.-sha512_block_data_order_nohw
.section .rodata
.align 6
@@ -1084,10 +1071,13 @@ sha512_block_data_order:
.align 2
.text
#ifndef __KERNEL__
.type sha512_block_armv8,%function
.globl sha512_block_data_order_hw
.hidden sha512_block_data_order_hw
.type sha512_block_data_order_hw,%function
.align 6
sha512_block_armv8:
.Lv8_entry:
sha512_block_data_order_hw:
// Armv8.3-A PAuth: even though x30 is pushed to stack it is not popped later.
AARCH64_VALID_CALL_TARGET
stp x29,x30,[sp,#-16]!
add x29,sp,#0
@@ -1601,6 +1591,6 @@ sha512_block_armv8:
ldr x29,[sp],#16
ret
.size sha512_block_armv8,.-sha512_block_armv8
.size sha512_block_data_order_hw,.-sha512_block_data_order_hw
#endif
#endif // !OPENSSL_NO_ASM && defined(OPENSSL_AARCH64) && defined(__ELF__)
linux-x86_64/crypto/fipsmodule/sha1-x86_64-linux.S
+20 -34
View File
@@ -5,36 +5,14 @@
#if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_X86_64) && defined(__ELF__)
.text
.extern OPENSSL_ia32cap_P
.hidden OPENSSL_ia32cap_P
.globl sha1_block_data_order
.hidden sha1_block_data_order
.type sha1_block_data_order,@function
.globl sha1_block_data_order_nohw
.hidden sha1_block_data_order_nohw
.type sha1_block_data_order_nohw,@function
.align 16
sha1_block_data_order:
sha1_block_data_order_nohw:
.cfi_startproc
_CET_ENDBR
leaq OPENSSL_ia32cap_P(%rip),%r10
movl 0(%r10),%r9d
movl 4(%r10),%r8d
movl 8(%r10),%r10d
testl $512,%r8d
jz .Lialu
testl $536870912,%r10d
jnz _shaext_shortcut
andl $296,%r10d
cmpl $296,%r10d
je _avx2_shortcut
andl $268435456,%r8d
andl $1073741824,%r9d
orl %r9d,%r8d
cmpl $1342177280,%r8d
je _avx_shortcut
jmp _ssse3_shortcut
.align 16
.Lialu:
movq %rsp,%rax
.cfi_def_cfa_register %rax
pushq %rbx
@@ -1264,12 +1242,14 @@ _CET_ENDBR
.Lepilogue:
ret
.cfi_endproc
.size sha1_block_data_order,.-sha1_block_data_order
.type sha1_block_data_order_shaext,@function
.size sha1_block_data_order_nohw,.-sha1_block_data_order_nohw
.globl sha1_block_data_order_hw
.hidden sha1_block_data_order_hw
.type sha1_block_data_order_hw,@function
.align 32
sha1_block_data_order_shaext:
_shaext_shortcut:
sha1_block_data_order_hw:
.cfi_startproc
_CET_ENDBR
movdqu (%rdi),%xmm0
movd 16(%rdi),%xmm1
movdqa K_XX_XX+160(%rip),%xmm3
@@ -1434,12 +1414,14 @@ _shaext_shortcut:
movd %xmm1,16(%rdi)
ret
.cfi_endproc
.size sha1_block_data_order_shaext,.-sha1_block_data_order_shaext
.size sha1_block_data_order_hw,.-sha1_block_data_order_hw
.globl sha1_block_data_order_ssse3
.hidden sha1_block_data_order_ssse3
.type sha1_block_data_order_ssse3,@function
.align 16
sha1_block_data_order_ssse3:
_ssse3_shortcut:
.cfi_startproc
_CET_ENDBR
movq %rsp,%r11
.cfi_def_cfa_register %r11
pushq %rbx
@@ -2623,11 +2605,13 @@ _ssse3_shortcut:
ret
.cfi_endproc
.size sha1_block_data_order_ssse3,.-sha1_block_data_order_ssse3
.globl sha1_block_data_order_avx
.hidden sha1_block_data_order_avx
.type sha1_block_data_order_avx,@function
.align 16
sha1_block_data_order_avx:
_avx_shortcut:
.cfi_startproc
_CET_ENDBR
movq %rsp,%r11
.cfi_def_cfa_register %r11
pushq %rbx
@@ -3751,11 +3735,13 @@ _avx_shortcut:
ret
.cfi_endproc
.size sha1_block_data_order_avx,.-sha1_block_data_order_avx
.globl sha1_block_data_order_avx2
.hidden sha1_block_data_order_avx2
.type sha1_block_data_order_avx2,@function
.align 16
sha1_block_data_order_avx2:
_avx2_shortcut:
.cfi_startproc
_CET_ENDBR
movq %rsp,%r11
.cfi_def_cfa_register %r11
pushq %rbx
linux-x86_64/crypto/fipsmodule/sha256-x86_64-linux.S
+17 -26
View File
@@ -6,28 +6,13 @@
#if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_X86_64) && defined(__ELF__)
.text
.extern OPENSSL_ia32cap_P
.hidden OPENSSL_ia32cap_P
.globl sha256_block_data_order
.hidden sha256_block_data_order
.type sha256_block_data_order,@function
.globl sha256_block_data_order_nohw
.hidden sha256_block_data_order_nohw
.type sha256_block_data_order_nohw,@function
.align 16
sha256_block_data_order:
sha256_block_data_order_nohw:
.cfi_startproc
_CET_ENDBR
leaq OPENSSL_ia32cap_P(%rip),%r11
movl 0(%r11),%r9d
movl 4(%r11),%r10d
movl 8(%r11),%r11d
testl $536870912,%r11d
jnz .Lshaext_shortcut
andl $1073741824,%r9d
andl $268435968,%r10d
orl %r9d,%r10d
cmpl $1342177792,%r10d
je .Lavx_shortcut
testl $512,%r10d
jnz .Lssse3_shortcut
movq %rsp,%rax
.cfi_def_cfa_register %rax
pushq %rbx
@@ -1733,7 +1718,7 @@ _CET_ENDBR
.Lepilogue:
ret
.cfi_endproc
.size sha256_block_data_order,.-sha256_block_data_order
.size sha256_block_data_order_nohw,.-sha256_block_data_order_nohw
.section .rodata
.align 64
.type K256,@object
@@ -1779,11 +1764,13 @@ K256:
.long 0xffffffff,0xffffffff,0x03020100,0x0b0a0908
.byte 83,72,65,50,53,54,32,98,108,111,99,107,32,116,114,97,110,115,102,111,114,109,32,102,111,114,32,120,56,54,95,54,52,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0
.text
.type sha256_block_data_order_shaext,@function
.globl sha256_block_data_order_hw
.hidden sha256_block_data_order_hw
.type sha256_block_data_order_hw,@function
.align 64
sha256_block_data_order_shaext:
sha256_block_data_order_hw:
.cfi_startproc
.Lshaext_shortcut:
_CET_ENDBR
leaq K256+128(%rip),%rcx
movdqu (%rdi),%xmm1
movdqu 16(%rdi),%xmm2
@@ -1987,12 +1974,14 @@ sha256_block_data_order_shaext:
movdqu %xmm2,16(%rdi)
ret
.cfi_endproc
.size sha256_block_data_order_shaext,.-sha256_block_data_order_shaext
.size sha256_block_data_order_hw,.-sha256_block_data_order_hw
.globl sha256_block_data_order_ssse3
.hidden sha256_block_data_order_ssse3
.type sha256_block_data_order_ssse3,@function
.align 64
sha256_block_data_order_ssse3:
.cfi_startproc
.Lssse3_shortcut:
_CET_ENDBR
movq %rsp,%rax
.cfi_def_cfa_register %rax
pushq %rbx
@@ -3101,11 +3090,13 @@ sha256_block_data_order_ssse3:
ret
.cfi_endproc
.size sha256_block_data_order_ssse3,.-sha256_block_data_order_ssse3
.globl sha256_block_data_order_avx
.hidden sha256_block_data_order_avx
.type sha256_block_data_order_avx,@function
.align 64
sha256_block_data_order_avx:
.cfi_startproc
.Lavx_shortcut:
_CET_ENDBR
movq %rsp,%rax
.cfi_def_cfa_register %rax
pushq %rbx
linux-x86_64/crypto/fipsmodule/sha512-x86_64-linux.S
+8 -17
View File
@@ -6,24 +6,13 @@
#if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_X86_64) && defined(__ELF__)
.text
.extern OPENSSL_ia32cap_P
.hidden OPENSSL_ia32cap_P
.globl sha512_block_data_order
.hidden sha512_block_data_order
.type sha512_block_data_order,@function
.globl sha512_block_data_order_nohw
.hidden sha512_block_data_order_nohw
.type sha512_block_data_order_nohw,@function
.align 16
sha512_block_data_order:
sha512_block_data_order_nohw:
.cfi_startproc
_CET_ENDBR
leaq OPENSSL_ia32cap_P(%rip),%r11
movl 0(%r11),%r9d
movl 4(%r11),%r10d
movl 8(%r11),%r11d
andl $1073741824,%r9d
andl $268435968,%r10d
orl %r9d,%r10d
cmpl $1342177792,%r10d
je .Lavx_shortcut
movq %rsp,%rax
.cfi_def_cfa_register %rax
pushq %rbx
@@ -1729,7 +1718,7 @@ _CET_ENDBR
.Lepilogue:
ret
.cfi_endproc
.size sha512_block_data_order,.-sha512_block_data_order
.size sha512_block_data_order_nohw,.-sha512_block_data_order_nohw
.section .rodata
.align 64
.type K512,@object
@@ -1819,11 +1808,13 @@ K512:
.quad 0x0001020304050607,0x08090a0b0c0d0e0f
.byte 83,72,65,53,49,50,32,98,108,111,99,107,32,116,114,97,110,115,102,111,114,109,32,102,111,114,32,120,56,54,95,54,52,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0
.text
.globl sha512_block_data_order_avx
.hidden sha512_block_data_order_avx
.type sha512_block_data_order_avx,@function
.align 64
sha512_block_data_order_avx:
.cfi_startproc
.Lavx_shortcut:
_CET_ENDBR
movq %rsp,%rax
.cfi_def_cfa_register %rax
pushq %rbx
src/crypto/fipsmodule/sha/asm/sha1-armv8.pl
+8 -18
View File
@@ -175,22 +175,12 @@ $code.=<<___;
.text
.extern OPENSSL_armcap_P
.hidden OPENSSL_armcap_P
.globl sha1_block_data_order
.type sha1_block_data_order,%function
.globl sha1_block_data_order_nohw
.type sha1_block_data_order_nohw,%function
.align 6
sha1_block_data_order:
sha1_block_data_order_nohw:
// Armv8.3-A PAuth: even though x30 is pushed to stack it is not popped later.
AARCH64_VALID_CALL_TARGET
#if defined(OPENSSL_HWASAN) && __clang_major__ >= 10
adrp x16,:pg_hi21_nc:OPENSSL_armcap_P
#else
adrp x16,:pg_hi21:OPENSSL_armcap_P
#endif
ldr w16,[x16,:lo12:OPENSSL_armcap_P]
tst w16,#ARMV8_SHA1
b.ne .Lv8_entry
stp x29,x30,[sp,#-96]!
add x29,sp,#0
@@ -239,7 +229,7 @@ $code.=<<___;
ldp x27,x28,[sp,#80]
ldr x29,[sp],#96
ret
.size sha1_block_data_order,.-sha1_block_data_order
.size sha1_block_data_order_nohw,.-sha1_block_data_order_nohw
___
{{{
my ($ABCD,$E,$E0,$E1)=map("v$_.16b",(0..3));
@@ -249,12 +239,12 @@ my ($W0,$W1)=("v20.4s","v21.4s");
my $ABCD_SAVE="v22.16b";
$code.=<<___;
.type sha1_block_armv8,%function
.globl sha1_block_data_order_hw
.type sha1_block_data_order_hw,%function
.align 6
sha1_block_armv8:
sha1_block_data_order_hw:
// Armv8.3-A PAuth: even though x30 is pushed to stack it is not popped later.
AARCH64_VALID_CALL_TARGET
.Lv8_entry:
stp x29,x30,[sp,#-16]!
add x29,sp,#0
@@ -318,7 +308,7 @@ $code.=<<___;
ldr x29,[sp],#16
ret
.size sha1_block_armv8,.-sha1_block_armv8
.size sha1_block_data_order_hw,.-sha1_block_data_order_hw
.section .rodata
.align 6
.Lconst:
src/crypto/fipsmodule/sha/asm/sha1-x86_64.pl
+23 -48
View File
@@ -237,42 +237,13 @@ push(@xi,shift(@xi));
$code.=<<___;
.text
.extern OPENSSL_ia32cap_P
.globl sha1_block_data_order
.type sha1_block_data_order,\@function,3
.globl sha1_block_data_order_nohw
.type sha1_block_data_order_nohw,\@function,3
.align 16
sha1_block_data_order:
sha1_block_data_order_nohw:
.cfi_startproc
_CET_ENDBR
leaq OPENSSL_ia32cap_P(%rip),%r10
mov 0(%r10),%r9d
mov 4(%r10),%r8d
mov 8(%r10),%r10d
test \$`1<<9`,%r8d # check SSSE3 bit
jz .Lialu
___
$code.=<<___ if ($shaext);
test \$`1<<29`,%r10d # check SHA bit
jnz _shaext_shortcut
___
$code.=<<___ if ($avx>1);
and \$`1<<3|1<<5|1<<8`,%r10d # check AVX2+BMI1+BMI2
cmp \$`1<<3|1<<5|1<<8`,%r10d
je _avx2_shortcut
___
$code.=<<___ if ($avx);
and \$`1<<28`,%r8d # mask AVX bit
and \$`1<<30`,%r9d # mask "Intel CPU" bit
or %r9d,%r8d
cmp \$`1<<28|1<<30`,%r8d
je _avx_shortcut
___
$code.=<<___;
jmp _ssse3_shortcut
.align 16
.Lialu:
mov %rsp,%rax
.cfi_def_cfa_register %rax
push %rbx
@@ -341,7 +312,7 @@ $code.=<<___;
.Lepilogue:
ret
.cfi_endproc
.size sha1_block_data_order,.-sha1_block_data_order
.size sha1_block_data_order_nohw,.-sha1_block_data_order_nohw
___
if ($shaext) {{{
######################################################################
@@ -352,11 +323,12 @@ my ($ABCD,$E,$E_,$BSWAP,$ABCD_SAVE,$E_SAVE)=map("%xmm$_",(0..3,8,9));
my @MSG=map("%xmm$_",(4..7));
$code.=<<___;
.type sha1_block_data_order_shaext,\@function,3
.globl sha1_block_data_order_hw
.type sha1_block_data_order_hw,\@function,3
.align 32
sha1_block_data_order_shaext:
_shaext_shortcut:
sha1_block_data_order_hw:
.cfi_startproc
_CET_ENDBR
___
$code.=<<___ if ($win64);
lea `-8-4*16`(%rsp),%rsp
@@ -457,7 +429,7 @@ ___
$code.=<<___;
ret
.cfi_endproc
.size sha1_block_data_order_shaext,.-sha1_block_data_order_shaext
.size sha1_block_data_order_hw,.-sha1_block_data_order_hw
___
}}}
{{{
@@ -487,11 +459,12 @@ ___
}
$code.=<<___;
.globl sha1_block_data_order_ssse3
.type sha1_block_data_order_ssse3,\@function,3
.align 16
sha1_block_data_order_ssse3:
_ssse3_shortcut:
.cfi_startproc
_CET_ENDBR
mov %rsp,$fp # frame pointer
.cfi_def_cfa_register $fp
push %rbx
@@ -961,11 +934,12 @@ my $_rol=sub { &shld(@_[0],@_) };
my $_ror=sub { &shrd(@_[0],@_) };
$code.=<<___;
.globl sha1_block_data_order_avx
.type sha1_block_data_order_avx,\@function,3
.align 16
sha1_block_data_order_avx:
_avx_shortcut:
.cfi_startproc
_CET_ENDBR
mov %rsp,$fp
.cfi_def_cfa_register $fp
push %rbx
@@ -1340,11 +1314,12 @@ my $rx=0;
my $frame="%r13";
$code.=<<___;
.globl sha1_block_data_order_avx2
.type sha1_block_data_order_avx2,\@function,3
.align 16
sha1_block_data_order_avx2:
_avx2_shortcut:
.cfi_startproc
_CET_ENDBR
mov %rsp,$fp
.cfi_def_cfa_register $fp
push %rbx
@@ -2019,14 +1994,14 @@ ssse3_handler:
.section .pdata
.align 4
.rva .LSEH_begin_sha1_block_data_order
.rva .LSEH_end_sha1_block_data_order
.rva .LSEH_info_sha1_block_data_order
.rva .LSEH_begin_sha1_block_data_order_nohw
.rva .LSEH_end_sha1_block_data_order_nohw
.rva .LSEH_info_sha1_block_data_order_nohw
___
$code.=<<___ if ($shaext);
.rva .LSEH_begin_sha1_block_data_order_shaext
.rva .LSEH_end_sha1_block_data_order_shaext
.rva .LSEH_info_sha1_block_data_order_shaext
.rva .LSEH_begin_sha1_block_data_order_hw
.rva .LSEH_end_sha1_block_data_order_hw
.rva .LSEH_info_sha1_block_data_order_hw
___
$code.=<<___;
.rva .LSEH_begin_sha1_block_data_order_ssse3
@@ -2046,12 +2021,12 @@ ___
$code.=<<___;
.section .xdata
.align 8
.LSEH_info_sha1_block_data_order:
.LSEH_info_sha1_block_data_order_nohw:
.byte 9,0,0,0
.rva se_handler
___
$code.=<<___ if ($shaext);
.LSEH_info_sha1_block_data_order_shaext:
.LSEH_info_sha1_block_data_order_hw:
.byte 9,0,0,0
.rva shaext_handler
___
src/crypto/fipsmodule/sha/asm/sha512-armv8.pl
+12 -30
View File
@@ -76,7 +76,7 @@ if ($flavour && $flavour ne "void") {
*STDOUT=*OUT;
}
$func="sha${BITS}_block_data_order";
$func="sha${BITS}_block_data_order_nohw";
($ctx,$inp,$num,$Ktbl)=map("x$_",(0..2,30));
@@ -180,31 +180,10 @@ $code.=<<___;
.text
.extern OPENSSL_armcap_P
.hidden OPENSSL_armcap_P
.globl $func
.type $func,%function
.align 6
$func:
AARCH64_VALID_CALL_TARGET
#ifndef __KERNEL__
#if defined(OPENSSL_HWASAN) && __clang_major__ >= 10
adrp x16,:pg_hi21_nc:OPENSSL_armcap_P
#else
adrp x16,:pg_hi21:OPENSSL_armcap_P
#endif
ldr w16,[x16,:lo12:OPENSSL_armcap_P]
___
$code.=<<___ if ($SZ==4);
tst w16,#ARMV8_SHA256
b.ne .Lv8_entry
___
$code.=<<___ if ($SZ==8);
tst w16,#ARMV8_SHA512
b.ne .Lv8_entry
___
$code.=<<___;
#endif
AARCH64_SIGN_LINK_REGISTER
stp x29,x30,[sp,#-128]!
add x29,sp,#0
@@ -356,11 +335,12 @@ my ($ABCD_SAVE,$EFGH_SAVE)=("v18.16b","v19.16b");
$code.=<<___;
.text
#ifndef __KERNEL__
.type sha256_block_armv8,%function
.globl sha256_block_data_order_hw
.type sha256_block_data_order_hw,%function
.align 6
sha256_block_armv8:
.Lv8_entry:
sha256_block_data_order_hw:
// Armv8.3-A PAuth: even though x30 is pushed to stack it is not popped later.
AARCH64_VALID_CALL_TARGET
stp x29,x30,[sp,#-16]!
add x29,sp,#0
@@ -425,7 +405,7 @@ $code.=<<___;
ldr x29,[sp],#16
ret
.size sha256_block_armv8,.-sha256_block_armv8
.size sha256_block_data_order_hw,.-sha256_block_data_order_hw
#endif
___
}
@@ -442,10 +422,12 @@ my ($AB,$CD,$EF,$GH)=map("v$_.16b",(26..29));
$code.=<<___;
.text
#ifndef __KERNEL__
.type sha512_block_armv8,%function
.globl sha512_block_data_order_hw
.type sha512_block_data_order_hw,%function
.align 6
sha512_block_armv8:
.Lv8_entry:
sha512_block_data_order_hw:
// Armv8.3-A PAuth: even though x30 is pushed to stack it is not popped later.
AARCH64_VALID_CALL_TARGET
stp x29,x30,[sp,#-16]!
add x29,sp,#0
@@ -529,7 +511,7 @@ $code.=<<___;
ldr x29,[sp],#16
ret
.size sha512_block_armv8,.-sha512_block_armv8
.size sha512_block_data_order_hw,.-sha512_block_data_order_hw
#endif
___
}
src/crypto/fipsmodule/sha/asm/sha512-x86_64.pl
+21 -48
View File
@@ -257,42 +257,12 @@ ___
$code=<<___;
.text
.extern OPENSSL_ia32cap_P
.globl $func
.type $func,\@function,3
.globl ${func}_nohw
.type ${func}_nohw,\@function,3
.align 16
$func:
${func}_nohw:
.cfi_startproc
_CET_ENDBR
___
$code.=<<___ if ($SZ==4 || $avx);
leaq OPENSSL_ia32cap_P(%rip),%r11
mov 0(%r11),%r9d
mov 4(%r11),%r10d
mov 8(%r11),%r11d
___
$code.=<<___ if ($SZ==4 && $shaext);
test \$`1<<29`,%r11d # check for SHA
jnz .Lshaext_shortcut
___
# XOP codepath removed.
$code.=<<___ if ($avx>1);
and \$`1<<8|1<<5|1<<3`,%r11d # check for BMI2+AVX2+BMI1
cmp \$`1<<8|1<<5|1<<3`,%r11d
je .Lavx2_shortcut
___
$code.=<<___ if ($avx);
and \$`1<<30`,%r9d # mask "Intel CPU" bit
and \$`1<<28|1<<9`,%r10d # mask AVX and SSSE3 bits
or %r9d,%r10d
cmp \$`1<<28|1<<9|1<<30`,%r10d
je .Lavx_shortcut
___
$code.=<<___ if ($SZ==4);
test \$`1<<9`,%r10d
jnz .Lssse3_shortcut
___
$code.=<<___;
mov %rsp,%rax # copy %rsp
.cfi_def_cfa_register %rax
push %rbx
@@ -400,7 +370,7 @@ $code.=<<___;
.Lepilogue:
ret
.cfi_endproc
.size $func,.-$func
.size ${func}_nohw,.-${func}_nohw
___
if ($SZ==4) {
@@ -558,11 +528,12 @@ my ($Wi,$ABEF,$CDGH,$TMP,$BSWAP,$ABEF_SAVE,$CDGH_SAVE)=map("%xmm$_",(0..2,7..10)
my @MSG=map("%xmm$_",(3..6));
$code.=<<___;
.type sha256_block_data_order_shaext,\@function,3
.globl sha256_block_data_order_hw
.type sha256_block_data_order_hw,\@function,3
.align 64
sha256_block_data_order_shaext:
sha256_block_data_order_hw:
.cfi_startproc
.Lshaext_shortcut:
_CET_ENDBR
___
$code.=<<___ if ($win64);
lea `-8-5*16`(%rsp),%rsp
@@ -707,7 +678,7 @@ ___
$code.=<<___;
ret
.cfi_endproc
.size sha256_block_data_order_shaext,.-sha256_block_data_order_shaext
.size sha256_block_data_order_hw,.-sha256_block_data_order_hw
___
}}}
{{{
@@ -772,11 +743,12 @@ my @X = map("%xmm$_",(0..3));
my ($t0,$t1,$t2,$t3, $t4,$t5) = map("%xmm$_",(4..9));
$code.=<<___;
.globl ${func}_ssse3
.type ${func}_ssse3,\@function,3
.align 64
${func}_ssse3:
.cfi_startproc
.Lssse3_shortcut:
_CET_ENDBR
mov %rsp,%rax # copy %rsp
.cfi_def_cfa_register %rax
push %rbx
@@ -1135,11 +1107,12 @@ if ($avx) {{
local *ror = sub { &shrd(@_[0],@_) };
$code.=<<___;
.globl ${func}_avx
.type ${func}_avx,\@function,3
.align 64
${func}_avx:
.cfi_startproc
.Lavx_shortcut:
_CET_ENDBR
mov %rsp,%rax # copy %rsp
.cfi_def_cfa_register %rax
push %rbx
@@ -2005,14 +1978,14 @@ ___
$code.=<<___;
.section .pdata
.align 4
.rva .LSEH_begin_$func
.rva .LSEH_end_$func
.rva .LSEH_info_$func
.rva .LSEH_begin_${func}_nohw
.rva .LSEH_end_${func}_nohw
.rva .LSEH_info_${func}_nohw
___
$code.=<<___ if ($SZ==4 && $shaext);
.rva .LSEH_begin_${func}_shaext
.rva .LSEH_end_${func}_shaext
.rva .LSEH_info_${func}_shaext
.rva .LSEH_begin_${func}_hw
.rva .LSEH_end_${func}_hw
.rva .LSEH_info_${func}_hw
___
$code.=<<___ if ($SZ==4);
.rva .LSEH_begin_${func}_ssse3
@@ -2032,13 +2005,13 @@ ___
$code.=<<___;
.section .xdata
.align 8
.LSEH_info_$func:
.LSEH_info_${func}_nohw:
.byte 9,0,0,0
.rva se_handler
.rva .Lprologue,.Lepilogue # HandlerData[]
___
$code.=<<___ if ($SZ==4 && $shaext);
.LSEH_info_${func}_shaext:
.LSEH_info_${func}_hw:
.byte 9,0,0,0
.rva shaext_handler
___
src/crypto/fipsmodule/sha/internal.h
+137 -6
View File
@@ -17,25 +17,156 @@
#include <openssl/base.h>
#include "../../internal.h"
#if defined(__cplusplus)
extern "C" {
#endif
// Define SHA{n}[_{variant}]_ASM if sha{n}_block_data_order[_{variant}] is
// defined in assembly.
#if !defined(OPENSSL_NO_ASM) && (defined(OPENSSL_X86) || defined(OPENSSL_ARM))
#if !defined(OPENSSL_NO_ASM) && \
(defined(OPENSSL_X86) || defined(OPENSSL_X86_64) || \
defined(OPENSSL_ARM) || defined(OPENSSL_AARCH64))
#define SHA1_ASM
#define SHA256_ASM
#define SHA512_ASM
void sha1_block_data_order(uint32_t *state, const uint8_t *in,
void sha1_block_data_order(uint32_t *state, const uint8_t *data,
size_t num_blocks);
void sha256_block_data_order(uint32_t *state, const uint8_t *in,
void sha256_block_data_order(uint32_t *state, const uint8_t *data,
size_t num_blocks);
void sha512_block_data_order(uint64_t *state, const uint8_t *in,
void sha512_block_data_order(uint64_t *state, const uint8_t *data,
size_t num_blocks);
#elif !defined(OPENSSL_NO_ASM) && defined(OPENSSL_AARCH64)
#define SHA1_ASM_NOHW
#define SHA256_ASM_NOHW
#define SHA512_ASM_NOHW
#define SHA1_ASM_HW
OPENSSL_INLINE int sha1_hw_capable(void) {
return CRYPTO_is_ARMv8_SHA1_capable();
}
#define SHA256_ASM_HW
OPENSSL_INLINE int sha256_hw_capable(void) {
return CRYPTO_is_ARMv8_SHA256_capable();
}
#define SHA512_ASM_HW
OPENSSL_INLINE int sha512_hw_capable(void) {
return CRYPTO_is_ARMv8_SHA512_capable();
}
#elif !defined(OPENSSL_NO_ASM) && defined(OPENSSL_X86_64)
#define SHA1_ASM_NOHW
#define SHA256_ASM_NOHW
#define SHA512_ASM_NOHW
#define SHA1_ASM_HW
OPENSSL_INLINE int sha1_hw_capable(void) {
return CRYPTO_is_x86_SHA_capable() && CRYPTO_is_SSSE3_capable();
}
#define SHA1_ASM_AVX2
OPENSSL_INLINE int sha1_avx2_capable(void) {
// TODO: Simplify this logic, which was extracted from the assembly:
// * Does AVX2 imply SSSE3?
// * sha1_block_data_order_avx2 does not seem to use SSSE3 instructions.
return CRYPTO_is_AVX2_capable() && CRYPTO_is_BMI2_capable() &&
CRYPTO_is_BMI1_capable() && CRYPTO_is_SSSE3_capable();
}
void sha1_block_data_order_avx2(uint32_t *state, const uint8_t *data,
size_t num);
#define SHA1_ASM_AVX
OPENSSL_INLINE int sha1_avx_capable(void) {
// TODO: Simplify this logic, which was extracted from the assembly:
// * Does AVX imply SSSE3?
// * sha1_block_data_order_avx does not seem to use SSSE3 instructions.
// Pre-Zen AMD CPUs had slow SHLD/SHRD; Zen added the SHA extension; see the
// discussion in sha1-586.pl.
return CRYPTO_is_AVX_capable() && CRYPTO_is_SSSE3_capable() &&
CRYPTO_is_intel_cpu();
}
void sha1_block_data_order_avx(uint32_t *state, const uint8_t *data,
size_t num);
#define SHA1_ASM_SSSE3
OPENSSL_INLINE int sha1_ssse3_capable(void) {
return CRYPTO_is_SSSE3_capable();
}
void sha1_block_data_order_ssse3(uint32_t *state, const uint8_t *data,
size_t num);
#define SHA256_ASM_HW
OPENSSL_INLINE int sha256_hw_capable(void) {
return CRYPTO_is_x86_SHA_capable();
}
#define SHA256_ASM_AVX
OPENSSL_INLINE int sha256_avx_capable(void) {
// TODO: Simplify this logic, which was extracted from the assembly:
// * Does AVX imply SSSE3?
// * sha256_block_data_order_avx does not seem to use SSSE3 instructions.
// Pre-Zen AMD CPUs had slow SHLD/SHRD; Zen added the SHA extension; see the
// discussion in sha1-586.pl.
return CRYPTO_is_AVX_capable() && CRYPTO_is_SSSE3_capable() &&
CRYPTO_is_intel_cpu();
}
void sha256_block_data_order_avx(uint32_t *state, const uint8_t *data,
size_t num);
#define SHA256_ASM_SSSE3
OPENSSL_INLINE int sha256_ssse3_capable(void) {
return CRYPTO_is_SSSE3_capable();
}
void sha256_block_data_order_ssse3(uint32_t *state, const uint8_t *data,
size_t num);
#define SHA512_ASM_AVX
OPENSSL_INLINE int sha512_avx_capable(void) {
// TODO: Simplify this logic, which was extracted from the assembly:
// * Does AVX imply SSSE3?
// * sha512_block_data_order_avx does not seem to use SSSE3 instructions.
// Pre-Zen AMD CPUs had slow SHLD/SHRD; Zen added the SHA extension; see the
// discussion in sha1-586.pl.
return CRYPTO_is_AVX_capable() && CRYPTO_is_SSSE3_capable() &&
CRYPTO_is_intel_cpu();
}
void sha512_block_data_order_avx(uint64_t *state, const uint8_t *data,
size_t num);
#endif
#if defined(SHA1_ASM_HW)
void sha1_block_data_order_hw(uint32_t *state, const uint8_t *data, size_t num);
#endif
#if defined(SHA1_ASM_NOHW)
void sha1_block_data_order_nohw(uint32_t *state, const uint8_t *data,
size_t num);
#endif
#if defined(SHA256_ASM_HW)
void sha256_block_data_order_hw(uint32_t *state, const uint8_t *data,
size_t num);
#endif
#if defined(SHA256_ASM_NOHW)
void sha256_block_data_order_nohw(uint32_t *state, const uint8_t *data,
size_t num);
#endif
#if defined(SHA512_ASM_HW)
void sha512_block_data_order_hw(uint64_t *state, const uint8_t *data,
size_t num);
#endif
#if defined(SHA512_ASM_NOHW)
void sha512_block_data_order_nohw(uint64_t *state, const uint8_t *data,
size_t num);
#endif
#if defined(__cplusplus)
} // extern "C"
src/crypto/fipsmodule/sha/sha1.c
+35 -2
View File
@@ -232,8 +232,10 @@ void CRYPTO_fips_186_2_prf(uint8_t *out, size_t out_len,
#define X(i) XX##i
#if !defined(SHA1_ASM)
static void sha1_block_data_order(uint32_t *state, const uint8_t *data,
size_t num) {
#if !defined(SHA1_ASM_NOHW)
static void sha1_block_data_order_nohw(uint32_t *state, const uint8_t *data,
size_t num) {
register uint32_t A, B, C, D, E, T;
uint32_t XX0, XX1, XX2, XX3, XX4, XX5, XX6, XX7, XX8, XX9, XX10,
XX11, XX12, XX13, XX14, XX15;
@@ -380,7 +382,38 @@ static void sha1_block_data_order(uint32_t *state, const uint8_t *data,
E = state[4];
}
}
#endif // !SHA1_ASM_NOHW
static void sha1_block_data_order(uint32_t *state, const uint8_t *data,
size_t num) {
#if defined(SHA1_ASM_HW)
if (sha1_hw_capable()) {
sha1_block_data_order_hw(state, data, num);
return;
}
#endif
#if defined(SHA1_ASM_AVX2)
if (sha1_avx2_capable()) {
sha1_block_data_order_avx(state, data, num);
return;
}
#endif
#if defined(SHA1_ASM_AVX)
if (sha1_avx_capable()) {
sha1_block_data_order_avx(state, data, num);
return;
}
#endif
#if defined(SHA1_ASM_SSSE3)
if (sha1_ssse3_capable()) {
sha1_block_data_order_ssse3(state, data, num);
return;
}
#endif
sha1_block_data_order_nohw(state, data, num);
}
#endif // !SHA1_ASM
#undef Xupdate
#undef K_00_19
src/crypto/fipsmodule/sha/sha256.c
+33 -5
View File
@@ -114,7 +114,7 @@ uint8_t *SHA256(const uint8_t *data, size_t len,
return out;
}
#ifndef SHA256_ASM
#if !defined(SHA256_ASM)
static void sha256_block_data_order(uint32_t *state, const uint8_t *in,
size_t num);
#endif
@@ -172,7 +172,9 @@ int SHA224_Final(uint8_t out[SHA224_DIGEST_LENGTH], SHA256_CTX *ctx) {
return sha256_final_impl(out, SHA224_DIGEST_LENGTH, ctx);
}
#ifndef SHA256_ASM
#if !defined(SHA256_ASM)
#if !defined(SHA256_ASM_NOHW)
static const uint32_t K256[64] = {
0x428a2f98UL, 0x71374491UL, 0xb5c0fbcfUL, 0xe9b5dba5UL, 0x3956c25bUL,
0x59f111f1UL, 0x923f82a4UL, 0xab1c5ed5UL, 0xd807aa98UL, 0x12835b01UL,
@@ -221,8 +223,8 @@ static const uint32_t K256[64] = {
ROUND_00_15(i, a, b, c, d, e, f, g, h); \
} while (0)
static void sha256_block_data_order(uint32_t *state, const uint8_t *data,
size_t num) {
static void sha256_block_data_order_nohw(uint32_t *state, const uint8_t *data,
size_t num) {
uint32_t a, b, c, d, e, f, g, h, s0, s1, T1;
uint32_t X[16];
int i;
@@ -308,7 +310,33 @@ static void sha256_block_data_order(uint32_t *state, const uint8_t *data,
}
}
#endif // !SHA256_ASM
#endif // !defined(SHA256_ASM_NOHW)
static void sha256_block_data_order(uint32_t *state, const uint8_t *data,
size_t num) {
#if defined(SHA256_ASM_HW)
if (sha256_hw_capable()) {
sha256_block_data_order_hw(state, data, num);
return;
}
#endif
#if defined(SHA256_ASM_AVX)
if (sha256_avx_capable()) {
sha256_block_data_order_avx(state, data, num);
return;
}
#endif
#if defined(SHA256_ASM_SSSE3)
if (sha256_ssse3_capable()) {
sha256_block_data_order_ssse3(state, data, num);
return;
}
#endif
sha256_block_data_order_nohw(state, data, num);
}
#endif // !defined(SHA256_ASM)
void SHA256_TransformBlocks(uint32_t state[8], const uint8_t *data,
size_t num_blocks) {
src/crypto/fipsmodule/sha/sha512.c
+26 -5
View File
@@ -279,7 +279,9 @@ static int sha512_final_impl(uint8_t *out, size_t md_len, SHA512_CTX *sha) {
return 1;
}
#ifndef SHA512_ASM
#if !defined(SHA512_ASM)
#if !defined(SHA512_ASM_NOHW)
static const uint64_t K512[80] = {
UINT64_C(0x428a2f98d728ae22), UINT64_C(0x7137449123ef65cd),
UINT64_C(0xb5c0fbcfec4d3b2f), UINT64_C(0xe9b5dba58189dbbc),
@@ -341,8 +343,8 @@ static const uint64_t K512[80] = {
#if defined(__i386) || defined(__i386__) || defined(_M_IX86)
// This code should give better results on 32-bit CPU with less than
// ~24 registers, both size and performance wise...
static void sha512_block_data_order(uint64_t *state, const uint8_t *in,
size_t num) {
static void sha512_block_data_order_nohw(uint64_t *state, const uint8_t *in,
size_t num) {
uint64_t A, E, T;
uint64_t X[9 + 80], *F;
int i;
@@ -414,8 +416,8 @@ static void sha512_block_data_order(uint64_t *state, const uint8_t *in,
ROUND_00_15(i + j, a, b, c, d, e, f, g, h); \
} while (0)
static void sha512_block_data_order(uint64_t *state, const uint8_t *in,
size_t num) {
static void sha512_block_data_order_nohw(uint64_t *state, const uint8_t *in,
size_t num) {
uint64_t a, b, c, d, e, f, g, h, s0, s1, T1;
uint64_t X[16];
int i;
@@ -498,6 +500,25 @@ static void sha512_block_data_order(uint64_t *state, const uint8_t *in,
#endif
#endif // !SHA512_ASM_NOHW
static void sha512_block_data_order(uint64_t *state, const uint8_t *data,
size_t num) {
#if defined(SHA512_ASM_HW)
if (sha512_hw_capable()) {
sha512_block_data_order_hw(state, data, num);
return;
}
#endif
#if defined(SHA512_ASM_AVX)
if (sha512_avx_capable()) {
sha512_block_data_order_avx(state, data, num);
return;
}
#endif
sha512_block_data_order_nohw(state, data, num);
}
#endif // !SHA512_ASM
#undef Sigma0
src/crypto/fipsmodule/sha/sha_test.cc
+77 -18
View File
@@ -42,41 +42,100 @@ TEST(SHATest, FIPS1862PRF) {
}
}
#if defined(SHA1_ASM) && defined(SUPPORTS_ABI_TEST)
#if defined(SUPPORTS_ABI_TEST)
TEST(SHATest, SHA1ABI) {
SHA_CTX ctx;
SHA1_Init(&ctx);
static const uint8_t kBuf[SHA_CBLOCK * 8] = {0};
CHECK_ABI(sha1_block_data_order, ctx.h, kBuf, 1);
CHECK_ABI(sha1_block_data_order, ctx.h, kBuf, 2);
CHECK_ABI(sha1_block_data_order, ctx.h, kBuf, 4);
CHECK_ABI(sha1_block_data_order, ctx.h, kBuf, 8);
for (size_t blocks : {1, 2, 4, 8}) {
#if defined(SHA1_ASM)
CHECK_ABI(sha1_block_data_order, ctx.h, kBuf, blocks);
#endif
#if defined(SHA1_ASM_HW)
if (sha1_hw_capable()) {
CHECK_ABI(sha1_block_data_order_hw, ctx.h, kBuf, blocks);
}
#endif
#if defined(SHA1_ASM_AVX2)
if (sha1_avx2_capable()) {
CHECK_ABI(sha1_block_data_order_avx2, ctx.h, kBuf, blocks);
}
#endif
#if defined(SHA1_ASM_AVX)
if (sha1_avx_capable()) {
CHECK_ABI(sha1_block_data_order_avx, ctx.h, kBuf, blocks);
return;
}
#endif
#if defined(SHA1_ASM_SSSE3)
if (sha1_ssse3_capable()) {
CHECK_ABI(sha1_block_data_order_ssse3, ctx.h, kBuf, blocks);
return;
}
#endif
#if defined(SHA1_ASM_NOHW)
CHECK_ABI(sha1_block_data_order_nohw, ctx.h, kBuf, blocks);
#endif
}
}
#endif // SHA1_ASM && SUPPORTS_ABI_TEST
#if defined(SHA256_ASM) && defined(SUPPORTS_ABI_TEST)
TEST(SHATest, SHA256ABI) {
SHA256_CTX ctx;
SHA256_Init(&ctx);
static const uint8_t kBuf[SHA256_CBLOCK * 8] = {0};
CHECK_ABI(sha256_block_data_order, ctx.h, kBuf, 1);
CHECK_ABI(sha256_block_data_order, ctx.h, kBuf, 2);
CHECK_ABI(sha256_block_data_order, ctx.h, kBuf, 4);
CHECK_ABI(sha256_block_data_order, ctx.h, kBuf, 8);
for (size_t blocks : {1, 2, 4, 8}) {
#if defined(SHA256_ASM)
CHECK_ABI(sha256_block_data_order, ctx.h, kBuf, blocks);
#endif
#if defined(SHA256_ASM_HW)
if (sha256_hw_capable()) {
CHECK_ABI(sha256_block_data_order_hw, ctx.h, kBuf, blocks);
}
#endif
#if defined(SHA256_ASM_AVX)
if (sha256_avx_capable()) {
CHECK_ABI(sha256_block_data_order_avx, ctx.h, kBuf, blocks);
return;
}
#endif
#if defined(SHA256_ASM_SSSE3)
if (sha256_ssse3_capable()) {
CHECK_ABI(sha256_block_data_order_ssse3, ctx.h, kBuf, blocks);
return;
}
#endif
#if defined(SHA256_ASM_NOHW)
CHECK_ABI(sha256_block_data_order_nohw, ctx.h, kBuf, blocks);
#endif
}
}
#endif // SHA256_ASM && SUPPORTS_ABI_TEST
#if defined(SHA512_ASM) && defined(SUPPORTS_ABI_TEST)
TEST(SHATest, SHA512ABI) {
SHA512_CTX ctx;
SHA512_Init(&ctx);
static const uint8_t kBuf[SHA512_CBLOCK * 4] = {0};
CHECK_ABI(sha512_block_data_order, ctx.h, kBuf, 1);
CHECK_ABI(sha512_block_data_order, ctx.h, kBuf, 2);
CHECK_ABI(sha512_block_data_order, ctx.h, kBuf, 3);
CHECK_ABI(sha512_block_data_order, ctx.h, kBuf, 4);
for (size_t blocks : {1, 2, 3, 4}) {
#if defined(SHA512_ASM)
CHECK_ABI(sha512_block_data_order, ctx.h, kBuf, blocks);
#endif
#if defined(SHA512_ASM_HW)
if (sha512_hw_capable()) {
CHECK_ABI(sha512_block_data_order_hw, ctx.h, kBuf, blocks);
}
#endif
#if defined(SHA512_ASM_AVX)
if (sha512_avx_capable()) {
CHECK_ABI(sha512_block_data_order_avx, ctx.h, kBuf, blocks);
}
#endif
#if defined(SHA512_ASM_NOHW)
CHECK_ABI(sha512_block_data_order_nohw, ctx.h, kBuf, blocks);
#endif
}
}
#endif // SHA512_ASM && SUPPORTS_ABI_TEST
#endif // SUPPORTS_ABI_TEST
src/crypto/internal.h
+44
View File
@@ -1450,6 +1450,15 @@ OPENSSL_INLINE int CRYPTO_is_ADX_capable(void) {
#endif
}
// SHA-1 and SHA-256 are defined as a single extension.
OPENSSL_INLINE int CRYPTO_is_x86_SHA_capable(void) {
#if defined(__SHA__)
return 1;
#else
return (OPENSSL_get_ia32cap(2) & (1u << 29)) != 0;
#endif
}
#endif // OPENSSL_X86 || OPENSSL_X86_64
#if defined(OPENSSL_ARM) || defined(OPENSSL_AARCH64)
@@ -1519,6 +1528,41 @@ OPENSSL_INLINE int CRYPTO_is_ARMv8_PMULL_capable(void) {
#endif
}
OPENSSL_INLINE int CRYPTO_is_ARMv8_SHA1_capable(void) {
// SHA-1 and SHA-2 (only) share |__ARM_FEATURE_SHA2| but otherwise
// are dealt with independently.
#if defined(OPENSSL_STATIC_ARMCAP_SHA1) || defined(__ARM_FEATURE_SHA2)
return 1;
#elif defined(OPENSSL_STATIC_ARMCAP)
return 0;
#else
return (OPENSSL_get_armcap() & ARMV8_SHA1) != 0;
#endif
}
OPENSSL_INLINE int CRYPTO_is_ARMv8_SHA256_capable(void) {
// SHA-1 and SHA-2 (only) share |__ARM_FEATURE_SHA2| but otherwise
// are dealt with independently.
#if defined(OPENSSL_STATIC_ARMCAP_SHA256) || defined(__ARM_FEATURE_SHA2)
return 1;
#elif defined(OPENSSL_STATIC_ARMCAP)
return 0;
#else
return (OPENSSL_get_armcap() & ARMV8_SHA256) != 0;
#endif
}
OPENSSL_INLINE int CRYPTO_is_ARMv8_SHA512_capable(void) {
// There is no |OPENSSL_STATIC_ARMCAP_SHA512|.
#if defined(__ARM_FEATURE_SHA512)
return 1;
#elif defined(OPENSSL_STATIC_ARMCAP)
return 0;
#else
return (OPENSSL_get_armcap() & ARMV8_SHA512) != 0;
#endif
}
#endif // OPENSSL_ARM || OPENSSL_AARCH64
#if defined(BORINGSSL_DISPATCH_TEST)
win-aarch64/crypto/fipsmodule/sha1-armv8-win.S
+7 -16
View File
@@ -8,25 +8,15 @@
.text
.globl sha1_block_data_order_nohw
.globl sha1_block_data_order
.def sha1_block_data_order
.def sha1_block_data_order_nohw
.type 32
.endef
.align 6
sha1_block_data_order:
sha1_block_data_order_nohw:
// Armv8.3-A PAuth: even though x30 is pushed to stack it is not popped later.
AARCH64_VALID_CALL_TARGET
#if defined(OPENSSL_HWASAN) && __clang_major__ >= 10
adrp x16,:pg_hi21_nc:OPENSSL_armcap_P
#else
adrp x16,OPENSSL_armcap_P
#endif
ldr w16,[x16,:lo12:OPENSSL_armcap_P]
tst w16,#ARMV8_SHA1
b.ne Lv8_entry
stp x29,x30,[sp,#-96]!
add x29,sp,#0
@@ -1083,14 +1073,15 @@ Loop:
ldr x29,[sp],#96
ret
.def sha1_block_armv8
.globl sha1_block_data_order_hw
.def sha1_block_data_order_hw
.type 32
.endef
.align 6
sha1_block_armv8:
sha1_block_data_order_hw:
// Armv8.3-A PAuth: even though x30 is pushed to stack it is not popped later.
AARCH64_VALID_CALL_TARGET
Lv8_entry:
stp x29,x30,[sp,#-16]!
add x29,sp,#0
win-aarch64/crypto/fipsmodule/sha256-armv8-win.S
+8 -19
View File
@@ -50,26 +50,13 @@
.text
.globl sha256_block_data_order_nohw
.globl sha256_block_data_order
.def sha256_block_data_order
.def sha256_block_data_order_nohw
.type 32
.endef
.align 6
sha256_block_data_order:
AARCH64_VALID_CALL_TARGET
#ifndef __KERNEL__
#if defined(OPENSSL_HWASAN) && __clang_major__ >= 10
adrp x16,:pg_hi21_nc:OPENSSL_armcap_P
#else
adrp x16,OPENSSL_armcap_P
#endif
ldr w16,[x16,:lo12:OPENSSL_armcap_P]
tst w16,#ARMV8_SHA256
b.ne Lv8_entry
#endif
sha256_block_data_order_nohw:
AARCH64_SIGN_LINK_REGISTER
stp x29,x30,[sp,#-128]!
add x29,sp,#0
@@ -1062,13 +1049,15 @@ LK256:
.align 2
.text
#ifndef __KERNEL__
.def sha256_block_armv8
.globl sha256_block_data_order_hw
.def sha256_block_data_order_hw
.type 32
.endef
.align 6
sha256_block_armv8:
Lv8_entry:
sha256_block_data_order_hw:
// Armv8.3-A PAuth: even though x30 is pushed to stack it is not popped later.
AARCH64_VALID_CALL_TARGET
stp x29,x30,[sp,#-16]!
add x29,sp,#0
win-aarch64/crypto/fipsmodule/sha512-armv8-win.S
+9 -19
View File
@@ -50,26 +50,13 @@
.text
.globl sha512_block_data_order_nohw
.globl sha512_block_data_order
.def sha512_block_data_order
.def sha512_block_data_order_nohw
.type 32
.endef
.align 6
sha512_block_data_order:
AARCH64_VALID_CALL_TARGET
#ifndef __KERNEL__
#if defined(OPENSSL_HWASAN) && __clang_major__ >= 10
adrp x16,:pg_hi21_nc:OPENSSL_armcap_P
#else
adrp x16,OPENSSL_armcap_P
#endif
ldr w16,[x16,:lo12:OPENSSL_armcap_P]
tst w16,#ARMV8_SHA512
b.ne Lv8_entry
#endif
sha512_block_data_order_nohw:
AARCH64_SIGN_LINK_REGISTER
stp x29,x30,[sp,#-128]!
add x29,sp,#0
@@ -1086,12 +1073,15 @@ LK512:
.align 2
.text
#ifndef __KERNEL__
.def sha512_block_armv8
.globl sha512_block_data_order_hw
.def sha512_block_data_order_hw
.type 32
.endef
.align 6
sha512_block_armv8:
Lv8_entry:
sha512_block_data_order_hw:
// Armv8.3-A PAuth: even though x30 is pushed to stack it is not popped later.
AARCH64_VALID_CALL_TARGET
stp x29,x30,[sp,#-16]!
add x29,sp,#0
win-x86_64/crypto/fipsmodule/sha1-x86_64-win.asm
+23 -40
View File
@@ -13,16 +13,15 @@ default rel
%endif
section .text code align=64
EXTERN OPENSSL_ia32cap_P
global sha1_block_data_order
global sha1_block_data_order_nohw
ALIGN 16
sha1_block_data_order:
sha1_block_data_order_nohw:
mov QWORD[8+rsp],rdi ;WIN64 prologue
mov QWORD[16+rsp],rsi
mov rax,rsp
$L$SEH_begin_sha1_block_data_order:
$L$SEH_begin_sha1_block_data_order_nohw:
mov rdi,rcx
mov rsi,rdx
mov rdx,r8
@@ -30,26 +29,6 @@ $L$SEH_begin_sha1_block_data_order:
_CET_ENDBR
lea r10,[OPENSSL_ia32cap_P]
mov r9d,DWORD[r10]
mov r8d,DWORD[4+r10]
mov r10d,DWORD[8+r10]
test r8d,512
jz NEAR $L$ialu
test r10d,536870912
jnz NEAR _shaext_shortcut
and r10d,296
cmp r10d,296
je NEAR _avx2_shortcut
and r8d,268435456
and r9d,1073741824
or r8d,r9d
cmp r8d,1342177280
je NEAR _avx_shortcut
jmp NEAR _ssse3_shortcut
ALIGN 16
$L$ialu:
mov rax,rsp
push rbx
@@ -1281,21 +1260,22 @@ $L$epilogue:
mov rsi,QWORD[16+rsp]
ret
$L$SEH_end_sha1_block_data_order:
$L$SEH_end_sha1_block_data_order_nohw:
global sha1_block_data_order_hw
ALIGN 32
sha1_block_data_order_shaext:
sha1_block_data_order_hw:
mov QWORD[8+rsp],rdi ;WIN64 prologue
mov QWORD[16+rsp],rsi
mov rax,rsp
$L$SEH_begin_sha1_block_data_order_shaext:
$L$SEH_begin_sha1_block_data_order_hw:
mov rdi,rcx
mov rsi,rdx
mov rdx,r8
_shaext_shortcut:
_CET_ENDBR
lea rsp,[((-72))+rsp]
movaps XMMWORD[(-8-64)+rax],xmm6
movaps XMMWORD[(-8-48)+rax],xmm7
@@ -1474,7 +1454,8 @@ $L$epilogue_shaext:
mov rsi,QWORD[16+rsp]
ret
$L$SEH_end_sha1_block_data_order_shaext:
$L$SEH_end_sha1_block_data_order_hw:
global sha1_block_data_order_ssse3
ALIGN 16
sha1_block_data_order_ssse3:
@@ -1487,8 +1468,8 @@ $L$SEH_begin_sha1_block_data_order_ssse3:
mov rdx,r8
_ssse3_shortcut:
_CET_ENDBR
mov r11,rsp
push rbx
@@ -2687,6 +2668,7 @@ $L$epilogue_ssse3:
ret
$L$SEH_end_sha1_block_data_order_ssse3:
global sha1_block_data_order_avx
ALIGN 16
sha1_block_data_order_avx:
@@ -2699,8 +2681,8 @@ $L$SEH_begin_sha1_block_data_order_avx:
mov rdx,r8
_avx_shortcut:
_CET_ENDBR
mov r11,rsp
push rbx
@@ -3839,6 +3821,7 @@ $L$epilogue_avx:
ret
$L$SEH_end_sha1_block_data_order_avx:
global sha1_block_data_order_avx2
ALIGN 16
sha1_block_data_order_avx2:
@@ -3851,8 +3834,8 @@ $L$SEH_begin_sha1_block_data_order_avx2:
mov rdx,r8
_avx2_shortcut:
_CET_ENDBR
mov r11,rsp
push rbx
@@ -5744,12 +5727,12 @@ $L$common_seh_tail:
section .pdata rdata align=4
ALIGN 4
DD $L$SEH_begin_sha1_block_data_order wrt ..imagebase
DD $L$SEH_end_sha1_block_data_order wrt ..imagebase
DD $L$SEH_info_sha1_block_data_order wrt ..imagebase
DD $L$SEH_begin_sha1_block_data_order_shaext wrt ..imagebase
DD $L$SEH_end_sha1_block_data_order_shaext wrt ..imagebase
DD $L$SEH_info_sha1_block_data_order_shaext wrt ..imagebase
DD $L$SEH_begin_sha1_block_data_order_nohw wrt ..imagebase
DD $L$SEH_end_sha1_block_data_order_nohw wrt ..imagebase
DD $L$SEH_info_sha1_block_data_order_nohw wrt ..imagebase
DD $L$SEH_begin_sha1_block_data_order_hw wrt ..imagebase
DD $L$SEH_end_sha1_block_data_order_hw wrt ..imagebase
DD $L$SEH_info_sha1_block_data_order_hw wrt ..imagebase
DD $L$SEH_begin_sha1_block_data_order_ssse3 wrt ..imagebase
DD $L$SEH_end_sha1_block_data_order_ssse3 wrt ..imagebase
DD $L$SEH_info_sha1_block_data_order_ssse3 wrt ..imagebase
@@ -5761,10 +5744,10 @@ ALIGN 4
DD $L$SEH_info_sha1_block_data_order_avx2 wrt ..imagebase
section .xdata rdata align=8
ALIGN 8
$L$SEH_info_sha1_block_data_order:
$L$SEH_info_sha1_block_data_order_nohw:
DB 9,0,0,0
DD se_handler wrt ..imagebase
$L$SEH_info_sha1_block_data_order_shaext:
$L$SEH_info_sha1_block_data_order_hw:
DB 9,0,0,0
DD shaext_handler wrt ..imagebase
$L$SEH_info_sha1_block_data_order_ssse3:
win-x86_64/crypto/fipsmodule/sha256-x86_64-win.asm
+21 -32
View File
@@ -14,15 +14,14 @@ default rel
section .text code align=64
EXTERN OPENSSL_ia32cap_P
global sha256_block_data_order
global sha256_block_data_order_nohw
ALIGN 16
sha256_block_data_order:
sha256_block_data_order_nohw:
mov QWORD[8+rsp],rdi ;WIN64 prologue
mov QWORD[16+rsp],rsi
mov rax,rsp
$L$SEH_begin_sha256_block_data_order:
$L$SEH_begin_sha256_block_data_order_nohw:
mov rdi,rcx
mov rsi,rdx
mov rdx,r8
@@ -30,19 +29,6 @@ $L$SEH_begin_sha256_block_data_order:
_CET_ENDBR
lea r11,[OPENSSL_ia32cap_P]
mov r9d,DWORD[r11]
mov r10d,DWORD[4+r11]
mov r11d,DWORD[8+r11]
test r11d,536870912
jnz NEAR $L$shaext_shortcut
and r9d,1073741824
and r10d,268435968
or r10d,r9d
cmp r10d,1342177792
je NEAR $L$avx_shortcut
test r10d,512
jnz NEAR $L$ssse3_shortcut
mov rax,rsp
push rbx
@@ -1750,7 +1736,7 @@ $L$epilogue:
mov rsi,QWORD[16+rsp]
ret
$L$SEH_end_sha256_block_data_order:
$L$SEH_end_sha256_block_data_order_nohw:
section .rdata rdata align=8
ALIGN 64
@@ -1801,20 +1787,21 @@ K256:
DB 111,114,103,62,0
section .text
global sha256_block_data_order_hw
ALIGN 64
sha256_block_data_order_shaext:
sha256_block_data_order_hw:
mov QWORD[8+rsp],rdi ;WIN64 prologue
mov QWORD[16+rsp],rsi
mov rax,rsp
$L$SEH_begin_sha256_block_data_order_shaext:
$L$SEH_begin_sha256_block_data_order_hw:
mov rdi,rcx
mov rsi,rdx
mov rdx,r8
$L$shaext_shortcut:
_CET_ENDBR
lea rsp,[((-88))+rsp]
movaps XMMWORD[(-8-80)+rax],xmm6
movaps XMMWORD[(-8-64)+rax],xmm7
@@ -2034,7 +2021,8 @@ $L$epilogue_shaext:
mov rsi,QWORD[16+rsp]
ret
$L$SEH_end_sha256_block_data_order_shaext:
$L$SEH_end_sha256_block_data_order_hw:
global sha256_block_data_order_ssse3
ALIGN 64
sha256_block_data_order_ssse3:
@@ -2048,7 +2036,7 @@ $L$SEH_begin_sha256_block_data_order_ssse3:
$L$ssse3_shortcut:
_CET_ENDBR
mov rax,rsp
push rbx
@@ -3167,6 +3155,7 @@ $L$epilogue_ssse3:
ret
$L$SEH_end_sha256_block_data_order_ssse3:
global sha256_block_data_order_avx
ALIGN 64
sha256_block_data_order_avx:
@@ -3180,7 +3169,7 @@ $L$SEH_begin_sha256_block_data_order_avx:
$L$avx_shortcut:
_CET_ENDBR
mov rax,rsp
push rbx
@@ -4391,12 +4380,12 @@ shaext_handler:
section .pdata rdata align=4
ALIGN 4
DD $L$SEH_begin_sha256_block_data_order wrt ..imagebase
DD $L$SEH_end_sha256_block_data_order wrt ..imagebase
DD $L$SEH_info_sha256_block_data_order wrt ..imagebase
DD $L$SEH_begin_sha256_block_data_order_shaext wrt ..imagebase
DD $L$SEH_end_sha256_block_data_order_shaext wrt ..imagebase
DD $L$SEH_info_sha256_block_data_order_shaext wrt ..imagebase
DD $L$SEH_begin_sha256_block_data_order_nohw wrt ..imagebase
DD $L$SEH_end_sha256_block_data_order_nohw wrt ..imagebase
DD $L$SEH_info_sha256_block_data_order_nohw wrt ..imagebase
DD $L$SEH_begin_sha256_block_data_order_hw wrt ..imagebase
DD $L$SEH_end_sha256_block_data_order_hw wrt ..imagebase
DD $L$SEH_info_sha256_block_data_order_hw wrt ..imagebase
DD $L$SEH_begin_sha256_block_data_order_ssse3 wrt ..imagebase
DD $L$SEH_end_sha256_block_data_order_ssse3 wrt ..imagebase
DD $L$SEH_info_sha256_block_data_order_ssse3 wrt ..imagebase
@@ -4405,11 +4394,11 @@ ALIGN 4
DD $L$SEH_info_sha256_block_data_order_avx wrt ..imagebase
section .xdata rdata align=8
ALIGN 8
$L$SEH_info_sha256_block_data_order:
$L$SEH_info_sha256_block_data_order_nohw:
DB 9,0,0,0
DD se_handler wrt ..imagebase
DD $L$prologue wrt ..imagebase,$L$epilogue wrt ..imagebase
$L$SEH_info_sha256_block_data_order_shaext:
$L$SEH_info_sha256_block_data_order_hw:
DB 9,0,0,0
DD shaext_handler wrt ..imagebase
$L$SEH_info_sha256_block_data_order_ssse3:
win-x86_64/crypto/fipsmodule/sha512-x86_64-win.asm
+10 -19
View File
@@ -14,15 +14,14 @@ default rel
section .text code align=64
EXTERN OPENSSL_ia32cap_P
global sha512_block_data_order
global sha512_block_data_order_nohw
ALIGN 16
sha512_block_data_order:
sha512_block_data_order_nohw:
mov QWORD[8+rsp],rdi ;WIN64 prologue
mov QWORD[16+rsp],rsi
mov rax,rsp
$L$SEH_begin_sha512_block_data_order:
$L$SEH_begin_sha512_block_data_order_nohw:
mov rdi,rcx
mov rsi,rdx
mov rdx,r8
@@ -30,15 +29,6 @@ $L$SEH_begin_sha512_block_data_order:
_CET_ENDBR
lea r11,[OPENSSL_ia32cap_P]
mov r9d,DWORD[r11]
mov r10d,DWORD[4+r11]
mov r11d,DWORD[8+r11]
and r9d,1073741824
and r10d,268435968
or r10d,r9d
cmp r10d,1342177792
je NEAR $L$avx_shortcut
mov rax,rsp
push rbx
@@ -1746,7 +1736,7 @@ $L$epilogue:
mov rsi,QWORD[16+rsp]
ret
$L$SEH_end_sha512_block_data_order:
$L$SEH_end_sha512_block_data_order_nohw:
section .rdata rdata align=8
ALIGN 64
@@ -1841,6 +1831,7 @@ K512:
DB 111,114,103,62,0
section .text
global sha512_block_data_order_avx
ALIGN 64
sha512_block_data_order_avx:
@@ -1854,7 +1845,7 @@ $L$SEH_begin_sha512_block_data_order_avx:
$L$avx_shortcut:
_CET_ENDBR
mov rax,rsp
push rbx
@@ -3127,15 +3118,15 @@ $L$in_prologue:
section .pdata rdata align=4
ALIGN 4
DD $L$SEH_begin_sha512_block_data_order wrt ..imagebase
DD $L$SEH_end_sha512_block_data_order wrt ..imagebase
DD $L$SEH_info_sha512_block_data_order wrt ..imagebase
DD $L$SEH_begin_sha512_block_data_order_nohw wrt ..imagebase
DD $L$SEH_end_sha512_block_data_order_nohw wrt ..imagebase
DD $L$SEH_info_sha512_block_data_order_nohw wrt ..imagebase
DD $L$SEH_begin_sha512_block_data_order_avx wrt ..imagebase
DD $L$SEH_end_sha512_block_data_order_avx wrt ..imagebase
DD $L$SEH_info_sha512_block_data_order_avx wrt ..imagebase
section .xdata rdata align=8
ALIGN 8
$L$SEH_info_sha512_block_data_order:
$L$SEH_info_sha512_block_data_order_nohw:
DB 9,0,0,0
DD se_handler wrt ..imagebase
DD $L$prologue wrt ..imagebase,$L$epilogue wrt ..imagebase