kernel-zhihe-a210/arch/riscv/boot/dts/zhihe/a210-platform-d2d.dtsi

/ {
	soc {
		d2d: d2d@0 {
			compatible = "zhihe,d2d";
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;
			nr_dies = <4>;
			status = "okay";

			d2d_ctrl0: d2d_ctrl@9080000 {
				compatible = "zhihe,d2d-ctrl";
				reg = <0x00 0x09080000 0x0 0x400>;
				interrupt-parent = <&intc>;
				interrupts = <47>;
			};

			d2d_ctrl1: d2d_ctrl@90c0000 {
				compatible = "zhihe,d2d-ctrl";
				reg = <0x00 0x090c0000 0x0 0x400>;
				interrupt-parent = <&intc>;
				interrupts = <48>;
			};

			d2d_phy0: d2d_phy@9100000 {
				compatible = "zhihe,d2d-phy";
				reg = <0x00 0x09100000 0x0 0x2000>;
				clocks = <&clk TOP_D2D_REF_CLK_MUX>;
			};

			d2d_phy1: d2d_phy@9140000 {
				compatible = "zhihe,d2d-phy";
				reg = <0x00 0x09140000 0x0 0x2000>;
			};
		};

		d2d_die1: d2d@2000000000 {
			compatible = "zhihe,d2d";
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;
			status = "okay";

			die1_d2d_ctrl0: die1_d2d_ctrl@2009080000 {
				compatible = "zhihe,d2d-ctrl";
				reg = <0x20 0x09080000 0x0 0x400>;
				interrupt-parent = <&intc_die1>;
				interrupts = <47>;
			};

			die1_d2d_ctrl1: die1_d2d_ctrl@20090c0000 {
				compatible = "zhihe,d2d-ctrl";
				reg = <0x20 0x090c0000 0x0 0x400>;
				interrupt-parent = <&intc_die1>;
				interrupts = <48>;
			};

			die1_d2d_phy0: die1_d2d_phy@2009100000 {
				compatible = "zhihe,d2d-phy";
				reg = <0x20 0x09100000 0x0 0x2000>;
				clocks = <&clk_die1 TOP_D2D_REF_CLK_MUX>;
			};

			die1_d2d_phy1: die1_d2d_phy@2009140000 {
				compatible = "zhihe,d2d-phy";
				reg = <0x20 0x09140000 0x0 0x2000>;
			};
		};
	};
};

/* DIE0 */
&uart0 {
	status = "disabled";
};

&uart1 {
	status = "disabled";
};

&uart2 {
	status = "disabled";
};

&uart3 {
	status = "disabled";
};

&uart5 {
	status = "disabled";
};

&uart6 {
	status = "disabled";
};

&uart7 {
	status = "disabled";
};

&uart8 {
	status = "disabled";
};

&uart9 {
	status = "disabled";
};

&spi0 {
	status = "disabled";
};

&spi1 {
	status = "disabled";
};

&i2c0 {
	status = "disabled";
};

&i2c1 {
	status = "disabled";
};

&i2c2 {
	status = "disabled";
};

&i2c3 {
	status = "disabled";
};

&i2c4 {
	status = "disabled";
};

&i2c5 {
	status = "disabled";
};

&i2c6 {
	status = "disabled";
};

&i2c7 {
	status = "disabled";
};

&pwm0 {
	status = "disabled";
};

&pwm1 {
	status = "disabled";
};

&pwm2 {
	status = "disabled";
};

&audio_i2s0 {
	status = "disabled";
};

&audio_i2s1 {
	status = "disabled";
};

&audio_i2s2 {
	status = "disabled";
};

&audio_i2s_8ch_sd1 {
	status = "disabled";
};

&audio_i2s_8ch_sd2 {
	status = "disabled";
};

&audio_i2s_8ch_sd3 {
	status = "disabled";
};

&audio_pdm0 {
	status = "disabled";
};

&peri3_padctrl {
	status = "disabled";
};

&gpio1 {
	status = "disabled";
};

&gpio4 {
	status = "disabled";
};

&gmac1 {
	status = "disabled";
};

&mdio1 {
	status = "disabled";
};

&can0 {
	status = "disabled";
};

&can1 {
	status = "disabled";
};

&can2 {
	status = "disabled";
};

&dmac1 {
	status = "disabled";
};

&timer0 {
	status = "disabled";
};

&timer1 {
	status = "disabled";
};

&timer3 {
	status = "disabled";
};

&timer4 {
	status = "disabled";
};

&timer5 {
	status = "disabled";
};

&timer6 {
	status = "disabled";
};

&timer7 {
	status = "disabled";
};

&dm3x4 {
	status = "disabled";
};

&rp3x1 {
	status = "disabled";
};

&usb2_0 {
  status = "disabled";
};

&usb31 {
	status = "disabled";
};

&sata {
	status = "disabled";
};

&dsi_host0 {
	status = "disabled";
};

&adc {
	status = "disabled";
};

&rtc {
	status = "disabled";
};

&dfmu_mt_vp {
	status = "disabled";
};

&dfmu_mt_npu {
	status = "disabled";
};

&dfmu_mt_vi {
	status = "disabled";
};

&dfmu_mt_vo {
	status = "disabled";
};

&dfmu_mt_peri1 {
	status = "disabled";
};

&dfmu_mt_pcie {
	status = "disabled";
};

&dfmu_mt_usb {
	status = "disabled";
};

&vidmem {
	status = "disabled";
};

/* DIE1 */
&uart4_die1 {
	status = "disabled";
};

&auxdisp {
	status = "disabled";
};

&dpu_enc0 {
	status = "disabled";
};