OERV-BSP/kernel-zhihe-a210
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Release develop 251114

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This commit is contained in:
hongyi
2025-11-14 16:33:50 +08:00
parent b37a325037
commit 47c96ca1c2
26 changed files with 1066 additions and 142 deletions
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1
arch/riscv/Kconfig.socs
View File

@@ -34,6 +34,7 @@ config SOC_STARFIVE
config ARCH_ZHIHE
bool "ZhiHe SoCs"
select CLOCKSOURCE_VALIDATE_LAST_CYCLE
help
This enables support for ZhiHe SoC platform hardware.

50
arch/riscv/boot/dts/zhihe/a210-dev.dts
View File

@@ -140,7 +140,7 @@
compatible = "wlan-platdata";
WIFI,vcc1-gpios = <&aw9535_1 11 GPIO_ACTIVE_HIGH>;
WIFI,vcc2-gpios = <&aw9535_1 12 GPIO_ACTIVE_HIGH>;
WIFI,poweren-gpios = <&gpio0_porta 14 GPIO_ACTIVE_HIGH>;
WIFI,poweren-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
power_on_after_init;
power_on_when_resume;
status = "okay";
@@ -148,7 +148,7 @@
wcn_bt: wireless-bluetooth {
compatible = "bluetooth-platdata";
BT,power-gpios = <&ao_gpio1_porta 4 GPIO_ACTIVE_HIGH>;
BT,power-gpios = <&ao_gpio1 4 GPIO_ACTIVE_HIGH>;
status = "okay";
};
@@ -270,7 +270,7 @@
dvdd08_ddr_reg: dvdd08_ddr {
regulator-name = "dvdd08_ddr";
regulator-type = "voltage";
regulator-settling-time-us = <1000>;
regulator-ramp-delay = <100>;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <800000>;
regulator-always-on;
@@ -279,7 +279,7 @@
dvdd_cpu_reg: dvdd_cpu {
regulator-name = "dvdd_cpu";
regulator-type = "voltage";
regulator-settling-time-us = <1000>;
regulator-ramp-delay = <100>;
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
@@ -288,7 +288,7 @@
dvddm_cpu_reg: dvddm_cpu {
regulator-name = "dvddm_cpu";
regulator-type = "voltage";
regulator-settling-time-us = <1000>;
regulator-ramp-delay = <100>;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
@@ -297,7 +297,7 @@
dvdd_vp_reg: dvdd_vp {
regulator-name = "dvdd_vp";
regulator-type = "voltage";
regulator-settling-time-us = <1000>;
regulator-ramp-delay = <100>;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <800000>;
regulator-always-on;
@@ -306,7 +306,7 @@
dvdd_npu_vip_reg: dvdd_npu_vip {
regulator-name = "dvdd_npu_vip";
regulator-type = "voltage";
regulator-settling-time-us = <1000>;
regulator-ramp-delay = <100>;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
@@ -315,7 +315,7 @@
dvdd_cpu_p_reg: dvdd_cpu_p {
regulator-name = "dvdd_cpu_p";
regulator-type = "voltage";
regulator-settling-time-us = <1000>;
regulator-ramp-delay = <100>;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
@@ -324,13 +324,24 @@
dvdd_gpu_reg: dvdd_gpu {
regulator-name = "dvdd_gpu";
regulator-type = "voltage";
regulator-settling-time-us = <1000>;
regulator-ramp-delay = <100>;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <800000>;
regulator-always-on;
};
};
cpufreq: a210_cpufreq {
compatible = "zhihe,a210-cpufreq";
clocks = <&clk TOP_CPUSYS_BUS_CLK_DIV>,
<&clk TOP_CPUSYS_PIC_CLK_DIV>,
<&clk TOP_CPUSYS_CFG_ACLK_DIV>,
<&clk TOP_CPUSYS_COM_APB_CLK_DIV>,
<&clk TOP_CPUSYS_APB_CLK_DIV>;
clock-names = "bus_clk", "pic_clk", "cfg_clk", "com_clk", "apb_clk";
status = "okay";
};
};
&aon_padctrl {
@@ -712,7 +723,7 @@
};
&qspi0 {
cs-gpios = <&gpio0_porta 19 0>;
cs-gpios = <&gpio0 19 0>;
rx-sample-dly = <2>;
spi-swap-data = <1>;
spi-max-frequency = <55000000>;
@@ -742,7 +753,7 @@
pinctrl-0 = <&rtc_pins>;
compatible = "nxp,pcf8563";
reg = <0x51>;
interrupt-parent = <&ao_gpio0_porta>;
interrupt-parent = <&ao_gpio0>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
wakeup-source;
};
@@ -986,16 +997,16 @@
&emmc {
max-frequency = <196608000>;
non-removable;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
cap-mmc-highspeed;
mmc-hs200-1_8v;
io_fixed_1v8;
is_emmc;
no-sdio;
no-sd;
pull_up;
bus-width = <8>;
cap-mmc-highspeed;
clk-delay-mmc-hs200 = <60>;
};
&sdhci0 {
@@ -1023,7 +1034,7 @@
&usb3 {
pinctrl-names = "default";
pinctrl-0 = <&usb3_pins>;
typec-pwren-gpios = <&gpio0_porta 27 GPIO_ACTIVE_HIGH>;
typec-pwren-gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>;
};
&sata {
@@ -1096,3 +1107,12 @@
};
};
};
&c920_4 {
dvdd-cpu-p-supply = <&dvdd_cpu_p_reg>;
};
&c908_0 {
dvdd-cpu-supply = <&dvdd_cpu_reg>;
dvddm-cpu-supply = <&dvddm_cpu_reg>;
};

14
arch/riscv/boot/dts/zhihe/a210-evb-d2d.dts
View File

@@ -227,16 +227,16 @@
&emmc {
max-frequency = <196608000>;
non-removable;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
cap-mmc-highspeed;
mmc-hs200-1_8v;
io_fixed_1v8;
is_emmc;
no-sdio;
no-sd;
pull_up;
bus-width = <8>;
cap-mmc-highspeed;
clk-delay-mmc-hs200 = <60>;
};
&sdhci0 {
@@ -252,7 +252,7 @@
};
&qspi0 {
cs-gpios = <&gpio0_porta 19 0>;
cs-gpios = <&gpio0 19 0>;
rx-sample-dly = <2>;
spi-swap-data = <1>;
spi-max-frequency = <55000000>;
@@ -272,7 +272,7 @@
};
&qspi1 {
cs-gpios = <&gpio2_porta 29 0>;
cs-gpios = <&gpio2 29 0>;
rx-sample-dly = <2>;
spi-swap-data = <1>;
spi-max-frequency = <55000000>;
@@ -348,7 +348,7 @@
};
&qspi0_die1 {
cs-gpios = <&gpio0_porta_die1 19 0>;
cs-gpios = <&gpio0_die1 19 0>;
rx-sample-dly = <2>;
spi-swap-data = <1>;
spi-max-frequency = <55000000>;
@@ -368,7 +368,7 @@
};
&qspi1_die1 {
cs-gpios = <&gpio2_porta_die1 29 0>;
cs-gpios = <&gpio2_die1 29 0>;
rx-sample-dly = <2>;
spi-swap-data = <1>;
spi-max-frequency = <55000000>;

70
arch/riscv/boot/dts/zhihe/a210-evb.dts
View File

@@ -122,7 +122,34 @@
status = "okay";
};
codec_dummy_i2s_8ch: codec_dummy_i2s_8ch {
codec_dummy_i2s_8ch0: codec_dummy_i2s_8ch0 {
compatible = "zhihe,dummy-pcm-i2s-8ch";
sound-name-prefix = "DUMMY";
#address-cells = <0>;
#size-cells = <0>;
#sound-dai-cells = <1>;
status = "okay";
};
codec_dummy_i2s_8ch1: codec_dummy_i2s_8ch1 {
compatible = "zhihe,dummy-pcm-i2s-8ch";
sound-name-prefix = "DUMMY";
#address-cells = <0>;
#size-cells = <0>;
#sound-dai-cells = <1>;
status = "okay";
};
codec_dummy_i2s_8ch2: codec_dummy_i2s_8ch2 {
compatible = "zhihe,dummy-pcm-i2s-8ch";
sound-name-prefix = "DUMMY";
#address-cells = <0>;
#size-cells = <0>;
#sound-dai-cells = <1>;
status = "okay";
};
codec_dummy_i2s_8ch3: codec_dummy_i2s_8ch3 {
compatible = "zhihe,dummy-pcm-i2s-8ch";
sound-name-prefix = "DUMMY";
#address-cells = <0>;
@@ -250,7 +277,7 @@
Sound_Card@2 {
compatible = "simple-audio-card";
simple-audio-card,name = "Sound-Card-I2S3";
simple-audio-card,name = "Sound-Card-HDMI";
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
@@ -259,6 +286,19 @@
};
Sound_Card@3 {
compatible = "simple-audio-card";
simple-audio-card,name = "Sound-Card-I2S3";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
SOUND_CARD_LINK(0, left_j, i2s_8ch_sd0, 0, dummy_i2s_8ch0, 0); /* I2S3-SD0 <-> HW-Codec */
SOUND_CARD_LINK(1, left_j, i2s_8ch_sd1, 0, dummy_i2s_8ch1, 0); /* I2S3-SD1 <-> HW-Codec */
SOUND_CARD_LINK(2, left_j, i2s_8ch_sd2, 0, dummy_i2s_8ch2, 0); /* I2S3-SD2 <-> HW-Codec */
SOUND_CARD_LINK(3, left_j, i2s_8ch_sd3, 0, dummy_i2s_8ch3, 0); /* I2S3-SD3 <-> HW-Codec */
};
Sound_Card@4 {
compatible = "simple-audio-card";
simple-audio-card,name = "Sound-Card-TDM";
#address-cells = <1>;
@@ -275,7 +315,7 @@
SOUND_CARD_LINK(7, dsp_b, tdm_slot7, 0, es7210_adc3, 0); /* TDM_SLOT7 <-> es7210_adc3 */
};
Sound_Card@4 {
Sound_Card@5 {
compatible = "simple-audio-card";
simple-audio-card,name = "Sound-Card-PDM";
#address-cells = <1>;
@@ -1047,7 +1087,7 @@
};
&spi0 {
cs-gpios = <&gpio0_porta 30 0>;
cs-gpios = <&gpio0 30 0>;
rx-sample-delay-ns = <4>;
spi-max-frequency = <55000000>;
@@ -1062,7 +1102,7 @@
};
&spi1 {
cs-gpios = <&gpio2_porta 18 0>;
cs-gpios = <&gpio2 18 0>;
rx-sample-delay-ns = <4>;
spi-max-frequency = <55000000>;
pinctrl-names = "default";
@@ -1079,7 +1119,7 @@
};
&qspi0 {
cs-gpios = <&gpio0_porta 19 0>;
cs-gpios = <&gpio0 19 0>;
rx-sample-dly = <2>;
spi-swap-data = <1>;
spi-max-frequency = <55000000>;
@@ -1099,7 +1139,7 @@
};
&qspi1 {
cs-gpios = <&gpio2_porta 29 0>;
cs-gpios = <&gpio2 29 0>;
rx-sample-dly = <2>;
spi-swap-data = <1>;
spi-max-frequency = <55000000>;
@@ -1255,7 +1295,7 @@
usbc: fusb302@0 {
compatible = "fcs,fusb302";
reg = <0x0>;
interrupt-parent = <&ao_gpio1_porta>;
interrupt-parent = <&ao_gpio1>;
interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default";
status = "disabled";
@@ -1375,16 +1415,16 @@
&emmc {
max-frequency = <196608000>;
non-removable;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
cap-mmc-highspeed;
mmc-hs200-1_8v;
io_fixed_1v8;
is_emmc;
no-sdio;
no-sd;
pull_up;
bus-width = <8>;
cap-mmc-highspeed;
clk-delay-mmc-hs200 = <60>;
};
&sdhci0 {
@@ -1483,10 +1523,10 @@
GPMUX_SEL_04 -> 1
GPMUX_SEL_11 -> 1
*/
// &audio_i2s_8ch_sd0 {
// pinctrl-names = "default";
// pinctrl-0 = <&i2s3_pins>;
// };
&audio_i2s_8ch_sd0 {
pinctrl-names = "default";
pinctrl-0 = <&i2s3_pins>;
};
/*
expansion IO: audio_tdm

8
arch/riscv/boot/dts/zhihe/a210-haps.dts
View File

@@ -319,7 +319,7 @@
};
&spi0 {
cs-gpios = <&gpio1_porta 7 0>;
cs-gpios = <&gpio1 7 0>;
rx-sample-delay-ns = <10>;
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
@@ -345,7 +345,7 @@
};
&spi1 {
// cs-gpios = <&gpio2_porta 15 0>;
// cs-gpios = <&gpio2 15 0>;
rx-sample-delay-ns = <10>;
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins>;
@@ -362,7 +362,7 @@
};
&qspi0 {
cs-gpios = <&gpio0_porta 19 0>;
cs-gpios = <&gpio0 19 0>;
rx-sample-dly = <4>;
pinctrl-names = "default";
pinctrl-0 = <&qspi0_pins>;
@@ -396,7 +396,7 @@
};
&qspi1 {
cs-gpios = <&gpio2_porta 29 0>;
cs-gpios = <&gpio2 29 0>;
rx-sample-dly = <4>;
pinctrl-names = "default";
pinctrl-0 = <&qspi1_pins>;

16
arch/riscv/boot/dts/zhihe/a210-platform-evb.dtsi
View File

@@ -71,6 +71,10 @@
status = "disabled";
};
&spi1 {
status = "disabled";
};
&qspi0 {
status = "disabled";
};
@@ -111,18 +115,6 @@
status = "disabled";
};
&audio_i2s_8ch_sd1 {
status = "disabled";
};
&audio_i2s_8ch_sd2 {
status = "disabled";
};
&audio_i2s_8ch_sd3 {
status = "disabled";
};
&peri3_padctrl {
status = "disabled";
};

82
arch/riscv/boot/dts/zhihe/a210-soc-core.dtsi
View File

@@ -31,6 +31,8 @@
cpu-cacheline = "64Bytes";
cpu-vector = "1.0";
capacity-dmips-mhz = <768>;
clocks = <&clk C908_CPU_TO_CDE_CLK_MUX>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
numa-node-id = <0>;
status = "okay";
@@ -55,6 +57,7 @@
cpu-cacheline = "64Bytes";
cpu-vector = "1.0";
capacity-dmips-mhz = <768>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
numa-node-id = <0>;
status = "okay";
@@ -79,6 +82,7 @@
cpu-cacheline = "64Bytes";
cpu-vector = "1.0";
capacity-dmips-mhz = <768>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
numa-node-id = <0>;
status = "okay";
@@ -103,6 +107,7 @@
cpu-cacheline = "64Bytes";
cpu-vector = "1.0";
capacity-dmips-mhz = <768>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
numa-node-id = <0>;
status = "okay";
@@ -128,6 +133,8 @@
cpu-cacheline = "64Bytes";
cpu-vector = "1.0";
capacity-dmips-mhz = <1024>;
clocks = <&clk C920_CPU_TO_CDE_CLK_MUX>;
operating-points-v2 = <&cluster1_opp>;
#cooling-cells = <2>;
numa-node-id = <0>;
status = "okay";
@@ -152,6 +159,7 @@
cpu-cacheline = "64Bytes";
cpu-vector = "1.0";
capacity-dmips-mhz = <1024>;
operating-points-v2 = <&cluster1_opp>;
#cooling-cells = <2>;
numa-node-id = <0>;
status = "okay";
@@ -176,6 +184,7 @@
cpu-cacheline = "64Bytes";
cpu-vector = "1.0";
capacity-dmips-mhz = <1024>;
operating-points-v2 = <&cluster1_opp>;
#cooling-cells = <2>;
numa-node-id = <0>;
status = "okay";
@@ -200,6 +209,7 @@
cpu-cacheline = "64Bytes";
cpu-vector = "1.0";
capacity-dmips-mhz = <1024>;
operating-points-v2 = <&cluster1_opp>;
#cooling-cells = <2>;
numa-node-id = <0>;
status = "okay";
@@ -286,6 +296,78 @@
};
};
cluster0_opp: opp-table-cluster0 {
compatible = "operating-points-v2";
opp-shared;
opp0-500000000 {
opp-hz = /bits/ 64 <500000000>;
bus-clk-hz = /bits/ 64 <196608000>;
pic-clk-hz = /bits/ 64 <250000000>;
cfg-clk-hz = /bits/ 64 <110000000>;
com-clk-hz = /bits/ 64 <82500000>;
apb-clk-hz = /bits/ 64 <82500000>;
opp-microvolt = <700000 800000>;
};
opp0-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
bus-clk-hz = /bits/ 64 <660000000>;
pic-clk-hz = /bits/ 64 <500000000>;
cfg-clk-hz = /bits/ 64 <220000000>;
com-clk-hz = /bits/ 64 <165000000>;
apb-clk-hz = /bits/ 64 <165000000>;
opp-microvolt = <700000 800000>;
};
opp0-1500000000 {
opp-hz = /bits/ 64 <1500000000>;
bus-clk-hz = /bits/ 64 <1000000000>;
pic-clk-hz = /bits/ 64 <1000000000>;
cfg-clk-hz = /bits/ 64 <330000000>;
com-clk-hz = /bits/ 64 <165000000>;
apb-clk-hz = /bits/ 64 <165000000>;
opp-microvolt = <800000 800000>;
};
opp0-1698000000 {
opp-hz = /bits/ 64 <1698000000>;
bus-clk-hz = /bits/ 64 <1100000000>;
pic-clk-hz = /bits/ 64 <1000000000>;
cfg-clk-hz = /bits/ 64 <330000000>;
com-clk-hz = /bits/ 64 <165000000>;
apb-clk-hz = /bits/ 64 <165000000>;
opp-microvolt = <900000 900000>;
};
opp0-1896000000 {
opp-hz = /bits/ 64 <1896000000>;
bus-clk-hz = /bits/ 64 <1320000000>;
pic-clk-hz = /bits/ 64 <1000000000>;
cfg-clk-hz = /bits/ 64 <330000000>;
com-clk-hz = /bits/ 64 <165000000>;
apb-clk-hz = /bits/ 64 <165000000>;
opp-microvolt = <1000000 1000000>;
};
};
cluster1_opp: opp-table-cluster1 {
compatible = "operating-points-v2";
opp-shared;
opp1-1500000000 {
opp-hz = /bits/ 64 <1500000000>;
opp-microvolt = <800000>;
};
opp1-1698000000 {
opp-hz = /bits/ 64 <1698000000>;
opp-microvolt = <900000>;
};
opp1-1896000000 {
opp-hz = /bits/ 64 <1896000000>;
opp-microvolt = <1000000>;
};
opp1-2298000000 {
opp-hz = /bits/ 64 <2298000000>;
opp-microvolt = <1000000>;
turbo-mode;
};
};
pmu {
compatible = "riscv,pmu";
riscv,event-to-mhpmevent =

16
arch/riscv/boot/dts/zhihe/a210-soc-peri-die1.dtsi
View File

@@ -37,7 +37,7 @@
status = "okay";
};
gpio0_die1: gpio@2002012000 {
gpio@2002012000 {
compatible = "snps,dw-apb-gpio";
reg = <0x20 0x02012000 0x0 0x1000>;
#address-cells = <1>;
@@ -47,7 +47,7 @@
clock-names = "bus", "db";
status = "okay";
gpio0_porta_die1: gpio0-controller@0 {
gpio0_die1: gpio0-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
@@ -62,7 +62,7 @@
};
};
gpio1_die1: gpio@2002013000 {
gpio@2002013000 {
compatible = "snps,dw-apb-gpio";
reg = <0x20 0x02013000 0x0 0x1000>;
#address-cells = <1>;
@@ -72,7 +72,7 @@
clock-names = "bus", "db";
status = "okay";
gpio1_porta_die1: gpio1-controller@0 {
gpio1_die1: gpio1-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
@@ -87,7 +87,7 @@
};
};
gpio2_die1: gpio@2008410000 {
gpio@2008410000 {
compatible = "snps,dw-apb-gpio";
reg = <0x20 0x08410000 0x0 0x1000>;
#address-cells = <1>;
@@ -97,7 +97,7 @@
clock-names = "bus", "db";
status = "okay";
gpio2_porta_die1: gpio2-controller@0 {
gpio2_die1: gpio2-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
@@ -112,7 +112,7 @@
};
};
gpio3_die1: gpio@2008412000 {
gpio@2008412000 {
compatible = "snps,dw-apb-gpio";
reg = <0x20 0x08412000 0x0 0x1000>;
#address-cells = <1>;
@@ -122,7 +122,7 @@
clock-names = "bus", "db";
status = "okay";
gpio3_porta_die1: gpio3-controller@0 {
gpio3_die1: gpio3-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;

32
arch/riscv/boot/dts/zhihe/a210-soc-peri.dtsi
View File

@@ -654,7 +654,7 @@
status = "okay";
};
ao_gpio0: gpio@30841000 {
gpio@30841000 {
compatible = "snps,dw-apb-gpio";
reg = <0x00 0x30841000 0x0 0x1000>;
#address-cells = <1>;
@@ -663,7 +663,7 @@
clock-names = "bus", "db";
status = "okay";
ao_gpio0_porta: ao_gpio0-controller@0 {
ao_gpio0: ao_gpio0-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
@@ -678,7 +678,7 @@
};
};
ao_gpio1: gpio@30897000 {
gpio@30897000 {
compatible = "snps,dw-apb-gpio";
reg = <0x00 0x30897000 0x0 0x1000>;
#address-cells = <1>;
@@ -687,7 +687,7 @@
clock-names = "bus", "db";
status = "okay";
ao_gpio1_porta: ao_gpio1-controller@0 {
ao_gpio1: ao_gpio1-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
@@ -726,7 +726,7 @@
status = "okay";
};
gpio0: gpio@02012000 {
gpio@02012000 {
compatible = "snps,dw-apb-gpio";
reg = <0x00 0x02012000 0x0 0x1000>;
#address-cells = <1>;
@@ -737,7 +737,7 @@
power-domains = <&power_peri1>;
status = "okay";
gpio0_porta: gpio0-controller@0 {
gpio0: gpio0-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
@@ -752,7 +752,7 @@
};
};
gpio1: gpio@02013000 {
gpio@02013000 {
compatible = "snps,dw-apb-gpio";
reg = <0x00 0x02013000 0x0 0x1000>;
#address-cells = <1>;
@@ -763,7 +763,7 @@
power-domains = <&power_peri1>;
status = "okay";
gpio1_porta: gpio1-controller@0 {
gpio1: gpio1-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
@@ -778,7 +778,7 @@
};
};
gpio2: gpio@08410000 {
gpio@08410000 {
compatible = "snps,dw-apb-gpio";
reg = <0x00 0x08410000 0x0 0x1000>;
#address-cells = <1>;
@@ -789,7 +789,7 @@
power-domains = <&power_peri2>;
status = "okay";
gpio2_porta: gpio2-controller@0 {
gpio2: gpio2-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
@@ -804,7 +804,7 @@
};
};
gpio3: gpio@08412000 {
gpio@08412000 {
compatible = "snps,dw-apb-gpio";
reg = <0x00 0x08412000 0x0 0x1000>;
#address-cells = <1>;
@@ -815,7 +815,7 @@
power-domains = <&power_peri2>;
status = "okay";
gpio3_porta: gpio3-controller@0 {
gpio3: gpio3-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
@@ -830,7 +830,7 @@
};
};
gpio4: gpio@00550000 {
gpio@00550000 {
compatible = "snps,dw-apb-gpio";
reg = <0x00 0x00550000 0x0 0x10000>;
#address-cells = <1>;
@@ -841,7 +841,7 @@
power-domains = <&power_peri3>;
status = "okay";
gpio4_porta: gpio4-controller@0 {
gpio4: gpio4-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
@@ -1180,6 +1180,7 @@
clocks = <&clk_peri PERI2_I2S3_SRC_CLK_EN>, <&clk_peri PERI2_I2S3_PCLK_EN>;
clock-names = "sclk", "pclk";
power-domains = <&power_peri2>;
multi-channels = <8>;
#sound-dai-cells = <1>;
dmas = <&dmac0 28>, <&dmac0 27>;
dma-names = "tx", "rx";
@@ -1206,6 +1207,7 @@
clocks = <&clk_peri PERI2_I2S3_SRC_CLK_EN>, <&clk_peri PERI2_I2S3_PCLK_EN>;
clock-names = "sclk", "pclk";
power-domains = <&power_peri2>;
multi-channels = <8>;
#sound-dai-cells = <1>;
dmas = <&dmac0 30>, <&dmac0 29>;
dma-names = "tx", "rx";
@@ -1221,6 +1223,7 @@
clocks = <&clk_peri PERI2_I2S3_SRC_CLK_EN>, <&clk_peri PERI2_I2S3_PCLK_EN>;
clock-names = "sclk", "pclk";
power-domains = <&power_peri2>;
multi-channels = <8>;
#sound-dai-cells = <1>;
dmas = <&dmac0 32>, <&dmac0 31>;
dma-names = "tx", "rx";
@@ -1236,6 +1239,7 @@
clocks = <&clk_peri PERI2_I2S3_SRC_CLK_EN>, <&clk_peri PERI2_I2S3_PCLK_EN>;
clock-names = "sclk", "pclk";
power-domains = <&power_peri2>;
multi-channels = <8>;
#sound-dai-cells = <1>;
dmas = <&dmac0 34>, <&dmac0 33>;
dma-names = "tx", "rx";

2
arch/riscv/boot/dts/zhihe/a210-som-v1.dts
View File

@@ -505,7 +505,7 @@
};
&qspi0 {
cs-gpios = <&gpio0_porta 19 0>;
cs-gpios = <&gpio0 19 0>;
rx-sample-dly = <2>;
spi-swap-data = <1>;
spi-max-frequency = <55000000>;

4
arch/riscv/configs/a210_evb_defconfig
View File

@@ -50,6 +50,10 @@ CONFIG_XUANTIE_ISA=y
CONFIG_PM=y
CONFIG_PM_DEBUG=y
CONFIG_PM_ADVANCED_DEBUG=y
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
CONFIG_RISCV_ZHIHE_CPUFREQ=y
CONFIG_KPROBES=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y

8
drivers/cpufreq/Kconfig
View File

@@ -321,5 +321,13 @@ config RISCV_XUANTIE_TH1520_CPUFREQ
This adds the CPUFreq driver support for XuanTie th1520 SoCs
which are capable of changing the CPU's frequency dynamically.
config RISCV_ZHIHE_CPUFREQ
bool "CPU frequency scaling driver for zhihe riscv SoCs"
depends on OF && COMMON_CLK && ZHIHE_AON
select PM_OPP
help
This adds the CPUFreq driver support for Zhihe riscv A210 SoCs
which are capable of changing the CPU's frequency dynamically.
endif
endmenu

1
drivers/cpufreq/Makefile
View File

@@ -108,3 +108,4 @@ obj-$(CONFIG_SH_CPU_FREQ) += sh-cpufreq.o
obj-$(CONFIG_SPARC_US2E_CPUFREQ) += sparc-us2e-cpufreq.o
obj-$(CONFIG_SPARC_US3_CPUFREQ) += sparc-us3-cpufreq.o
obj-$(CONFIG_RISCV_XUANTIE_TH1520_CPUFREQ) += th1520-cpufreq.o
obj-$(CONFIG_RISCV_ZHIHE_CPUFREQ) += zhihe-cpufreq.o

510
drivers/cpufreq/zhihe-cpufreq.c Normal file
View File

@@ -0,0 +1,510 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2025 Zhihe Computing Limited.
*
* Dong Yan <yand@zhcomputing.com>
*/
#define pr_fmt(fmt)KBUILD_MODNAME ": " fmt
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/cpu.h>
#include <linux/cpufreq.h>
#include <linux/cpumask.h>
#include <linux/err.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/pm_opp.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
#include <linux/thermal.h>
#include <linux/mutex.h>
#define ZH_DVFS_MAX_REGULATORS 2
/* SOC specific data */
struct zh_cpufreq_bus_opp {
unsigned long long bus_clk_freq;
unsigned long long pic_clk_freq;
unsigned long long cfg_clk_freq;
unsigned long long com_clk_freq;
unsigned long long apb_clk_freq;
};
struct zh_cpufreq_soc_data {
struct device *dev;
struct clk *bus_clk;
struct clk *pic_clk;
struct clk *cfg_clk;
struct clk *com_clk;
struct clk *apb_clk;
struct zh_cpufreq_bus_opp *bus_opp;
unsigned int num_bus_opp;
};
/* cluster specific data */
struct zh_cpufreq_cluster_data {
cpumask_var_t cpus;
struct device *cpu_dev;
struct regulator *dvdd_cpu;
struct regulator *dvddm_cpu;
struct regulator *dvdd_cpu_p;
struct list_head node;
int opp_token;
struct cpufreq_frequency_table *freq_table;
struct clk *pll_mux;
struct zh_cpufreq_soc_data *soc;
unsigned int num_opps;
};
static LIST_HEAD(info_list);
static struct freq_attr *zh_cpufreq_attr[] = {
&cpufreq_freq_attr_scaling_available_freqs,
NULL, /* Extra space for boost-attr if required */
NULL,
};
static struct zh_cpufreq_cluster_data *zh_cpufreq_cluster_data_lookup(int cpu)
{
struct zh_cpufreq_cluster_data *cluster;
list_for_each_entry(cluster, &info_list, node) {
if (cpumask_test_cpu(cpu, cluster->cpus))
return cluster;
}
return NULL;
}
static int zh_cpufreq_online(struct cpufreq_policy *policy)
{
/* TODO: hotplug specific actions */
return 0;
}
static int zh_cpufreq_offline(struct cpufreq_policy *policy)
{
/* TODO: hotplug specific actions */
return 0;
}
static int zh_cpufreq_init(struct cpufreq_policy *policy)
{
struct zh_cpufreq_cluster_data *cluster;
struct device *cpu_dev;
unsigned int transition_latency;
int ret;
cluster = zh_cpufreq_cluster_data_lookup(policy->cpu);
if (!cluster) {
pr_err("failed to find data for cpu%d\n", policy->cpu);
return -ENODEV;
}
cpu_dev = cluster->cpu_dev;
transition_latency = dev_pm_opp_get_max_transition_latency(cpu_dev);
if (!transition_latency)
transition_latency = CPUFREQ_ETERNAL;
cpumask_copy(policy->cpus, cluster->cpus);
policy->driver_data = cluster;
policy->clk = cluster->pll_mux;
policy->freq_table = cluster->freq_table;
policy->suspend_freq = dev_pm_opp_get_suspend_opp_freq(cpu_dev) / 1000;
policy->cpuinfo.transition_latency = transition_latency;
policy->dvfs_possible_from_any_cpu = true;
/* Support turbo/boost mode */
if (policy_has_boost_freq(policy)) {
/* This gets disabled by core on driver unregister */
ret = cpufreq_enable_boost_support();
if (ret)
return ret;
zh_cpufreq_attr[1] = &cpufreq_freq_attr_scaling_boost_freqs;
}
return 0;
}
static int zh_cpufreq_exit(struct cpufreq_policy *policy)
{
clk_put(policy->clk);
return 0;
}
static int zh_set_target(struct cpufreq_policy *policy, unsigned int index)
{
struct zh_cpufreq_cluster_data *cluster = policy->driver_data;
struct zh_cpufreq_soc_data *soc = cluster->soc;
unsigned long target_freq = policy->freq_table[index].frequency;
unsigned int current_freq = policy->cur;
if (target_freq < current_freq && policy->cpu == 0) {
clk_set_rate(soc->bus_clk, soc->bus_opp[index].bus_clk_freq);
clk_set_rate(soc->pic_clk, soc->bus_opp[index].pic_clk_freq);
clk_set_rate(soc->cfg_clk, soc->bus_opp[index].cfg_clk_freq);
clk_set_rate(soc->com_clk, soc->bus_opp[index].com_clk_freq);
clk_set_rate(soc->apb_clk, soc->bus_opp[index].apb_clk_freq);
}
clk_set_rate(cluster->pll_mux, 1000000000);
dev_pm_opp_set_rate(cluster->cpu_dev, target_freq * 1000);
if (target_freq > current_freq && policy->cpu == 0) {
clk_set_rate(soc->bus_clk, soc->bus_opp[index].bus_clk_freq);
clk_set_rate(soc->pic_clk, soc->bus_opp[index].pic_clk_freq);
clk_set_rate(soc->cfg_clk, soc->bus_opp[index].cfg_clk_freq);
clk_set_rate(soc->com_clk, soc->bus_opp[index].com_clk_freq);
clk_set_rate(soc->apb_clk, soc->bus_opp[index].apb_clk_freq);
}
return 0;
}
static struct cpufreq_driver zh_cpufreq_driver = {
.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK | CPUFREQ_HAVE_GOVERNOR_PER_POLICY |
CPUFREQ_IS_COOLING_DEV,
.verify = cpufreq_generic_frequency_table_verify,
.target_index = zh_set_target,
.get = cpufreq_generic_get,
.init = zh_cpufreq_init,
.exit = zh_cpufreq_exit,
.online = zh_cpufreq_online,
.offline = zh_cpufreq_offline,
.register_em = cpufreq_register_em_with_opp,
.name = "zh-cpufreq",
.attr = zh_cpufreq_attr,
.suspend = cpufreq_generic_suspend,
};
static int find_supply_name(struct device *dev, struct device_node *cpu_np, const char ***reg_names_out)
{
struct property *prop;
const char *prop_name;
size_t len;
int count = 0;
const char **names_array;
if (!cpu_np)
return -EINVAL;
names_array = devm_kzalloc(dev, (ZH_DVFS_MAX_REGULATORS + 1) * sizeof(char *), GFP_KERNEL);
if (!names_array)
return -ENOMEM;
for_each_property_of_node(cpu_np, prop) {
prop_name = prop->name;
len = strlen(prop_name);
if (len > 7 && strcmp(prop_name + len - 7, "-supply") == 0) {
if (count >= ZH_DVFS_MAX_REGULATORS) {
pr_err("Too many regulators defined!\n");
return -ENOMEM;
}
char *reg_name_buf = devm_kzalloc(dev, len - 7 + 1, GFP_KERNEL);
if (!reg_name_buf)
return -ENOMEM;
strncpy(reg_name_buf, prop_name, len - 7);
reg_name_buf[len - 7] = '\0';
names_array[count] = reg_name_buf;
count++;
}
}
*reg_names_out = names_array;
return count;
}
static int zh_opp_config_regulators(struct device *dev,
struct dev_pm_opp *old_opp, struct dev_pm_opp *new_opp,
struct regulator **regulators, unsigned int count)
{
int ret;
struct dev_pm_opp_supply new_supplies[2];
/* We must have two regulators here */
WARN_ON(count != 2);
/* Fetch supplies and freq information from OPP core */
ret = dev_pm_opp_get_supplies(new_opp, new_supplies);
WARN_ON(ret);
for (int i = 0; i < count; i++) {
if (IS_ERR(regulators[i])) {
dev_dbg(dev, "%s: regulator not available: %ld\n", __func__,
PTR_ERR(regulators[i]));
return 0;
}
ret = regulator_set_voltage_triplet(regulators[i], new_supplies[i].u_volt_min,
new_supplies[i].u_volt, new_supplies[i].u_volt_max);
if (ret)
dev_err(dev, "%s: failed to set voltage (%lu %lu %lu mV): %d\n",
__func__, new_supplies[i].u_volt_min, new_supplies[i].u_volt,
new_supplies[i].u_volt_max, ret);
}
return 0;
}
static int find_bus_info(struct zh_cpufreq_soc_data *soc)
{
struct device_node *cpu_np = NULL;
struct device_node *opp_table_np = NULL;
struct device_node *opp_np = NULL;
struct device *cpu_dev = get_cpu_device(0);
struct device *dev = soc->dev;
int i = 0;
soc->bus_clk = clk_get(dev, "bus_clk");
if (IS_ERR(soc->bus_clk)) {
dev_err(dev, "failed to get bus_clk\n");
return PTR_ERR(soc->bus_clk);
}
soc->pic_clk = clk_get(dev, "pic_clk");
if (IS_ERR(soc->pic_clk)) {
dev_err(dev, "failed to get pic_clk\n");
return PTR_ERR(soc->pic_clk);
}
soc->cfg_clk = clk_get(dev, "cfg_clk");
if (IS_ERR(soc->cfg_clk)) {
dev_err(dev, "failed to get cfg_clk\n");
return PTR_ERR(soc->cfg_clk);
}
soc->com_clk = clk_get(dev, "com_clk");
if (IS_ERR(soc->com_clk)) {
dev_err(dev, "failed to get com_clk\n");
return PTR_ERR(soc->com_clk);
}
soc->apb_clk = clk_get(dev, "apb_clk");
if (IS_ERR(soc->apb_clk)) {
dev_err(dev, "failed to get apb_clk\n");
return PTR_ERR(soc->apb_clk);
}
cpu_np = of_get_cpu_node(0, NULL);
if (!cpu_np) {
dev_err(dev, "Failed to get CPU device node\n");
return -ENODEV;
}
opp_table_np = of_parse_phandle(cpu_np, "operating-points-v2", 0);
if (!opp_table_np) {
dev_err(dev, "Failed to get CPU opp_table\n");
return -ENODEV;
}
soc->num_bus_opp = dev_pm_opp_get_opp_count(cpu_dev);
if (!soc->num_bus_opp) {
dev_err(dev, "No OPPs found\n");
return -ENODEV;
}
soc->bus_opp = devm_kzalloc(dev, sizeof(struct zh_cpufreq_bus_opp) * soc->num_bus_opp, GFP_KERNEL);
if (!soc->bus_opp)
return -ENOMEM;
for_each_child_of_node(opp_table_np, opp_np) {
if (of_property_read_u64(opp_np, "bus-clk-hz", &soc->bus_opp[i].bus_clk_freq))
dev_warn(dev, "Missing 'bus-clk-hz' for OPP%d\n", i);
if (of_property_read_u64(opp_np, "pic-clk-hz", &soc->bus_opp[i].pic_clk_freq))
dev_warn(dev, "Missing 'pic-clk-hz' for OPP%d\n", i);
if (of_property_read_u64(opp_np, "cfg-clk-hz", &soc->bus_opp[i].cfg_clk_freq))
dev_warn(dev, "Missing 'cfg-clk-hz' for OPP%d\n", i);
if (of_property_read_u64(opp_np, "com-clk-hz", &soc->bus_opp[i].com_clk_freq))
dev_warn(dev, "Missing 'com-clk-hz' for OPP%d\n", i);
if (of_property_read_u64(opp_np, "apb-clk-hz", &soc->bus_opp[i].apb_clk_freq))
dev_warn(dev, "Missing 'apb-clk-hz' for OPP%d\n", i);
i++;
}
return 0;
}
static int zh_cpufreq_prepare_cluster(struct device *dev, int cpu)
{
struct zh_cpufreq_cluster_data *cluster;
struct device *cpu_dev;
const char **reg_names = NULL;
int num_regulators;
int ret;
cluster = zh_cpufreq_cluster_data_lookup(cpu);
if (cluster)
return 0; // dvfs cluster of this cpu already existed in case of hotplug.
cpu_dev = get_cpu_device(cpu);
if (!cpu_dev)
return -EPROBE_DEFER;
cluster = devm_kzalloc(dev, sizeof(*cluster), GFP_KERNEL);
if (!cluster) {
return -ENOMEM;
}
cluster->soc = dev_get_drvdata(dev);
cluster->cpu_dev = cpu_dev;
cluster->pll_mux = clk_get(cpu_dev, NULL);
if (IS_ERR(cluster->pll_mux)) {
ret = PTR_ERR(cluster->pll_mux);
dev_err(cpu_dev, "%s: failed to get clk: %d\n", __func__, ret);
return ret;
}
if (!alloc_cpumask_var(&cluster->cpus, GFP_KERNEL))
return -ENOMEM;
/*
* OPP layer will be taking care of regulators now, but it needs to know
* the name of the regulator first.
*/
num_regulators = find_supply_name(dev, of_get_cpu_node(cpu, NULL), &reg_names);
if (num_regulators <= 0) {
of_node_put(of_get_cpu_node(cpu, NULL));
ret = dev_err_probe(dev, num_regulators,
"failed to find regulators for cpu%d\n", cpu);
goto free_cpumask;
}
cluster->opp_token = dev_pm_opp_set_regulators(cpu_dev, reg_names);
if (cluster->opp_token < 0) {
ret = dev_err_probe(dev, cluster->opp_token,
"failed to set regulators\n");
goto free_cpumask;
}
ret = dev_pm_opp_set_config_regulators(cpu_dev, zh_opp_config_regulators);
if (ret < 0) {
dev_err(dev, "failed to set config_regulators callback ret=%d\n", ret);
goto free_cpumask;
}
/* Get OPP-sharing information from "operating-points-v2" bindings .
* After this point, cpumask will include all cpus within the same cluster.
*/
ret = dev_pm_opp_of_get_sharing_cpus(cpu_dev, cluster->cpus);
if (ret) {
goto out_regulator;
}
/*
* Initialize OPP tables for all priv->cpus from device tree. They will be shared by
* all CPUs which have marked their CPUs shared with OPP bindings.
*/
ret = dev_pm_opp_of_cpumask_add_table(cluster->cpus);
if (ret) {
goto out_table;
}
/*
* The OPP table must be initialized by this point.
*/
cluster->num_opps = dev_pm_opp_get_opp_count(cpu_dev);
if (cluster->num_opps <= 0) {
dev_err(cpu_dev, "OPP table can't be empty\n");
ret = -ENODEV;
goto out_table;
}
ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &cluster->freq_table);
if (ret) {
dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
goto out_table;
}
list_add(&cluster->node, &info_list);
return 0;
out_table:
dev_pm_opp_of_cpumask_remove_table(cluster->cpus);
out_regulator:
dev_pm_opp_put_regulators(cluster->opp_token);
free_cpumask:
free_cpumask_var(cluster->cpus);
return ret;
}
static void zh_cpufreq_release(void)
{
struct zh_cpufreq_cluster_data *cluster, *tmp;
list_for_each_entry_safe(cluster, tmp, &info_list, node) {
dev_pm_opp_free_cpufreq_table(cluster->cpu_dev, &cluster->freq_table);
dev_pm_opp_of_cpumask_remove_table(cluster->cpus);
dev_pm_opp_put_regulators(cluster->opp_token);
free_cpumask_var(cluster->cpus);
list_del(&cluster->node);
}
}
static int zh_cpufreq_probe(struct platform_device *pdev)
{
struct zh_cpufreq_soc_data *soc;
struct device *dev = &pdev->dev;
int cpu, ret;
soc = devm_kzalloc(dev, sizeof(*soc), GFP_KERNEL);
if (!soc)
return -ENOMEM;
soc->dev = dev;
dev_set_drvdata(dev, soc);
for_each_possible_cpu(cpu) {
ret = zh_cpufreq_prepare_cluster(dev, cpu);
if (ret)
goto err;
}
ret = find_bus_info(soc);
if (ret < 0) {
dev_err(dev, "failed to find bus clk opp %d\n", ret);
goto err;
}
ret = cpufreq_register_driver(&zh_cpufreq_driver);
if (ret) {
dev_err(dev, "failed register driver: %d\n", ret);
goto err;
}
return 0;
err:
zh_cpufreq_release();
return ret;
}
static const struct of_device_id zh_cpufreq_of_match[] = {
{ .compatible = "zhihe,a210-cpufreq"},
{}
};
MODULE_DEVICE_TABLE(of, zh_cpufreq_of_match);
static struct platform_driver zh_cpufreq_platdrv = {
.driver = {
.name = "zh-cpufreq",
.of_match_table = of_match_ptr(zh_cpufreq_of_match),
},
.probe = zh_cpufreq_probe,
};
module_platform_driver(zh_cpufreq_platdrv);
MODULE_AUTHOR("Dong Yan <yand@zhcomputing.com>");
MODULE_DESCRIPTION("Zhihe cpufreq driver");
MODULE_LICENSE("GPL v2");

3
drivers/gpu/drm/verisilicon/dw_dp.c
View File

@@ -3296,7 +3296,8 @@ static void dw_dp_bridge_detach(struct drm_bridge *bridge)
{
struct dw_dp *dp = bridge_to_dp(bridge);
drm_connector_cleanup(&dp->connector);
if (dp->connector.dev)
drm_connector_cleanup(&dp->connector);
}
static void dw_dp_bridge_atomic_pre_enable(struct drm_bridge *bridge,

9
drivers/mmc/host/sdhci-of-dwcmshc.c
View File

@@ -502,11 +502,13 @@ static void th1520_set_uhs_signaling(struct sdhci_host *host,
priv->delay_line = th_priv->delay_line[MMC_TIMING_MMC_HS400];
th1520_sdhci_set_phy(host); /* update tx delay*/
} else if(timing == MMC_TIMING_UHS_SDR104){
} else if(timing == MMC_TIMING_MMC_HS200) {
priv->delay_line = th_priv->delay_line[MMC_TIMING_MMC_HS200];
} else if(timing == MMC_TIMING_UHS_SDR104) {
priv->delay_line = th_priv->delay_line[MMC_TIMING_UHS_SDR104];
th1520_sdhci_set_phy(host); /* update tx delay*/
sdhci_writeb(host, 0, PHY_DLLDL_CNFG_R);
}else {
} else {
sdhci_writeb(host, 0, PHY_DLLDL_CNFG_R);
if(th_priv->rxclk_sw_tune_en && (timing == MMC_TIMING_SD_HS)) {
(void)th1520_sdhci_set_rxclk_sample_delay(host, th_priv->rxclk_delay_set, 10000);
@@ -1070,6 +1072,9 @@ static int th1520_sdhci_get_priv_props(struct device *dev, bool is_emmc,
if(device_property_get_clk_delay(dev, "clk-delay-mmc-hs400",
&(th_priv->delay_line[MMC_TIMING_MMC_HS400]) ) < 0 )
th_priv->delay_line[MMC_TIMING_MMC_HS400] = PHY_SDCLKDL_DC_HS400;
if(device_property_get_clk_delay(dev, "clk-delay-mmc-hs200",
&(th_priv->delay_line[MMC_TIMING_MMC_HS200]) ) < 0 )
th_priv->delay_line[MMC_TIMING_MMC_HS200] = PHY_SDCLKDL_DC_DEFAULT;
}
else
{

3
drivers/regulator/zhihe-aon-regulator.c
View File

@@ -272,8 +272,11 @@ static int aon_regu_is_enabled(struct regulator_dev *reg)
static int aon_regu_set_voltage(struct regulator_dev *reg,
int minuV, int max_uV, unsigned int *selector)
{
const struct regulator_desc *desc = reg->desc;
u16 regu_id = (u16) rdev_get_id(reg);
*selector = DIV_ROUND_UP(minuV - desc->min_uV, desc->uV_step);
return aon_set_regulator(zhihe_aon_pmic_info.ipc_handle, regu_id, minuV);
}

4
sound/soc/codecs/aw87519.c
View File

@@ -582,9 +582,7 @@ static const struct snd_kcontrol_new aw87519_controls[] = {
static int aw87519_component_probe(struct snd_soc_component* component)
{
struct aw87519 *pa = snd_soc_component_get_drvdata(component);
return 0; // snd_soc_add_component_controls(component, aw87519_controls, ARRAY_SIZE(aw87519_controls));
return 0;
}
static int aw87519_power_event(struct snd_soc_dapm_widget *w,

8
sound/soc/codecs/aw87565.c
View File

@@ -346,8 +346,6 @@ static const struct snd_kcontrol_new aw87565_controls[] = {
static int aw87565_component_probe(struct snd_soc_component* component)
{
struct aw87565 *pa = snd_soc_component_get_drvdata(component);
return 0;
}
@@ -422,10 +420,6 @@ static const struct snd_soc_component_driver aw87565_component_driver = {
******************************************************************************/
static int aw87565_i2c_probe(struct i2c_client *client)
{
struct device_node *np = client->dev.of_node;
struct device_node *node;
struct device_node *aw9535_node = NULL;
int reg_val;
struct aw87565 *aw87565;
int ret = -1;
@@ -436,7 +430,7 @@ static int aw87565_i2c_probe(struct i2c_client *client)
aw87565 = devm_kzalloc(&client->dev, sizeof(struct aw87565), GFP_KERNEL);
if (aw87565 == NULL) {
dev_err(&client->dev, "Failed to alloc priv data: %d\n", ret);
dev_err(&client->dev, "Failed to alloc priv data\n");
return -ENOMEM;
}

2
sound/soc/xuantie/th1520-i2s-8ch.c
View File

@@ -606,8 +606,6 @@ static int th1520_audio_i2s_8ch_probe(struct platform_device *pdev)
int ret;
unsigned int irq;
const char *sprop;
const uint32_t *iprop;
struct resource *res;
struct th1520_i2s_priv *priv;
struct device *dev = &pdev->dev;

3
sound/soc/xuantie/th1520-spdif.c
View File

@@ -328,7 +328,6 @@ static int th1520_spdif_suspend(struct device *dev)
static int th1520_spdif_resume(struct device *dev)
{
struct th1520_spdif_priv *priv = dev_get_drvdata(dev);
int ret;
pm_runtime_get_sync(dev);
@@ -349,7 +348,7 @@ static int th1520_spdif_resume(struct device *dev)
pm_runtime_put_sync(dev);
return ret;
return 0;
}
#endif

2
sound/soc/xuantie/th1520-tdm.c
View File

@@ -108,6 +108,7 @@ static int th1520_tdm_dai_trigger(struct snd_pcm_substream *substream, int cmd,
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
priv->state = TDM_STATE_IDLE;
fallthrough;
case SNDRV_PCM_TRIGGER_SUSPEND:
th1520_tdm_snd_rxctrl(priv, 0);
break;
@@ -437,7 +438,6 @@ irqreturn_t tdm_interrupt(int irq, void* dev_id)
static int th1520_tdm_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
const char *sprop;
const uint32_t *iprop;
struct th1520_tdm_priv *tdm_priv;
struct resource *res;

258
sound/soc/zhihe/zhihe-i2s.c
View File

@@ -24,6 +24,13 @@
#define DRV_NAME "zhihe-i2s"
static int i2s3_probe_flag = 0;
static void __iomem *i2s3_host_regs = NULL;
static atomic_t rx_device_usage = ATOMIC_INIT(0);
/* 0: master-sd0 && 1: slave-sd1 && 2: slave-sd2 && 3: slave-sd3 */
static struct dma_chan *i2s3_tx_ch[4] = { NULL, NULL, NULL, NULL };
static struct dma_chan *i2s3_rx_ch[4] = { NULL, NULL, NULL, NULL };
static unsigned int a200_special_sample_rates[] = { 11025, 22050, 44100, 88200 };
@@ -137,14 +144,86 @@ static int a210_i2s_set_div(struct zhihe_i2s_priv *i2s_priv, unsigned int rate,
return ret;
}
static int zhihe_snd_ctrl(struct zhihe_i2s_priv *i2s_priv, bool tx, bool on)
static bool tx_fifo_empty(void __iomem *addr)
{
unsigned int status = readl(addr + I2S_SR);
return ((status & SR_TFE_TX_FIFO_EMPTY_Msk) == SR_TFE_TX_FIFO_EMPTY) &&
!(status & SR_TXBUSY_STATUS);
}
static bool rx_fifo_full(void __iomem *addr, unsigned int channels)
{
unsigned int rx_fifo_full_msk = 0, rx_fifo_full = 0;
unsigned int status = readl(addr + I2S_SR);
switch (channels) {
case 8:
rx_fifo_full_msk |= SR_RFF3_Msk;
rx_fifo_full |= SR_RFF3_RX_FIFO_FULL;
fallthrough;
case 6:
rx_fifo_full_msk |= SR_RFF2_Msk;
rx_fifo_full |= SR_RFF2_RX_FIFO_FULL;
fallthrough;
case 4:
rx_fifo_full_msk |= SR_RFF1_Msk;
rx_fifo_full |= SR_RFF1_RX_FIFO_FULL;
fallthrough;
case 2:
rx_fifo_full_msk |= SR_RFF0_Msk;
rx_fifo_full |= SR_RFF0_RX_FIFO_FULL;
break;
default:
rx_fifo_full_msk |= SR_RFF0_Msk;
rx_fifo_full |= SR_RFF0_RX_FIFO_FULL;
break;
}
return ((status & rx_fifo_full_msk) == rx_fifo_full) &&
(status & SR_RXBUSY_STATUS);
}
static int i2s_multi_channel_sync(void __iomem *addr, unsigned int channels,
bool master, bool tx, bool on)
{
if (on)
return 0;
if (!addr)
return -EINVAL;
do {
if (tx && tx_fifo_empty(addr))
break;
else if (!tx) {
if (!master)
break;
else if (rx_fifo_full(addr, channels) && atomic_read(&rx_device_usage) == 0) {
udelay(100);
break;
}
}
udelay(10);
} while (1);
return 0;
}
static int zhihe_snd_ctrl(struct zhihe_i2s_priv *i2s_priv, bool tx, bool on,
int (*cb)(struct dma_chan *))
{
unsigned int dma_en;
unsigned long flags;
int ret = 0;
int i;
if (strstr(i2s_priv->drvdata->name, I2S3) && !i2s_priv->regmap)
return 0;
if (strstr(i2s_priv->drvdata->name, I2S3)) {
if (!tx && on)
atomic_inc(&rx_device_usage);
else if (!tx && !on)
atomic_dec(&rx_device_usage);
if (!i2s_priv->regmap)
return i2s_multi_channel_sync(i2s3_host_regs, i2s_priv->ch_cnt, false, tx, on);
}
spin_lock_irqsave(&i2s_priv->zhihe_i2s_lock, flags);
@@ -161,6 +240,7 @@ static int zhihe_snd_ctrl(struct zhihe_i2s_priv *i2s_priv, bool tx, bool on)
regmap_write(i2s_priv->regmap, I2S_IISEN, IISEN_I2SEN);
} else {
dma_en &= tx ? ~DMACR_TDMAE_EN : ~DMACR_RDMAE_EN;
i2s_multi_channel_sync(i2s_priv->regs, i2s_priv->ch_cnt, true, tx, on);
regmap_write(i2s_priv->regmap, I2S_DMACR, dma_en);
/**
@@ -176,12 +256,20 @@ static int zhihe_snd_ctrl(struct zhihe_i2s_priv *i2s_priv, bool tx, bool on)
FUNCMODE_RMODE_Msk,
FUNCMODE_TMODE_WEN |
FUNCMODE_RMODE_WEN);
/* work around to deal with channel sync */
for (i = 1; i < i2s_priv->ch_cnt / 2; i++) {
if (i2s3_tx_ch[i])
cb(i2s3_tx_ch[i]);
if (i2s3_rx_ch[i])
cb(i2s3_rx_ch[i]);
}
}
}
spin_unlock_irqrestore(&i2s_priv->zhihe_i2s_lock, flags);
return ret;
return 0;
}
/**
@@ -195,24 +283,24 @@ static int zhihe_i2s_dai_trigger(struct snd_pcm_substream *substream, int cmd,
{
struct zhihe_i2s_priv *i2s_priv = snd_soc_dai_get_drvdata(dai);
bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
int (*cb)(struct dma_chan *chan);
int ret;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
ret = zhihe_snd_ctrl(i2s_priv, tx, true);
ret = zhihe_snd_ctrl(i2s_priv, tx, true, NULL);
break;
case SNDRV_PCM_TRIGGER_STOP:
/* work around for DMAC stop issue. */
dmaengine_terminate_async(snd_dmaengine_pcm_get_chan(substream));
ret = zhihe_snd_ctrl(i2s_priv, tx, false);
cb = dmaengine_terminate_async;
ret = zhihe_snd_ctrl(i2s_priv, tx, false, cb);
break;
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
/* work around for DMAC stop issue. */
dmaengine_pause(snd_dmaengine_pcm_get_chan(substream));
ret = zhihe_snd_ctrl(i2s_priv, tx, false);
ret = zhihe_snd_ctrl(i2s_priv, tx, false, NULL);
break;
default:
return -EINVAL;
@@ -308,7 +396,6 @@ static int zhihe_i2s_dai_hw_params(struct snd_pcm_substream *substream,
unsigned int ratio = IIS_MCLK_SEL_256;
unsigned int funcmode;
int ret = 0;
bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
if (strstr(i2s_priv->drvdata->name, I2S3) && !i2s_priv->regmap)
return 0;
@@ -321,7 +408,7 @@ static int zhihe_i2s_dai_hw_params(struct snd_pcm_substream *substream,
break;
case SNDRV_PCM_FORMAT_S16_LE:
fssta |= I2S_DATA_WIDTH_16BIT;
fssta |= FSSTA_SCLK_SEL_32;
fssta |= FSSTA_SCLK_SEL_64; // in multi-channel mode, HW-codec require sclk at 64fs
fssta |= FSSTA_MCLK_SEL_256;
break;
case SNDRV_PCM_FORMAT_S24_LE:
@@ -345,20 +432,26 @@ static int zhihe_i2s_dai_hw_params(struct snd_pcm_substream *substream,
regmap_read(i2s_priv->regmap, I2S_FUNCMODE, &funcmode);
/**
* CH_SEL: channel 0 work (default).
* When enable channel 1/2/3 during tx mode, dma will fail to stop.
*/
if (strstr(i2s_priv->drvdata->name, I2S3)) {
if (tx) {
funcmode &= ~FUNCMODE_CH1_ENABLE;
funcmode &= ~FUNCMODE_CH2_ENABLE;
funcmode &= ~FUNCMODE_CH3_ENABLE;
} else {
funcmode |= FUNCMODE_CH1_ENABLE;
funcmode |= FUNCMODE_CH2_ENABLE;
funcmode |= FUNCMODE_CH3_ENABLE;
}
funcmode &= ~FUNCMODE_CH0_ENABLE;
funcmode &= ~FUNCMODE_CH1_ENABLE;
funcmode &= ~FUNCMODE_CH2_ENABLE;
funcmode &= ~FUNCMODE_CH3_ENABLE;
switch (i2s_priv->ch_cnt) {
case 8:
funcmode |= FUNCMODE_CH3_ENABLE;
fallthrough;
case 6:
funcmode |= FUNCMODE_CH2_ENABLE;
fallthrough;
case 4:
funcmode |= FUNCMODE_CH1_ENABLE;
fallthrough;
case 2:
funcmode |= FUNCMODE_CH0_ENABLE;
break;
default:
dev_err(i2s_priv->dev, "Invalid channel count: %u\n", i2s_priv->ch_cnt);
return -EINVAL;
}
regmap_write(i2s_priv->regmap, I2S_FUNCMODE, funcmode);
@@ -395,6 +488,7 @@ static int zhihe_hdmi_dai_hw_params(struct snd_pcm_substream *substream,
unsigned int rate = params_rate(params);
unsigned int fssta = 0, iiscnf_out = 0;
unsigned int ratio = IIS_MCLK_SEL_256;
unsigned int funcmode;
int ret = 0;
if (strstr(i2s_priv->drvdata->name, I2S3) && !i2s_priv->regmap)
@@ -420,6 +514,15 @@ static int zhihe_hdmi_dai_hw_params(struct snd_pcm_substream *substream,
regmap_update_bits(i2s_priv->regmap, I2S_FSSTA, FSSTA_DATAWTH_Msk |
FSSTA_SCLK_SEL_Msk | FSSTA_MCLK_SEL_Msk, fssta);
/* HDMI audio only use channel 0. */
regmap_read(i2s_priv->regmap, I2S_FUNCMODE, &funcmode);
funcmode &= ~FUNCMODE_CH0_ENABLE;
funcmode &= ~FUNCMODE_CH1_ENABLE;
funcmode &= ~FUNCMODE_CH2_ENABLE;
funcmode &= ~FUNCMODE_CH3_ENABLE;
funcmode |= FUNCMODE_CH0_ENABLE;
regmap_write(i2s_priv->regmap, I2S_FUNCMODE, funcmode);
if (channels == MONO_SOURCE)
iiscnf_out |= CNFOUT_TX_VOICE_EN_MONO;
else
@@ -435,6 +538,70 @@ static int zhihe_hdmi_dai_hw_params(struct snd_pcm_substream *substream,
return ret;
}
static int zhihe_i2s_dai_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct zhihe_i2s_priv *i2s_priv = snd_soc_dai_get_drvdata(dai);
struct dma_chan *chan = snd_dmaengine_pcm_get_chan(substream);
bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
if (!strcmp(i2s_priv->drvdata->name, "i2s3-8ch-sd0")) {
if (tx)
i2s3_tx_ch[0] = chan;
else
i2s3_rx_ch[0] = chan;
} else if (!strcmp(i2s_priv->drvdata->name, "i2s3-8ch-sd1")) {
if (tx)
i2s3_tx_ch[1] = chan;
else
i2s3_rx_ch[1] = chan;
} else if (!strcmp(i2s_priv->drvdata->name, "i2s3-8ch-sd2")) {
if (tx)
i2s3_tx_ch[2] = chan;
else
i2s3_rx_ch[2] = chan;
} else if (!strcmp(i2s_priv->drvdata->name, "i2s3-8ch-sd3")) {
if (tx)
i2s3_tx_ch[3] = chan;
else
i2s3_rx_ch[3] = chan;
}
return 0;
}
static void zhihe_i2s_dai_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct zhihe_i2s_priv *i2s_priv = snd_soc_dai_get_drvdata(dai);
bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
if (!strcmp(i2s_priv->drvdata->name, "i2s3-8ch-sd0")) {
if (tx)
i2s3_tx_ch[0] = NULL;
else
i2s3_rx_ch[0] = NULL;
} else if (!strcmp(i2s_priv->drvdata->name, "i2s3-8ch-sd1")) {
if (tx)
i2s3_tx_ch[1] = NULL;
else
i2s3_rx_ch[1] = NULL;
} else if (!strcmp(i2s_priv->drvdata->name, "i2s3-8ch-sd2")) {
if (tx)
i2s3_tx_ch[2] = NULL;
else
i2s3_rx_ch[2] = NULL;
} else if (!strcmp(i2s_priv->drvdata->name, "i2s3-8ch-sd3")) {
if (tx)
i2s3_tx_ch[3] = NULL;
else
i2s3_rx_ch[3] = NULL;
}
if (i2s_priv->regmap)
regmap_write(i2s_priv->regmap, I2S_ICR, 0xffffffff);
}
static int zhihe_i2s_dai_probe(struct snd_soc_dai *dai)
{
struct zhihe_i2s_priv *i2s_priv = snd_soc_dai_get_drvdata(dai);
@@ -471,6 +638,8 @@ static int zhihe_hdmi_dai_probe(struct snd_soc_dai *dai)
static const struct snd_soc_dai_ops zhihe_i2s_dai_ops = {
.probe = zhihe_i2s_dai_probe,
.startup = zhihe_i2s_dai_startup,
.shutdown = zhihe_i2s_dai_shutdown,
.trigger = zhihe_i2s_dai_trigger,
.set_fmt = zhihe_i2s_set_fmt_dai,
.hw_params = zhihe_i2s_dai_hw_params,
@@ -810,7 +979,7 @@ static int zhihe_i2s_probe(struct platform_device *pdev)
struct snd_soc_dai_driver *dai;
struct resource *res;
struct axi_dma_peripheral_config *dma_pcfg;
void __iomem *regs;
unsigned int val;
int ret;
i2s_priv = devm_kzalloc(&pdev->dev, sizeof(*i2s_priv), GFP_KERNEL);
@@ -855,17 +1024,28 @@ static int zhihe_i2s_probe(struct platform_device *pdev)
if (of_property_read_bool(np, "rx-ch-left"))
i2s_priv->rx_ch_left = true;
/* multi-channels support */
if (!of_property_read_u32(np, "multi-channels", &val))
if (val == 2 || val == 4 || val == 6 || val == 8)
i2s_priv->ch_cnt = val;
else {
dev_err(i2s_priv->dev, "Invalid channel count: %u\n", val);
return -EINVAL;
}
else
i2s_priv->ch_cnt = 2;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (strstr(i2s_priv->drvdata->name, I2S3) && i2s3_probe_flag) {
regs = NULL;
if (strstr(i2s_priv->drvdata->name, I2S3) && strcmp(i2s_priv->drvdata->name, "i2s3-8ch-sd0")) {
i2s_priv->regs = NULL;
i2s_priv->regmap = NULL;
} else {
regs = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(regs))
return PTR_ERR(regs);
i2s_priv->regs = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(i2s_priv->regs))
return PTR_ERR(i2s_priv->regs);
i2s_priv->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
i2s_priv->regmap = devm_regmap_init_mmio(&pdev->dev, i2s_priv->regs,
&zhihe_i2s_regmap_config);
if (IS_ERR(i2s_priv->regmap)) {
dev_err(&pdev->dev,
@@ -1009,9 +1189,17 @@ static int zhihe_i2s_probe(struct platform_device *pdev)
goto err_suspend;
}
if (strstr(i2s_priv->drvdata->name, I2S3))
/**
* Notice: In the I2S3 interface, SD0 serves as the master channel for
* register control, while SD1, SD2, and SD3 operate as slave channels.
*/
if (strstr(i2s_priv->drvdata->name, I2S3)) {
if (!strcmp(i2s_priv->drvdata->name, "i2s3-8ch-sd0"))
i2s3_host_regs = i2s_priv->regs;
i2s3_probe_flag++;
}
return ret;
err_suspend:
@@ -1034,6 +1222,8 @@ static void zhihe_i2s_remove(struct platform_device *pdev)
i2s3_probe_flag--;
if (!i2s_priv->regmap)
return;
if (i2s3_probe_flag == 0)
i2s3_host_regs = NULL;
}
pm_runtime_disable(&pdev->dev);

98
sound/soc/zhihe/zhihe-i2s.h
View File

@@ -297,21 +297,93 @@ enum {
#define SR_TXBUSY_Msk (0x1U << SR_TXBUSY_Pos)
#define SR_TXBUSY_STATUS SR_TXBUSY_Msk
#define SR_TFNF_Pos (2U)
#define SR_TFNF_Msk (0x1U << SR_TFNF_Pos)
#define SR_TFNF_TX_FIFO_NOT_FULL SR_TFNF_Msk
#define SR_TFNF0_Pos (2U)
#define SR_TFNF0_Msk (0x1U << SR_TFNF0_Pos)
#define SR_TFNF0_TX_FIFO_NOT_FULL SR_TFNF0_Msk
#define SR_TFE_Pos (3U)
#define SR_TFE_Msk (0x1U << SR_TFE_Pos)
#define SR_TFE_TX_FIFO_EMPTY SR_TFE_Msk
#define SR_TFE0_Pos (3U)
#define SR_TFE0_Msk (0x1U << SR_TFE0_Pos)
#define SR_TFE0_TX_FIFO_EMPTY SR_TFE0_Msk
#define SR_RFNE_Pos (4U)
#define SR_RFNE_Msk (0x1U << SR_RFNE_Pos)
#define SR_RFNE_RX_FIFO_NOT_EMPTY SR_RFNE_Msk
#define SR_RFNE0_Pos (4U)
#define SR_RFNE0_Msk (0x1U << SR_RFNE0_Pos)
#define SR_RFNE0_RX_FIFO_NOT_EMPTY SR_RFNE0_Msk
#define SR_RFF_Pos (5U)
#define SR_RFF_Msk (0x1U << SR_RFF_Pos)
#define SR_RFF_RX_FIFO_FULL SR_RFF_Msk
#define SR_RFF0_Pos (5U)
#define SR_RFF0_Msk (0x1U << SR_RFF0_Pos)
#define SR_RFF0_RX_FIFO_FULL SR_RFF0_Msk
#define SR_TFNF1_Pos (6U)
#define SR_TFNF1_Msk (0x1U << SR_TFNF1_Pos)
#define SR_TFNF1_TX_FIFO_NOT_FULL SR_TFNF1_Msk
#define SR_TFE1_Pos (7U)
#define SR_TFE1_Msk (0x1U << SR_TFE1_Pos)
#define SR_TFE1_TX_FIFO_EMPTY SR_TFE1_Msk
#define SR_RFNE1_Pos (8U)
#define SR_RFNE1_Msk (0x1U << SR_RFNE1_Pos)
#define SR_RFNE1_RX_FIFO_NOT_EMPTY SR_RFNE1_Msk
#define SR_RFF1_Pos (9U)
#define SR_RFF1_Msk (0x1U << SR_RFF1_Pos)
#define SR_RFF1_RX_FIFO_FULL SR_RFF1_Msk
#define SR_TFNF2_Pos (10U)
#define SR_TFNF2_Msk (0x1U << SR_TFNF2_Pos)
#define SR_TFNF2_TX_FIFO_NOT_FULL SR_TFNF2_Msk
#define SR_TFE2_Pos (11U)
#define SR_TFE2_Msk (0x1U << SR_TFE2_Pos)
#define SR_TFE2_TX_FIFO_EMPTY SR_TFE2_Msk
#define SR_RFNE2_Pos (12U)
#define SR_RFNE2_Msk (0x1U << SR_RFNE2_Pos)
#define SR_RFNE2_RX_FIFO_NOT_EMPTY SR_RFNE2_Msk
#define SR_RFF2_Pos (13U)
#define SR_RFF2_Msk (0x1U << SR_RFF2_Pos)
#define SR_RFF2_RX_FIFO_FULL SR_RFF2_Msk
#define SR_TFNF3_Pos (14U)
#define SR_TFNF3_Msk (0x1U << SR_TFNF3_Pos)
#define SR_TFNF3_TX_FIFO_NOT_FULL SR_TFNF3_Msk
#define SR_TFE3_Pos (15U)
#define SR_TFE3_Msk (0x1U << SR_TFE3_Pos)
#define SR_TFE3_TX_FIFO_EMPTY SR_TFE3_Msk
#define SR_RFNE3_Pos (16U)
#define SR_RFNE3_Msk (0x1U << SR_RFNE3_Pos)
#define SR_RFNE3_RX_FIFO_NOT_EMPTY SR_RFNE3_Msk
#define SR_RFF3_Pos (17U)
#define SR_RFF3_Msk (0x1U << SR_RFF3_Pos)
#define SR_RFF3_RX_FIFO_FULL SR_RFF3_Msk
#define SR_TFNF_TX_FIFO_NOT_FULL_Msk (SR_TFNF0_TX_FIFO_NOT_FULL | \
SR_TFNF1_TX_FIFO_NOT_FULL | \
SR_TFNF2_TX_FIFO_NOT_FULL | \
SR_TFNF3_TX_FIFO_NOT_FULL)
#define SR_TFNF_TX_FIFO_NOT_FULL SR_TFNF_TX_FIFO_NOT_FULL_Msk
#define SR_TFE_TX_FIFO_EMPTY_Msk (SR_TFE0_TX_FIFO_EMPTY | \
SR_TFE1_TX_FIFO_EMPTY | \
SR_TFE2_TX_FIFO_EMPTY | \
SR_TFE3_TX_FIFO_EMPTY)
#define SR_TFE_TX_FIFO_EMPTY SR_TFE_TX_FIFO_EMPTY_Msk
#define SR_RFNE_RX_FIFO_NOT_EMPTY_Msk (SR_RFNE0_RX_FIFO_NOT_EMPTY | \
SR_RFNE1_RX_FIFO_NOT_EMPTY | \
SR_RFNE2_RX_FIFO_NOT_EMPTY | \
SR_RFNE3_RX_FIFO_NOT_EMPTY)
#define SR_RFNE_RX_FIFO_NOT_EMPTY SR_RFNE_RX_FIFO_NOT_EMPTY_Msk
#define SR_RFF_RX_FIFO_FULL_Msk (SR_RFF0_RX_FIFO_FULL | \
SR_RFF1_RX_FIFO_FULL | \
SR_RFF2_RX_FIFO_FULL | \
SR_RFF3_RX_FIFO_FULL)
#define SR_RFF_RX_FIFO_FULL SR_RFF_RX_FIFO_FULL_Msk
/* IMR, offset: 0x30 */
#define IMR_WADEM_Pos (0U)
@@ -547,6 +619,7 @@ struct zhihe_i2s_priv {
struct device *dev;
struct regmap *regmap;
struct regmap *audio_cpr_regmap;
void __iomem *regs;
void __iomem *sys_csr;
struct reset_control *rst;
struct snd_dmaengine_dai_dma_data dma_params_tx;
@@ -557,6 +630,7 @@ struct zhihe_i2s_priv {
bool alolrc_high;
bool rx_ch_left;
bool hdmi_connected;
unsigned int ch_cnt;
int board;
spinlock_t zhihe_i2s_lock;

2
sound/soc/zhihe/zhihe-pcm-dma.c
View File

@@ -6,7 +6,7 @@
*
* Author: Anonymous <anonymous@zhcomputing.com>
*/
#include <linux/platform_device.h>
#include <linux/types.h>
#include <linux/module.h>

2
sound/soc/zhihe/zhihe-tdm.c
View File

@@ -158,7 +158,7 @@ static void zhihe_tdm_set_div(struct zhihe_tdm_priv *chip, u32 sample_rate,
bool is_divclk1 = false;
u32 src_clk;
u32 div0;
int i, ret;
int i;
clk_set_rate(chip->sclk, AUDIO_DIVCLK0);