OERV-BSP/kernel-zhihe-a210
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Release develop 251217

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This commit is contained in:
hongyi
2025-12-17 12:17:54 +08:00
parent 841a1afde6
commit 0cf5473f0f
8 changed files with 155 additions and 52 deletions
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11
arch/riscv/boot/dts/zhihe/a210-dev.dts
View File

@@ -1185,15 +1185,20 @@
&power_gpu {
pmic-supply = <&dvdd_gpu_reg>;
pmic-microvolt = <800000>;
};
&power_npu_wrapper {
pmic-supply = <&dvdd_npu_vip_reg>;
pmic-microvolt = <1000000>;
};
&power_vp_wrapper {
pmic-supply = <&dvdd_vp_reg>;
pmic-microvolt = <800000>;
};
&venc {
dvdd-supply = <&dvdd_vp_reg>;
};
&vdec {
dvdd-supply = <&dvdd_vp_reg>;
};

2
arch/riscv/boot/dts/zhihe/a210-platform-d2d.dtsi
View File

@@ -25,6 +25,7 @@
d2d_phy0: d2d_phy@9100000 {
compatible = "zhihe,d2d-phy";
reg = <0x00 0x09100000 0x0 0x2000>;
clocks = <&clk TOP_D2D_REF_CLK_MUX>;
};
d2d_phy1: d2d_phy@9140000 {
@@ -57,6 +58,7 @@
die1_d2d_phy0: die1_d2d_phy@2009100000 {
compatible = "zhihe,d2d-phy";
reg = <0x20 0x09100000 0x0 0x2000>;
clocks = <&clk_die1 TOP_D2D_REF_CLK_MUX>;
};
die1_d2d_phy1: die1_d2d_phy@2009140000 {

38
arch/riscv/boot/dts/zhihe/a210-soc-core-die1.dtsi
View File

@@ -32,7 +32,6 @@
cpu-tlb = "1024 4-ways";
cpu-vector = "1.0";
capacity-dmips-mhz = <768>;
dynamic-power-coefficient = <277>;
#cooling-cells = <2>;
numa-node-id = <1>;
cpu8_intc: interrupt-controller {
@@ -60,7 +59,6 @@
cpu-tlb = "1024 4-ways";
cpu-vector = "1.0";
capacity-dmips-mhz = <768>;
dynamic-power-coefficient = <277>;
#cooling-cells = <2>;
numa-node-id = <1>;
cpu9_intc: interrupt-controller {
@@ -88,7 +86,6 @@
cpu-tlb = "1024 4-ways";
cpu-vector = "1.0";
capacity-dmips-mhz = <768>;
dynamic-power-coefficient = <277>;
#cooling-cells = <2>;
numa-node-id = <1>;
cpu10_intc: interrupt-controller {
@@ -117,7 +114,6 @@
cpu-tlb = "1024 4-ways";
cpu-vector = "1.0";
capacity-dmips-mhz = <768>;
dynamic-power-coefficient = <277>;
#cooling-cells = <2>;
numa-node-id = <1>;
cpu11_intc: interrupt-controller {
@@ -147,7 +143,6 @@
cpu-tlb = "1024 4-ways";
cpu-vector = "1.0";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <854>;
#cooling-cells = <2>;
numa-node-id = <1>;
cpu12_intc: interrupt-controller {
@@ -175,7 +170,6 @@
cpu-tlb = "1024 4-ways";
cpu-vector = "1.0";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <854>;
#cooling-cells = <2>;
numa-node-id = <1>;
cpu13_intc: interrupt-controller {
@@ -203,7 +197,6 @@
cpu-tlb = "1024 4-ways";
cpu-vector = "1.0";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <854>;
#cooling-cells = <2>;
numa-node-id = <1>;
cpu14_intc: interrupt-controller {
@@ -231,7 +224,6 @@
cpu-tlb = "1024 4-ways";
cpu-vector = "1.0";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <854>;
#cooling-cells = <2>;
numa-node-id = <1>;
cpu15_intc: interrupt-controller {
@@ -437,7 +429,7 @@
reg-names = "GPU_SS_PWRAP_CLK_EN","GPU_SS_TOP_CLK_EN";
#clock-cells = <1>;
assigned-clocks = <&clk_die1 TOP_GPU_CORE_CLK_DIV>;
assigned-clock-rates = <792000000>;
assigned-clock-rates = <528000000>;
status = "okay";
};
@@ -484,8 +476,8 @@
#clock-cells = <1>;
assigned-clocks = <&clk_die1 TOP_VP_ACLK_DIV>, <&clk_die1 TOP_VP_VDEC_CCLK_DIV>,
<&clk_die1 TOP_VP_VENC_CCLK_DIV>, <&clk_die1 TOP_VP_G2D_CCLK_DIV>;
assigned-clock-rates = <880000000>, <786432000>,
<600000000>, <786432000>;
assigned-clock-rates = <528000000>, <600000000>,
<528000000>, <600000000>;
status = "okay";
};
@@ -511,7 +503,7 @@
reg-names = "NPU_CLK","NPU_TOP_CLK";
#clock-cells = <1>;
assigned-clocks = <&clk_die1 TOP_NPU_CCLK_DIV>, <&clk_die1 TOP_NPU_ACLK_DIV>;
assigned-clock-rates = <880000000>, <880000000>;
assigned-clock-rates = <472000000>, <472000000>;
status = "okay";
};
@@ -541,7 +533,7 @@
<&clk_die1 TOP_PERI_TDM_SRC_CLK_MUX>, <&clk_die1 TOP_PAD_SENSOR_VCLK0_DIV>,
<&clk_die1 TOP_PAD_SENSOR_VCLK1_DIV>, <&clk_die1 TOP_PERI_HIRES_CLK0_DIV>,
<&clk_die1 TOP_PERI_HIRES_CLK1_DIV>, <&clk_die1 TOP_PERI_EMMC_REF_CLK_DIV>,
<&clk_die1 TOP_PERI_MST_ACLK0_DIV>, <&clk_die1 TOP_PERI_MST_CLK1_DIV>,
<&clk_die1 TOP_PERI_MST_ACLK0_DIV>, <&clk_die1 TOP_PERI_MST_CLK1_DIV>,
<&clk_die1 TOP_TEE_CLK_DIV>;
assigned-clock-rates = <24000000>, <316108800>, /* peri0_timer_clk,peri1_i2s0_src_clk */
<316108800>, <316108800>, /* peri2_i2s1_src_clk,peri2_i2s2_src_clk */
@@ -633,7 +625,7 @@
reg-names = "GPU_SS_PWRAP_CLK_EN","GPU_SS_TOP_CLK_EN";
#clock-cells = <1>;
assigned-clocks = <&clk_die2 TOP_GPU_CORE_CLK_DIV>;
assigned-clock-rates = <792000000>;
assigned-clock-rates = <528000000>;
status = "okay";
};
@@ -680,8 +672,8 @@
#clock-cells = <1>;
assigned-clocks = <&clk_die2 TOP_VP_ACLK_DIV>, <&clk_die2 TOP_VP_VDEC_CCLK_DIV>,
<&clk_die2 TOP_VP_VENC_CCLK_DIV>, <&clk_die2 TOP_VP_G2D_CCLK_DIV>;
assigned-clock-rates = <880000000>, <786432000>,
<600000000>, <786432000>;
assigned-clock-rates = <528000000>, <600000000>,
<528000000>, <600000000>;
status = "okay";
};
@@ -707,7 +699,7 @@
reg-names = "NPU_CLK","NPU_TOP_CLK";
#clock-cells = <1>;
assigned-clocks = <&clk_die2 TOP_NPU_CCLK_DIV>, <&clk_die2 TOP_NPU_ACLK_DIV>;
assigned-clock-rates = <880000000>, <880000000>;
assigned-clock-rates = <472000000>, <472000000>;
status = "okay";
};
@@ -737,7 +729,7 @@
<&clk_die2 TOP_PERI_TDM_SRC_CLK_MUX>, <&clk_die2 TOP_PAD_SENSOR_VCLK0_DIV>,
<&clk_die2 TOP_PAD_SENSOR_VCLK1_DIV>, <&clk_die2 TOP_PERI_HIRES_CLK0_DIV>,
<&clk_die2 TOP_PERI_HIRES_CLK1_DIV>, <&clk_die2 TOP_TEE_CLK_DIV>,
<&clk_die2 TOP_PERI_EMMC_REF_CLK_DIV>, <&clk_die2 TOP_PERI_MST_ACLK0_DIV>,
<&clk_die2 TOP_PERI_EMMC_REF_CLK_DIV>, <&clk_die2 TOP_PERI_MST_ACLK0_DIV>,
<&clk_die2 TOP_PERI_MST_CLK1_DIV>;
assigned-clock-rates = <24000000>, <316108800>, /* peri0_timer_clk,peri1_i2s0_src_clk */
<316108800>, <316108800>, /* peri2_i2s1_src_clk,peri2_i2s2_src_clk */
@@ -829,7 +821,7 @@
reg-names = "GPU_SS_PWRAP_CLK_EN","GPU_SS_TOP_CLK_EN";
#clock-cells = <1>;
assigned-clocks = <&clk_die3 TOP_GPU_CORE_CLK_DIV>;
assigned-clock-rates = <792000000>;
assigned-clock-rates = <528000000>;
status = "okay";
};
@@ -876,8 +868,8 @@
#clock-cells = <1>;
assigned-clocks = <&clk_die3 TOP_VP_ACLK_DIV>, <&clk_die3 TOP_VP_VDEC_CCLK_DIV>,
<&clk_die3 TOP_VP_VENC_CCLK_DIV>, <&clk_die3 TOP_VP_G2D_CCLK_DIV>;
assigned-clock-rates = <880000000>, <786432000>,
<600000000>, <786432000>;
assigned-clock-rates = <528000000>, <600000000>,
<528000000>, <600000000>;
status = "okay";
};
@@ -903,7 +895,7 @@
reg-names = "NPU_CLK","NPU_TOP_CLK";
#clock-cells = <1>;
assigned-clocks = <&clk_die3 TOP_NPU_CCLK_DIV>, <&clk_die3 TOP_NPU_ACLK_DIV>;
assigned-clock-rates = <880000000>, <880000000>;
assigned-clock-rates = <472000000>, <472000000>;
status = "okay";
};
@@ -933,7 +925,7 @@
<&clk_die3 TOP_PERI_TDM_SRC_CLK_MUX>, <&clk_die3 TOP_PAD_SENSOR_VCLK0_DIV>,
<&clk_die3 TOP_PAD_SENSOR_VCLK1_DIV>, <&clk_die3 TOP_PERI_HIRES_CLK0_DIV>,
<&clk_die3 TOP_PERI_HIRES_CLK1_DIV>, <&clk_die3 TOP_TEE_CLK_DIV>,
<&clk_die3 TOP_PERI_EMMC_REF_CLK_DIV>, <&clk_die3 TOP_PERI_MST_ACLK0_DIV>,
<&clk_die3 TOP_PERI_EMMC_REF_CLK_DIV>, <&clk_die3 TOP_PERI_MST_ACLK0_DIV>,
<&clk_die3 TOP_PERI_MST_CLK1_DIV>;
assigned-clock-rates = <24000000>, <316108800>, /* peri0_timer_clk,peri1_i2s0_src_clk */
<316108800>, <316108800>, /* peri2_i2s1_src_clk,peri2_i2s2_src_clk */

16
arch/riscv/boot/dts/zhihe/a210-soc-core.dtsi
View File

@@ -36,7 +36,6 @@
cpu-tlb = "1024 4-ways";
cpu-vector = "1.0";
capacity-dmips-mhz = <768>;
dynamic-power-coefficient = <277>;
clocks = <&clk C908_CPU_TO_CDE_CLK_MUX>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
@@ -67,7 +66,6 @@
cpu-tlb = "1024 4-ways";
cpu-vector = "1.0";
capacity-dmips-mhz = <768>;
dynamic-power-coefficient = <277>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
numa-node-id = <0>;
@@ -97,7 +95,6 @@
cpu-tlb = "1024 4-ways";
cpu-vector = "1.0";
capacity-dmips-mhz = <768>;
dynamic-power-coefficient = <277>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
numa-node-id = <0>;
@@ -127,7 +124,6 @@
cpu-tlb = "1024 4-ways";
cpu-vector = "1.0";
capacity-dmips-mhz = <768>;
dynamic-power-coefficient = <277>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
numa-node-id = <0>;
@@ -158,7 +154,6 @@
cpu-tlb = "1024 4-ways";
cpu-vector = "1.0";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <854>;
clocks = <&clk C920_CPU_TO_CDE_CLK_MUX>;
operating-points-v2 = <&cluster1_opp>;
#cooling-cells = <2>;
@@ -189,7 +184,6 @@
cpu-tlb = "1024 4-ways";
cpu-vector = "1.0";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <854>;
operating-points-v2 = <&cluster1_opp>;
#cooling-cells = <2>;
numa-node-id = <0>;
@@ -219,7 +213,6 @@
cpu-tlb = "1024 4-ways";
cpu-vector = "1.0";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <854>;
operating-points-v2 = <&cluster1_opp>;
#cooling-cells = <2>;
numa-node-id = <0>;
@@ -249,7 +242,6 @@
cpu-tlb = "1024 4-ways";
cpu-vector = "1.0";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <854>;
operating-points-v2 = <&cluster1_opp>;
#cooling-cells = <2>;
numa-node-id = <0>;
@@ -582,7 +574,7 @@
reg-names = "GPU_SS_PWRAP_CLK_EN","GPU_SS_TOP_CLK_EN";
#clock-cells = <1>;
assigned-clocks = <&clk TOP_GPU_CORE_CLK_DIV>;
assigned-clock-rates = <792000000>;
assigned-clock-rates = <528000000>;
power-domains = <&power_gpu>;
status = "okay";
};
@@ -631,8 +623,8 @@
#clock-cells = <1>;
assigned-clocks = <&clk TOP_VP_ACLK_DIV>, <&clk TOP_VP_VDEC_CCLK_DIV>,
<&clk TOP_VP_VENC_CCLK_DIV>, <&clk TOP_VP_G2D_CCLK_DIV>;
assigned-clock-rates = <880000000>, <786432000>,
<600000000>, <786432000>;
assigned-clock-rates = <528000000>, <600000000>,
<528000000>, <600000000>;
power-domains = <&power_vp_wrapper>;
status = "okay";
};
@@ -660,7 +652,7 @@
reg-names = "NPU_CLK","NPU_TOP_CLK";
#clock-cells = <1>;
assigned-clocks = <&clk TOP_NPU_CCLK_DIV>, <&clk TOP_NPU_ACLK_DIV>;
assigned-clock-rates = <880000000>, <880000000>;
assigned-clock-rates = <472000000>, <472000000>;
power-domains = <&power_npu_wrapper>;
status = "okay";
};

56
arch/riscv/boot/dts/zhihe/a210-soc-peri.dtsi
View File

@@ -1097,6 +1097,44 @@
#size-cells = <0>;
status = "okay";
};
vdec_opp_table: opp_table_vdec {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <750000>;
};
opp01 {
opp-hz = /bits/ 64 <786432000>;
opp-microvolt = <800000>;
};
};
venc_opp_table: opp_table_venc {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <528000000>;
opp-microvolt = <750000>;
};
opp01 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <800000>;
};
};
g2d_opp_table: opp_table_g2d {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <750000>;
};
opp01 {
opp-hz = /bits/ 64 <786432000>;
opp-microvolt = <800000>;
};
};
vdec: vdec@0006800000 {
compatible = "zhihe,vpu-vc9000d";
@@ -1107,8 +1145,12 @@
interrupt-parent = <&intc>;
interrupts = <229>, <231>;
power-domains = <&power_vdec>;
clocks = <&clk_vp VP_VDEC_CCLK_EN>;
clock-names = "vdec_cclk";
clocks = <&clk_vp VP_VDEC_CCLK_EN>, <&clk_vp VP_VDEC_ACLK_EN>;
clock-names = "vdec_cclk", "vp_aclk";
operating-points-v2 = <&vdec_opp_table>;
aclk-freq-low = <528000000>;
aclk-freq-high = <880000000>;
cclk-threshold = <600000000>;
status = "okay";
};
@@ -1121,8 +1163,12 @@
interrupt-parent = <&intc>;
interrupts = <230>, <350>;
power-domains = <&power_venc>;
clocks = <&clk_vp VP_VENC_CCLK_EN>;
clock-names = "venc_cclk";
clocks = <&clk_vp VP_VENC_CCLK_EN>, <&clk_vp VP_VENC_ACLK_EN>;
clock-names = "venc_cclk", "vp_aclk";
operating-points-v2 = <&venc_opp_table>;
aclk-freq-low = <528000000>;
aclk-freq-high = <880000000>;
cclk-threshold = <528000000>;
status = "okay";
};
@@ -1406,7 +1452,7 @@
compatible = "zhihe,c10phy";
reg = <0x00 0x08040000 0x0 0x3C000>;
status = "okay";
};
};
};
usb20_zhihe: usb20_zhihe@08300000 {

9
arch/riscv/configs/a210_evb_defconfig
View File

@@ -51,7 +51,6 @@ CONFIG_RISCV_SBI_V01=y
CONFIG_PM=y
CONFIG_PM_DEBUG=y
CONFIG_PM_ADVANCED_DEBUG=y
CONFIG_ENERGY_MODEL=y
CONFIG_CPU_IDLE=y
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_STAT=y
@@ -222,6 +221,7 @@ CONFIG_MICROSEMI_PHY=y
CONFIG_MOTORCOMM_PHY=y
CONFIG_REALTEK_PHY=y
CONFIG_CAN_FLEXCAN=m
CONFIG_USB_RTL8152=m
CONFIG_USB_USBNET=m
# CONFIG_USB_NET_AX8817X is not set
# CONFIG_USB_NET_AX88179_178A is not set
@@ -433,6 +433,13 @@ CONFIG_RPMSG_TH1520=y
CONFIG_RPMSG_VIRTIO=y
CONFIG_A210_BMU=y
CONFIG_A210_D2D=m
CONFIG_PM_DEVFREQ=y
CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
CONFIG_DEVFREQ_GOV_PERFORMANCE=y
CONFIG_DEVFREQ_GOV_POWERSAVE=y
CONFIG_DEVFREQ_GOV_USERSPACE=y
CONFIG_DEVFREQ_GOV_PASSIVE=y
CONFIG_PM_DEVFREQ_EVENT=y
CONFIG_EXTCON=y
CONFIG_IIO=y
CONFIG_IIO_SW_DEVICE=y

18
drivers/pmdomain/zhihe/a210-pd.c
View File

@@ -226,7 +226,7 @@ static ssize_t a210_power_domain_write(struct file *file,
continue;
break;
}
if (idx == soc->num_domains) {
dev_err(dev, "no taget power domain-%s found, idx = %d, total pd numbers = %d\n",
pd_name, idx, soc->num_domains);
@@ -475,7 +475,7 @@ static int a210_init_pm_domains(struct platform_device *pdev)
for_each_child_of_node(np, child) {
if (!of_device_is_available(child))
continue;
ret = a210_add_one_domain(pdev, child);
if (ret) {
dev_err(dev, "failed to handle node %pOFn: %d\n",
@@ -529,14 +529,18 @@ static int a210_pd_parse_regulators(struct device *dev)
dev_dbg(dev, "Regulator for %s deferred %ld\n", child->name, PTR_ERR(pd_soc->regulators[id]));
return -EPROBE_DEFER;
} else {
u32 voltage;
of_property_read_u32(child, "pmic-microvolt", &voltage);
regulator_set_voltage(pd_soc->regulators[id], voltage, voltage);
u32 min_uV, max_uV;
if (of_property_read_u32(child_regulator, "regulator-min-microvolt", &min_uV) == 0 &&
of_property_read_u32(child_regulator, "regulator-max-microvolt", &max_uV) == 0) {
regulator_set_voltage(pd_soc->regulators[id], min_uV, max_uV);
dev_info(dev, "Set %s voltage range [%d, %d]uV\n",
child->name, min_uV, max_uV);
}
}
}
}
of_node_put(np);
return 0;
}
@@ -551,7 +555,7 @@ static int a210_pd_probe(struct platform_device *pdev)
return -ENOMEM;
pd_soc->dev = dev;
dev_set_drvdata(dev, pd_soc);
dev_set_drvdata(dev, pd_soc);
ret = a210_pd_parse_regulators(dev);
if (ret)

57
drivers/soc/zhihe/a210-d2d.c
View File

@@ -20,6 +20,7 @@
#include <linux/kobject.h>
#include <linux/sysfs.h>
#include <linux/bitfield.h>
#include <linux/clk.h>
#define DRIVER_NAME "a210-d2d"
@@ -107,6 +108,8 @@ struct a210_d2d_phy {
struct resource *mem_res; /* memory resource */
u32 phy_id; /* PHY ID (0 or 1) */
u32 speed; /* PHY speed */
u32 refclk; /* reference clock rate in Hz */
struct clk *clk; /* clock pointer */
struct kobject kobj; /* kobject for sysfs */
};
@@ -551,10 +554,23 @@ static ssize_t phy_base_addr_show(struct kobject *kobj,
}
static struct kobj_attribute phy_base_addr_attr = __ATTR_RO(phy_base_addr);
static ssize_t refclk_show(struct kobject *kobj,
struct kobj_attribute *attr, char *buf)
{
struct a210_d2d_phy *phy = to_phy(kobj);
if (!phy->refclk)
return sprintf(buf, "N/A\n");
return sprintf(buf, "%u Hz\n", phy->refclk);
}
static struct kobj_attribute refclk_attr = __ATTR_RO(refclk);
/* Attribute array for phy kobject */
static struct attribute *phy_attrs[] = {
&speed_attr.attr,
&phy_base_addr_attr.attr,
&refclk_attr.attr,
NULL,
};
@@ -703,6 +719,8 @@ static int a210_d2d_parse_child_nodes(struct platform_device *pdev,
/* Check if this is a d2d_phy node */
else if (of_device_is_compatible(child, "zhihe,d2d-phy")) {
struct a210_d2d_phy *phy;
struct clk *clk;
unsigned long clk_rate;
if (d2d->num_phys >= 2) {
dev_warn(dev, "Too many d2d_phy nodes, skipping %pOF\n",
@@ -739,6 +757,39 @@ static int a210_d2d_parse_child_nodes(struct platform_device *pdev,
/* Initialize speed to 0 as default */
phy->speed = 0;
/* Get clock from device tree if available */
clk = of_clk_get(child, 0);
if (IS_ERR(clk)) {
ret = PTR_ERR(clk);
/* If clock provider is not ready, defer probe */
if (ret == -EPROBE_DEFER) {
dev_info(dev, "Clock not ready for phy%d, deferring probe\n",
phy->phy_id);
of_node_put(child);
return ret;
}
/* Clock is optional for other errors, just log a message */
dev_dbg(dev, "No clock specified for phy%d (err=%d)\n",
phy->phy_id, ret);
phy->clk = NULL;
phy->refclk = 0;
} else {
phy->clk = clk;
ret = clk_prepare_enable(clk);
if (ret) {
dev_err(dev, "Failed to enable clock for phy%d: %d\n",
phy->phy_id, ret);
clk_put(clk);
of_node_put(child);
return ret;
}
clk_rate = clk_get_rate(clk);
phy->refclk = (u32)clk_rate;
dev_info(dev, "D2D phy%d: refclk=%u Hz\n",
phy->phy_id, phy->refclk);
}
dev_info(dev, "D2D phy%d: base=0x%llx\n",
phy->phy_id, (u64)res.start);
@@ -832,8 +883,12 @@ static int a210_d2d_remove(struct platform_device *pdev)
kobject_put(&d2d->ctrl[i].kobj);
}
/* Cleanup PHY kobjects */
/* Cleanup PHY kobjects and clocks */
for (i = 0; i < d2d->num_phys; i++) {
if (d2d->phy[i].clk) {
clk_disable_unprepare(d2d->phy[i].clk);
clk_put(d2d->phy[i].clk);
}
kobject_put(&d2d->phy[i].kobj);
}