driver: mipi : test tool

update mipi driver support mipi test tool

Signed-off-by: keith.zhao <keith.zhao@starfivetech.com>

drivers/gpu/drm/verisilicon/Kconfig

@@ -67,4 +67,12 @@ config STARFIVE_DSI
 	  enable MIPI DSI on VIC7110 based SoC, you should
 	  select this option.
 
+config STARFIVE_MIPI_TOOL_TEST
+	bool "Starfive MIPI TOOL USED"
+	depends on STARFIVE_DSI
+	default n
+	help
+	  This selects use to config the dsi timming parameters produced by Starfive MIPI tool.
+	  if no config, the mipi controller will use the default way to handle it.
+
 source "drivers/gpu/drm/verisilicon/adv7511/Kconfig"

drivers/gpu/drm/verisilicon/starfive_drm_dsi.c

@@ -746,7 +746,13 @@ static int cdns_dsi_mode2cfg(struct cdns_dsi *dsi,
 					  bpp, 0);
 	dsi_cfg->hfp = dpi_to_dsi_timing(mode_to_dpi_hfp(mode, mode_valid_check),
 					 bpp, DSI_HFP_FRAME_OVERHEAD);
-
+#ifdef CONFIG_STARFIVE_MIPI_TOOL_TEST
+	//update dsi timming
+	dsi_cfg->hfp = mode->dsi_hfp - DSI_HFP_FRAME_OVERHEAD;
+	dsi_cfg->hact = mode->dsi_hact;
+	dsi_cfg->hsa = mode->dsi_hsa - DSI_HSA_FRAME_OVERHEAD;
+	dsi_cfg->hbp = mode->dsi_hbp - DSI_HBP_FRAME_OVERHEAD;
+#endif
 	return 0;
 }
 
@@ -826,7 +832,14 @@ static int cdns_dsi_check_conf(struct cdns_dsi *dsi,
 	ret = cdns_dsi_mode2cfg(dsi, mode, dsi_cfg, mode_valid_check);
 	if (ret)
 		return ret;
+#ifdef CONFIG_STARFIVE_MIPI_TOOL_TEST
+	phy_mipi_dphy_get_default_config_for_hs_clk_rate(mode->crtc_clock * 1000,
+				mipi_dsi_pixel_format_to_bpp(output->dev->format),
+				nlanes, mode->dsi_bitrate, phy_cfg);
 
+	phy_cfg->hs_clk_rate = mode->dsi_bitrate;
+
+#else
 	phy_mipi_dphy_get_default_config(mode->crtc_clock * 1000,
 					 mipi_dsi_pixel_format_to_bpp(output->dev->format),
 					 nlanes, phy_cfg);
@@ -835,6 +848,8 @@ static int cdns_dsi_check_conf(struct cdns_dsi *dsi,
 	if (ret)
 		return ret;
 
+#endif
+
 	ret = phy_validate(dsi->dphy, PHY_MODE_MIPI_DPHY, 0, &output->phy_opts);
 	if (ret)
 		return ret;
@@ -1176,6 +1191,16 @@ static void cdns_dsi_bridge_enable(struct drm_bridge *bridge)
 
 	tmp = readl(dsi->regs + MCTL_MAIN_EN) | IF_EN(input->id);
 	writel(tmp, dsi->regs + MCTL_MAIN_EN);
+
+#ifdef CONFIG_STARFIVE_MIPI_TOOL_TEST
+	tmp = readl(dsi->regs + VID_MODE_STS);
+	printk("%s,VID_MODE_STS %08x************************\n", __func__, tmp);
+	tmp = readl(dsi->regs + MCTL_LANE_STS);
+	printk("%s,MCTL_LANE_STS %08x************************\n", __func__, tmp);
+	tmp = readl(dsi->regs + MCTL_DPHY_ERR);
+	printk("%s,MCTL_DPHY_ERR %08x************************\n", __func__, tmp);
+#endif
+
 }
 
 static const struct drm_bridge_funcs cdns_dsi_bridge_funcs = {

drivers/gpu/drm/verisilicon/starfive_drm_seeedpanel.c

@@ -323,33 +323,136 @@ static int seeed_panel_enable(struct drm_panel *panel)
 	return 0;
 }
 
+#ifdef CONFIG_STARFIVE_MIPI_TOOL_TEST
+static int display_parse_dt(struct device *dev, struct drm_display_mode *mode)
+{
+	struct device_node *np = dev->of_node;
+
+	if (of_property_read_u32(np, "clock", &mode->clock)) {
+		dev_err(dev, "Failed to read clock property\n");
+		return -EINVAL;
+	}
+
+	if (of_property_read_u16(np, "hdisplay", &mode->hdisplay)) {
+		dev_err(dev, "Failed to read hdisplay property\n");
+		return -EINVAL;
+	}
+
+	if (of_property_read_u16(np, "hsync_start", &mode->hsync_start)) {
+		dev_err(dev, "Failed to read hsync_start property\n");
+		return -EINVAL;
+	}
+
+	if (of_property_read_u16(np, "hsync_end", &mode->hsync_end)) {
+		dev_err(dev, "Failed to read hsync_end property\n");
+		return -EINVAL;
+	}
+
+	if (of_property_read_u16(np, "htotal", &mode->htotal)) {
+		dev_err(dev, "Failed to read htotal property\n");
+		return -EINVAL;
+	}
+
+	if (of_property_read_u16(np, "vdisplay", &mode->vdisplay)) {
+		dev_err(dev, "Failed to read vdisplay property\n");
+		return -EINVAL;
+	}
+
+	if (of_property_read_u16(np, "vsync_start", &mode->vsync_start)) {
+		dev_err(dev, "Failed to read vsync_start property\n");
+		return -EINVAL;
+	}
+
+	if (of_property_read_u16(np, "vsync_end", &mode->vsync_end)) {
+		dev_err(dev, "Failed to read vsync_end property\n");
+		return -EINVAL;
+	}
+
+	if (of_property_read_u16(np, "vtotal", &mode->vtotal)) {
+		dev_err(dev, "Failed to read vtotal property\n");
+		return -EINVAL;
+	}
+
+	if (of_property_read_u16(np, "dsi_dlanes", &mode->dsi_dlanes)) {
+		dev_err(dev, "Failed to read dsi_dlanes property\n");
+		return -EINVAL;
+	}
+
+	if (of_property_read_u32(np, "dsi_bitrate", &mode->dsi_bitrate)) {
+		dev_err(dev, "Failed to read dsi_bitrate property\n");
+		return -EINVAL;
+	}
+
+	if (of_property_read_u16(np, "dsi_hsa", &mode->dsi_hsa)) {
+		dev_err(dev, "Failed to read dsi_hsa property\n");
+		return -EINVAL;
+	}
+
+	if (of_property_read_u16(np, "dsi_hbp", &mode->dsi_hbp)) {
+		dev_err(dev, "Failed to read dsi_hbp property\n");
+		return -EINVAL;
+	}
+
+	if (of_property_read_u16(np, "dsi_hfp", &mode->dsi_hfp)) {
+		dev_err(dev, "Failed to read dsi_hfp property\n");
+		return -EINVAL;
+	}
+
+	if (of_property_read_u16(np, "dsi_hact", &mode->dsi_hact)) {
+		dev_err(dev, "Failed to read dsi_hact property\n");
+		return -EINVAL;
+	}
+
+	dev_info(dev, "Display config parsed successfully:\n");
+	dev_info(dev, "clock: %u\n", mode->clock);
+	dev_info(dev, "hdisplay: %u\n", mode->hdisplay);
+	dev_info(dev, "hsync_start: %u\n", mode->hsync_start);
+	dev_info(dev, "hsync_end: %u\n", mode->hsync_end);
+	dev_info(dev, "htotal: %u\n", mode->htotal);
+	dev_info(dev, "vdisplay: %u\n", mode->vdisplay);
+	dev_info(dev, "vsync_start: %u\n", mode->vsync_start);
+	dev_info(dev, "vsync_end: %u\n", mode->vsync_end);
+	dev_info(dev, "vtotal: %u\n", mode->vtotal);
+	dev_info(dev, "dsi_dlanes: %u\n", mode->dsi_dlanes);
+	dev_info(dev, "dsi_bitrate: %u\n", mode->dsi_bitrate);
+	dev_info(dev, "dsi_hsa: %u\n", mode->dsi_hsa);
+	dev_info(dev, "dsi_hbp: %u\n", mode->dsi_hbp);
+	dev_info(dev, "dsi_hfp: %u\n", mode->dsi_hfp);
+	dev_info(dev, "dsi_hact: %u\n", mode->dsi_hact);
+
+    return 0;
+}
+#endif
 static int seeed_panel_get_modes(struct drm_panel *panel,
 				struct drm_connector *connector)
 {
-	unsigned int i, num = 0;
+	unsigned int num = 0;
 	static const u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
+	struct drm_display_mode *mode;
 
-	for (i = 0; i < ARRAY_SIZE(seeed_panel_modes); i++) {
-		const struct drm_display_mode *m = &seeed_panel_modes[i];
-		struct drm_display_mode *mode;
+#ifdef CONFIG_STARFIVE_MIPI_TOOL_TEST
+	struct drm_display_mode mode_temp;
 
-		mode = drm_mode_duplicate(connector->dev, m);
-		if (!mode) {
-			dev_err(panel->dev, "failed to add mode %ux%u@%u\n",
-				m->hdisplay, m->vdisplay,
-				drm_mode_vrefresh(m));
-			continue;
-		}
+	memset(&mode_temp, 0, sizeof(mode_temp));
+	display_parse_dt(panel->dev, &mode_temp);
 
-		mode->type |= DRM_MODE_TYPE_DRIVER;
-
-		if (i == 0)
-			mode->type |= DRM_MODE_TYPE_PREFERRED;
-
-		drm_mode_set_name(mode);
-		drm_mode_probed_add(connector, mode);
-		num++;
+	mode = drm_mode_duplicate(connector->dev, &mode_temp);
+	if (!mode) {
+		return 0;
 	}
+#else
+	mode = drm_mode_duplicate(connector->dev, &seeed_panel_modes[0]);
+	if (!mode) {
+		return 0;
+	}
+#endif
+
+	mode->type |= DRM_MODE_TYPE_DRIVER;
+	mode->type |= DRM_MODE_TYPE_PREFERRED;
+
+	drm_mode_set_name(mode);
+	drm_mode_probed_add(connector, mode);
+	num++;
 
 	connector->display_info.bpc = 8;
 	connector->display_info.width_mm = 154;

drivers/gpu/drm/verisilicon/vs_dc.c

@@ -811,16 +811,14 @@ static bool vs_dc_mode_fixup(struct device *dev,
 				  struct drm_display_mode *adjusted_mode)
 {
 
-#if 1
-	;//printk("====> %s, %d--pix_clk.\n", __func__, __LINE__);
-#else
 	struct vs_dc *dc = dev_get_drvdata(dev);
-
-	long clk_rate;
-	if (dc->pix_clk) {
-		clk_rate = clk_round_rate(dc->pix_clk,
-					  adjusted_mode->clock * 1000);
-		adjusted_mode->clock = DIV_ROUND_UP(clk_rate, 1000);
+#ifdef CONFIG_STARFIVE_MIPI_TOOL_TEST
+	if (mode->dsi_hact) {
+		long clk_rate;
+		clk_rate = clk_round_rate(dc->dc8200_pix0, mode->clock * 1000 + 1000);
+		clk_rate += 1000;
+		adjusted_mode->clock = clk_rate/1000;
+		printk("adjusted_mode->clock = %ld\n", adjusted_mode->clock);
 	}
 #endif
 

drivers/phy/phy-core-mipi-dphy.c

@@ -88,6 +88,18 @@ int phy_mipi_dphy_get_default_config(unsigned long pixel_clock,
 }
 EXPORT_SYMBOL(phy_mipi_dphy_get_default_config);
 
+int phy_mipi_dphy_get_default_config_for_hs_clk_rate(unsigned long pixel_clock,
+				     unsigned int bpp,
+				     unsigned int lanes,
+				     unsigned long long hs_clk_rate,
+				     struct phy_configure_opts_mipi_dphy *cfg)
+{
+	return phy_mipi_dphy_calc_config(pixel_clock, bpp, lanes, hs_clk_rate, cfg);
+
+}
+EXPORT_SYMBOL(phy_mipi_dphy_get_default_config_for_hs_clk_rate);
+
+
 int phy_mipi_dphy_get_default_config_for_hsclk(unsigned long long hs_clk_rate,
 					       unsigned int lanes,
 					       struct phy_configure_opts_mipi_dphy *cfg)

include/drm/drm_modes.h

@@ -266,6 +266,14 @@ struct drm_display_mode {
 	u16 vsync_end;
 	u16 vtotal;
 	u16 vscan;
+#ifdef CONFIG_STARFIVE_MIPI_TOOL_TEST
+	u32 dsi_bitrate;
+	u16 dsi_dlanes;
+	u16 dsi_hsa;
+	u16 dsi_hbp;
+	u16 dsi_hfp;
+	u16 dsi_hact;
+#endif
 	/**
 	 * @flags:
 	 *

include/linux/phy/phy-mipi-dphy.h

@@ -279,9 +279,16 @@ int phy_mipi_dphy_get_default_config(unsigned long pixel_clock,
 				     unsigned int bpp,
 				     unsigned int lanes,
 				     struct phy_configure_opts_mipi_dphy *cfg);
+
 int phy_mipi_dphy_get_default_config_for_hsclk(unsigned long long hs_clk_rate,
 					       unsigned int lanes,
 					       struct phy_configure_opts_mipi_dphy *cfg);
+
+int phy_mipi_dphy_get_default_config_for_hs_clk_rate(unsigned long pixel_clock,
+						     unsigned int bpp,
+						     unsigned int lanes,
+						     unsigned long long hs_clk_rate,
+						     struct phy_configure_opts_mipi_dphy *cfg);
 int phy_mipi_dphy_config_validate(struct phy_configure_opts_mipi_dphy *cfg);
 
 #endif /* __PHY_MIPI_DPHY_H_ */