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reset: spacemit-k1x: add RESET_COMBO_PHY reset signal

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USB3 and PCIE0 of k1x shares a combo phy. BIT(8) of APMU register
APMU_PCIE_CLK_RES_CTRL_0 is designed for USB3 to reset the combo phy
without resetting the PCIE0.

Change-Id: I1935d228b1c4c8d81fd280a8dc245806539d7104
Signed-off-by: Junzhong Pan <junzhong.pan@spacemit.com>
This commit is contained in:
Junzhong Pan
2025-06-18 14:58:15 +08:00
committed by 张猛
parent 8be331c040
commit defacd6ae1
2 changed files with 45 additions and 44 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/reset/reset-spacemit-k1x.c
View File

@@ -277,6 +277,7 @@ static const struct spacemit_reset_signal
[RESET_SDH1] = { APMU_SDH1_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU }, [RESET_SDH1] = { APMU_SDH1_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU },
[RESET_USB_AXI] = { APMU_USB_CLK_RES_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU }, [RESET_USB_AXI] = { APMU_USB_CLK_RES_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU },
[RESET_USBP1_AXI] = { APMU_USB_CLK_RES_CTRL, BIT(4), BIT(4), 0, RST_BASE_TYPE_APMU }, [RESET_USBP1_AXI] = { APMU_USB_CLK_RES_CTRL, BIT(4), BIT(4), 0, RST_BASE_TYPE_APMU },
[RESET_COMBO_PHY] = { APMU_PCIE_CLK_RES_CTRL_0, BIT(8), 0, BIT(8), RST_BASE_TYPE_APMU },
[RESET_USB3_0] = { APMU_USB_CLK_RES_CTRL, BIT(9)|BIT(10)|BIT(11), BIT(9)|BIT(10)|BIT(11), 0, RST_BASE_TYPE_APMU }, [RESET_USB3_0] = { APMU_USB_CLK_RES_CTRL, BIT(9)|BIT(10)|BIT(11), BIT(9)|BIT(10)|BIT(11), 0, RST_BASE_TYPE_APMU },
[RESET_QSPI] = { APMU_QSPI_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU }, [RESET_QSPI] = { APMU_QSPI_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU },
[RESET_QSPI_BUS] = { APMU_QSPI_CLK_RES_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU }, [RESET_QSPI_BUS] = { APMU_QSPI_CLK_RES_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU },
@@ -570,4 +571,3 @@ out:
} }
CLK_OF_DECLARE(k1x_reset, "spacemit,k1x-reset", spacemit_reset_init); CLK_OF_DECLARE(k1x_reset, "spacemit,k1x-reset", spacemit_reset_init);

87
include/dt-bindings/reset/spacemit-k1x-reset.h
View File

@@ -84,54 +84,55 @@
#define RESET_SDH1 73 #define RESET_SDH1 73
#define RESET_USB_AXI 74 #define RESET_USB_AXI 74
#define RESET_USBP1_AXI 75 #define RESET_USBP1_AXI 75
#define RESET_USB3_0 76 #define RESET_COMBO_PHY 76
#define RESET_QSPI 77 #define RESET_USB3_0 77
#define RESET_QSPI_BUS 78 #define RESET_QSPI 78
#define RESET_DMA 79 #define RESET_QSPI_BUS 79
#define RESET_AES 80 #define RESET_DMA 80
#define RESET_VPU 81 #define RESET_AES 81
#define RESET_GPU 82 #define RESET_VPU 82
#define RESET_SDH2 83 #define RESET_GPU 83
#define RESET_MC 84 #define RESET_SDH2 84
#define RESET_EM_AXI 85 #define RESET_MC 85
#define RESET_EM 86 #define RESET_EM_AXI 86
#define RESET_AUDIO_SYS 87 #define RESET_EM 87
#define RESET_HDMI 88 #define RESET_AUDIO_SYS 88
#define RESET_PCIE0 89 #define RESET_HDMI 89
#define RESET_PCIE1 90 #define RESET_PCIE0 90
#define RESET_PCIE2 91 #define RESET_PCIE1 91
#define RESET_EMAC0 92 #define RESET_PCIE2 92
#define RESET_EMAC1 93 #define RESET_EMAC0 93
#define RESET_EMAC1 94
//APBC2 //APBC2
#define RESET_SEC_UART1 94 #define RESET_SEC_UART1 95
#define RESET_SEC_SSP2 95 #define RESET_SEC_SSP2 96
#define RESET_SEC_TWSI3 96 #define RESET_SEC_TWSI3 97
#define RESET_SEC_RTC 97 #define RESET_SEC_RTC 98
#define RESET_SEC_TIMERS0 98 #define RESET_SEC_TIMERS0 99
#define RESET_SEC_KPC 99 #define RESET_SEC_KPC 100
#define RESET_SEC_GPIO 100 #define RESET_SEC_GPIO 101
#define RESET_RCPU_HDMIAUDIO 101 #define RESET_RCPU_HDMIAUDIO 102
#define RESET_RCPU_CAN 102 #define RESET_RCPU_CAN 103
#define RESET_RCPU_I2C0 103 #define RESET_RCPU_I2C0 104
#define RESET_RCPU_SSP0 104 #define RESET_RCPU_SSP0 105
#define RESET_RCPU_IR 105 #define RESET_RCPU_IR 106
#define RESET_RCPU_UART0 106 #define RESET_RCPU_UART0 107
#define RESET_RCPU_UART1 107 #define RESET_RCPU_UART1 108
#define RESET_RCPU2_PWM0 108 #define RESET_RCPU2_PWM0 109
#define RESET_RCPU2_PWM1 109 #define RESET_RCPU2_PWM1 110
#define RESET_RCPU2_PWM2 110 #define RESET_RCPU2_PWM2 111
#define RESET_RCPU2_PWM3 111 #define RESET_RCPU2_PWM3 112
#define RESET_RCPU2_PWM4 112 #define RESET_RCPU2_PWM4 113
#define RESET_RCPU2_PWM5 113 #define RESET_RCPU2_PWM5 114
#define RESET_RCPU2_PWM6 114 #define RESET_RCPU2_PWM6 115
#define RESET_RCPU2_PWM7 115 #define RESET_RCPU2_PWM7 116
#define RESET_RCPU2_PWM8 116 #define RESET_RCPU2_PWM8 117
#define RESET_RCPU2_PWM9 117 #define RESET_RCPU2_PWM9 118
#define RESET_NUMBER 118 #define RESET_NUMBER 119
#endif /* __DT_BINDINGS_RESET_SAPCEMIT_K1X_H__ */ #endif /* __DT_BINDINGS_RESET_SAPCEMIT_K1X_H__ */